[PATCH 0/4] xilinx: mbv: Prepare MBV for CI

[PATCH 0/4] xilinx: mbv: Prepare MBV for CI

[Michal Simek]

Hi,

this patch series is fixing issues reported by dt-schema and all 4
combinations are tested on Qemu to be able to wire them in CI.
U-Boot hooks changes are sent here
https://lore.kernel.org/r/82725079ee90362468fe8096db24ef2959725af9.1753181505.git.michal.simek@amd.com

Thanks,
Michal


Michal Simek (4):
  xilinx: mbv: Disable OF_HAS_PRIOR_STAGE
  xilinx: mbv: Add missing mmu-type cpu property
  xilinx: mbv: Fix dt properties in interrupt controller node
  xilinx: mbv: Use separate DTB for binman nodes

 arch/riscv/dts/Makefile              |  1 +
 arch/riscv/dts/xilinx-binman.dts     | 12 ++++++++++++
 arch/riscv/dts/xilinx-mbv32.dts      |  8 ++++----
 arch/riscv/dts/xilinx-mbv64.dts      |  8 ++++----
 board/xilinx/mbv/Kconfig             |  1 -
 configs/xilinx_mbv32_defconfig       |  1 +
 configs/xilinx_mbv32_smode_defconfig |  1 +
 configs/xilinx_mbv64_defconfig       |  1 +
 configs/xilinx_mbv64_smode_defconfig |  1 +
 9 files changed, 25 insertions(+), 9 deletions(-)
 create mode 100644 arch/riscv/dts/xilinx-binman.dts

-- 
2.43.0

base-commit: 063b2e618afb05a32d66218f3631a5f23b30ea3e
branch: debian-sent3

[PATCH 1/4] xilinx: mbv: Disable OF_HAS_PRIOR_STAGE

[Michal Simek]

There is no reason to use OF_BOARD for MBV because reduced DT is used by
SPL and full DT is passed via u-boot.img or u-boot.itb. There is no reason
to pick up DTB from certain address.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 board/xilinx/mbv/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig
index c52ba1870b0b..68acd8955ae8 100644
--- a/board/xilinx/mbv/Kconfig
+++ b/board/xilinx/mbv/Kconfig
@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS
 	imply SPL_RAM_DEVICE
 	imply CMD_SBI
 	imply CMD_PING
-	imply OF_HAS_PRIOR_STAGE
 
 source "board/xilinx/Kconfig"
 
-- 
2.43.0

Re: [PATCH 1/4] xilinx: mbv: Disable OF_HAS_PRIOR_STAGE

[Leo Liang]

On Tue, Jul 22, 2025 at 01:03:43PM +0200, Michal Simek wrote:
> There is no reason to use OF_BOARD for MBV because reduced DT is used by
> SPL and full DT is passed via u-boot.img or u-boot.itb. There is no reason
> to pick up DTB from certain address.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>  board/xilinx/mbv/Kconfig | 1 -
>  1 file changed, 1 deletion(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

[PATCH 2/4] xilinx: mbv: Add missing mmu-type cpu property

[Michal Simek]

OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/riscv/dts/xilinx-mbv32.dts | 3 ++-
 arch/riscv/dts/xilinx-mbv64.dts | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 4050ce2f051d..96e428062442 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv32imafdc";
+			mmu-type = "riscv,sv39";
 			i-cache-size = <32768>;
 			d-cache-size = <32768>;
 			clock-frequency = <100000000>;
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 4d65d338ecb6..5a989c1697e4 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
 			i-cache-size = <32768>;
 			d-cache-size = <32768>;
 			clock-frequency = <100000000>;
-- 
2.43.0

Re: [PATCH 2/4] xilinx: mbv: Add missing mmu-type cpu property

[Leo Liang]

On Tue, Jul 22, 2025 at 01:03:44PM +0200, Michal Simek wrote:
> OpenSBI expects mmu-type to be present in DT that's why add it. Without it
> OpenSBI disable CPU node which ends up in not working boot.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>  arch/riscv/dts/xilinx-mbv32.dts | 3 ++-
>  arch/riscv/dts/xilinx-mbv64.dts | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

[PATCH 3/4] xilinx: mbv: Fix dt properties in interrupt controller node

[Michal Simek]

Properties didn't match dt binding that's why should be fixed.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

Binding has been sent here:
https://lore.kernel.org/r/6ddaf6f1e3748cdeda2e2e32ee69343a06c60dcb.1753166980.git.michal.simek@amd.com
but it is used for more then 15 years unchanged.
---
 arch/riscv/dts/xilinx-mbv32.dts | 3 ++-
 arch/riscv/dts/xilinx-mbv64.dts | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 96e428062442..b426510f3434 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -71,7 +71,8 @@
 			interrupt-controller;
 			interrupt-parent = <&cpu0_intc>;
 			#interrupt-cells = <2>;
-			kind-of-intr = <0>;
+			xlnx,num-intr-inputs = <2>;
+			xlnx,kind-of-intr = <0>;
 		};
 
 		xlnx_timer0: timer@41c00000 {
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 5a989c1697e4..3762def29f9a 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -71,7 +71,8 @@
 			interrupt-controller;
 			interrupt-parent = <&cpu0_intc>;
 			#interrupt-cells = <2>;
-			kind-of-intr = <0>;
+			xlnx,num-intr-inputs = <2>;
+			xlnx,kind-of-intr = <0>;
 		};
 
 		xlnx_timer0: timer@41c00000 {
-- 
2.43.0

Re: [PATCH 3/4] xilinx: mbv: Fix dt properties in interrupt controller node

[Leo Liang]

On Tue, Jul 22, 2025 at 01:03:45PM +0200, Michal Simek wrote:
> Properties didn't match dt binding that's why should be fixed.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
> Binding has been sent here:
> https://lore.kernel.org/r/6ddaf6f1e3748cdeda2e2e32ee69343a06c60dcb.1753166980.git.michal.simek@amd.com
> but it is used for more then 15 years unchanged.
> ---
>  arch/riscv/dts/xilinx-mbv32.dts | 3 ++-
>  arch/riscv/dts/xilinx-mbv64.dts | 3 ++-
>  2 files changed, 4 insertions(+), 2 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

[PATCH 4/4] xilinx: mbv: Use separate DTB for binman nodes

[Michal Simek]

The commit d92fdb60677b ("binman: Add option for pointing to separate
description") added support for separating binman description to own file
not the be the part of DT for OS.
The main reason is that binman is not passing dt schema validation that's
why want to keep it separated.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/riscv/dts/Makefile              |  1 +
 arch/riscv/dts/xilinx-binman.dts     | 12 ++++++++++++
 arch/riscv/dts/xilinx-mbv32.dts      |  2 --
 arch/riscv/dts/xilinx-mbv64.dts      |  2 --
 configs/xilinx_mbv32_defconfig       |  1 +
 configs/xilinx_mbv32_smode_defconfig |  1 +
 configs/xilinx_mbv64_defconfig       |  1 +
 configs/xilinx_mbv64_smode_defconfig |  1 +
 8 files changed, 17 insertions(+), 4 deletions(-)
 create mode 100644 arch/riscv/dts/xilinx-binman.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 2b10c2d6c019..68dfe9ce56d3 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -14,6 +14,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
 dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
 dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
+dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
 dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
 
 include $(srctree)/scripts/Makefile.dts
diff --git a/arch/riscv/dts/xilinx-binman.dts b/arch/riscv/dts/xilinx-binman.dts
new file mode 100644
index 000000000000..715080ed763c
--- /dev/null
+++ b/arch/riscv/dts/xilinx-binman.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * binman file for AMD MicroBlaze V
+ *
+ * (C) Copyright 2025, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index b426510f3434..f7a3e076fd50 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -9,8 +9,6 @@
 
 /dts-v1/;
 
-#include "binman.dtsi"
-
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 3762def29f9a..e6235ed2f525 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -9,8 +9,6 @@
 
 /dts-v1/;
 
-#include "binman.dtsi"
-
 / {
 	#address-cells = <2>;
 	#size-cells = <2>;
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 7dde2fc0a8f1..d2483b5089ce 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -39,5 +39,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_XILINX_UARTLITE=y
 CONFIG_XILINX_TIMER=y
 # CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_GZIP=y
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index b96b02c6125e..930a1e9f83b9 100644
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -43,5 +43,6 @@ CONFIG_XILINX_UARTLITE=y
 # CONFIG_RISCV_TIMER is not set
 CONFIG_XILINX_TIMER=y
 # CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_GZIP=y
diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig
index 77fcf4d68651..c0f748c72c6a 100644
--- a/configs/xilinx_mbv64_defconfig
+++ b/configs/xilinx_mbv64_defconfig
@@ -40,5 +40,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_XILINX_UARTLITE=y
 CONFIG_XILINX_TIMER=y
 # CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_GZIP=y
diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig
index e53c0771baf6..9817acac9dad 100644
--- a/configs/xilinx_mbv64_smode_defconfig
+++ b/configs/xilinx_mbv64_smode_defconfig
@@ -44,5 +44,6 @@ CONFIG_XILINX_UARTLITE=y
 # CONFIG_RISCV_TIMER is not set
 CONFIG_XILINX_TIMER=y
 # CONFIG_BINMAN_FDT is not set
+CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
 CONFIG_PANIC_HANG=y
 CONFIG_SPL_GZIP=y
-- 
2.43.0

Re: [PATCH 4/4] xilinx: mbv: Use separate DTB for binman nodes

[Leo Liang]

On Tue, Jul 22, 2025 at 01:03:46PM +0200, Michal Simek wrote:
> The commit d92fdb60677b ("binman: Add option for pointing to separate
> description") added support for separating binman description to own file
> not the be the part of DT for OS.
> The main reason is that binman is not passing dt schema validation that's
> why want to keep it separated.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
>  arch/riscv/dts/Makefile              |  1 +
>  arch/riscv/dts/xilinx-binman.dts     | 12 ++++++++++++
>  arch/riscv/dts/xilinx-mbv32.dts      |  2 --
>  arch/riscv/dts/xilinx-mbv64.dts      |  2 --
>  configs/xilinx_mbv32_defconfig       |  1 +
>  configs/xilinx_mbv32_smode_defconfig |  1 +
>  configs/xilinx_mbv64_defconfig       |  1 +
>  configs/xilinx_mbv64_smode_defconfig |  1 +
>  8 files changed, 17 insertions(+), 4 deletions(-)
>  create mode 100644 arch/riscv/dts/xilinx-binman.dts

Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>

Re: [PATCH 0/4] xilinx: mbv: Prepare MBV for CI

[Michal Simek]

On 7/22/25 13:03, Michal Simek wrote:
> Hi,
> 
> this patch series is fixing issues reported by dt-schema and all 4
> combinations are tested on Qemu to be able to wire them in CI.
> U-Boot hooks changes are sent here
> https://lore.kernel.org/r/82725079ee90362468fe8096db24ef2959725af9.1753181505.git.michal.simek@amd.com
> 
> Thanks,
> Michal
> 
> 
> Michal Simek (4):
>    xilinx: mbv: Disable OF_HAS_PRIOR_STAGE
>    xilinx: mbv: Add missing mmu-type cpu property
>    xilinx: mbv: Fix dt properties in interrupt controller node
>    xilinx: mbv: Use separate DTB for binman nodes
> 
>   arch/riscv/dts/Makefile              |  1 +
>   arch/riscv/dts/xilinx-binman.dts     | 12 ++++++++++++
>   arch/riscv/dts/xilinx-mbv32.dts      |  8 ++++----
>   arch/riscv/dts/xilinx-mbv64.dts      |  8 ++++----
>   board/xilinx/mbv/Kconfig             |  1 -
>   configs/xilinx_mbv32_defconfig       |  1 +
>   configs/xilinx_mbv32_smode_defconfig |  1 +
>   configs/xilinx_mbv64_defconfig       |  1 +
>   configs/xilinx_mbv64_smode_defconfig |  1 +
>   9 files changed, 25 insertions(+), 9 deletions(-)
>   create mode 100644 arch/riscv/dts/xilinx-binman.dts
> 

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs