[PATCH v2 0/5] target/riscv: Fix no-TCG build

[PATCH v2 0/5] target/riscv: Fix no-TCG build

[Zephyr Li]

This series fixes the riscv64-softmmu --disable-tcg build by keeping
TCG-only files and code out of no-TCG builds, while keeping common
helpers available for non-TCG configurations.

The first patches move common helpers out of TCG-only helper files. The
later patches reject x-misa-w when TCG is unavailable, provide a no-TCG
stub for riscv_cpu_validate_set_extensions(), and build RISC-V TCG-only
sources only when TCG is enabled.

Changes in v2:
- Split the original patch into smaller logical patches.
- Drop the unused tcg/tcg.h include.
- Add a no-TCG stub for riscv_cpu_validate_set_extensions().
- Keep x-misa-w rejected during CPU realize when TCG is unavailable.

Testing:
- riscv64-softmmu --enable-kvm --disable-tcg --enable-debug builds
  successfully.
- riscv64-softmmu --enable-debug builds successfully.
- qemu-system-riscv64 -M virt,accel=qtest -cpu rv64,x-misa-w=true \
  -S -nographic reports "x-misa-w requires TCG".

Zephyr Li (5):
  target/riscv: Remove unused tcg/tcg.h include
  target/riscv: Move fflags helpers to common code
  target/riscv: Move riscv_raise_exception() to common code
  target/riscv: Reject x-misa-w without TCG
  target/riscv: Build TCG-only code only with TCG

 target/riscv/cpu.c         |  8 +++++-
 target/riscv/cpu_helper.c  | 53 ++++++++++++++++++++++++++++++++++++++
 target/riscv/csr.c         | 11 ++++++--
 target/riscv/fpu_helper.c  | 27 -------------------
 target/riscv/meson.build   |  9 ++++---
 target/riscv/op_helper.c   | 15 -----------
 target/riscv/tcg/tcg-cpu.h | 10 +++++++
 7 files changed, 85 insertions(+), 48 deletions(-)

-- 
2.43.0

[PATCH v2 1/5] target/riscv: Remove unused tcg/tcg.h include

[Zephyr Li]

Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
---
 target/riscv/cpu.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 862834b480..1dea66972d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -36,7 +36,6 @@
 #include "system/tcg.h"
 #include "kvm/kvm_riscv.h"
 #include "tcg/tcg-cpu.h"
-#include "tcg/tcg.h"
 
 /* RISC-V CPU definitions */
 static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
-- 
2.43.0

[PATCH v2 2/5] target/riscv: Move fflags helpers to common code

[Zephyr Li]

Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
---
 target/riscv/cpu_helper.c | 28 ++++++++++++++++++++++++++++
 target/riscv/fpu_helper.c | 27 ---------------------------
 2 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 17305e1bb7..678c106ae5 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,6 +21,7 @@
 #include "qemu/log.h"
 #include "qemu/main-loop.h"
 #include "cpu.h"
+#include "fpu/softfloat.h"
 #include "internals.h"
 #include "pmu.h"
 #include "exec/cputlb.h"
@@ -38,6 +39,33 @@
 #include "pmp.h"
 #include "qemu/plugin.h"
 
+target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
+{
+    int soft = get_float_exception_flags(&env->fp_status);
+    target_ulong hard = 0;
+
+    hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0;
+    hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0;
+    hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0;
+    hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0;
+    hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0;
+
+    return hard;
+}
+
+void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
+{
+    int soft = 0;
+
+    soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0;
+    soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0;
+    soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0;
+    soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0;
+    soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0;
+
+    set_float_exception_flags(soft, &env->fp_status);
+}
+
 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)
 {
 #ifdef CONFIG_USER_ONLY
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index af40561b31..eec6328281 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -23,33 +23,6 @@
 #include "fpu/softfloat.h"
 #include "internals.h"
 
-target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
-{
-    int soft = get_float_exception_flags(&env->fp_status);
-    target_ulong hard = 0;
-
-    hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0;
-    hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0;
-    hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0;
-    hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0;
-    hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0;
-
-    return hard;
-}
-
-void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
-{
-    int soft = 0;
-
-    soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0;
-    soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0;
-    soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0;
-    soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0;
-    soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0;
-
-    set_float_exception_flags(soft, &env->fp_status);
-}
-
 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
 {
     int softrm;
-- 
2.43.0

[PATCH v2 3/5] target/riscv: Move riscv_raise_exception() to common code

[Zephyr Li]

Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
---
 target/riscv/cpu_helper.c | 19 +++++++++++++++++++
 target/riscv/op_helper.c  | 15 ---------------
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 678c106ae5..752752d520 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -39,6 +39,25 @@
 #include "pmp.h"
 #include "qemu/plugin.h"
 
+/* Exceptions processing helpers */
+G_NORETURN void riscv_raise_exception(CPURISCVState *env,
+                                      RISCVException exception,
+                                      uintptr_t pc)
+{
+    CPUState *cs = env_cpu(env);
+
+    trace_riscv_exception(exception,
+                          riscv_cpu_get_trap_name(exception, false),
+                          env->pc);
+
+    cs->exception_index = exception;
+#ifdef CONFIG_TCG
+    cpu_loop_exit_restore(cs, pc);
+#else
+    qemu_build_not_reached();
+#endif
+}
+
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
 {
     int soft = get_float_exception_flags(&env->fp_status);
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 81873014cb..d17a8bbf10 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -28,21 +28,6 @@
 #include "exec/tlb-flags.h"
 #include "trace.h"
 
-/* Exceptions processing helpers */
-G_NORETURN void riscv_raise_exception(CPURISCVState *env,
-                                      RISCVException exception,
-                                      uintptr_t pc)
-{
-    CPUState *cs = env_cpu(env);
-
-    trace_riscv_exception(exception,
-                          riscv_cpu_get_trap_name(exception, false),
-                          env->pc);
-
-    cs->exception_index = exception;
-    cpu_loop_exit_restore(cs, pc);
-}
-
 void helper_raise_exception(CPURISCVState *env, uint32_t exception)
 {
     riscv_raise_exception(env, exception, 0);
-- 
2.43.0

[PATCH v2 4/5] target/riscv: Reject x-misa-w without TCG

[Zephyr Li]

Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
---
 target/riscv/cpu.c         |  7 +++++++
 target/riscv/tcg/tcg-cpu.h | 10 ++++++++++
 2 files changed, 17 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1dea66972d..8f54610097 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -955,6 +955,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
     Error *local_err = NULL;
 
+#ifndef CONFIG_TCG
+    if (cpu->cfg.misa_w) {
+        error_setg(errp, "x-misa-w requires TCG");
+        return;
+    }
+#endif
+
     cpu_exec_realizefn(cs, &local_err);
     if (local_err != NULL) {
         error_propagate(errp, local_err);
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index a23716a5ac..20ad294f88 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -22,7 +22,17 @@
 
 #include "cpu.h"
 
+#ifdef CONFIG_TCG
 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
+#else
+static inline void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
+                                                     Error **errp)
+{
+    (void)cpu;
+    (void)errp;
+    qemu_build_not_reached();
+}
+#endif
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
-- 
2.43.0

[PATCH v2 5/5] target/riscv: Build TCG-only code only with TCG

[Zephyr Li]

Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
---
 target/riscv/cpu_helper.c |  6 ++++++
 target/riscv/csr.c        | 11 +++++++++--
 target/riscv/meson.build  |  9 ++++++---
 3 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 752752d520..e53a5d567d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -29,8 +29,10 @@
 #include "exec/target_page.h"
 #include "system/memory.h"
 #include "instmap.h"
+#ifdef CONFIG_TCG
 #include "tcg/tcg-op.h"
 #include "accel/tcg/cpu-ops.h"
+#endif
 #include "trace.h"
 #include "semihosting/common-semi.h"
 #include "exec/icount.h"
@@ -1714,6 +1716,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     return TRANSLATE_SUCCESS;
 }
 
+#ifdef CONFIG_TCG
 static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
                                 MMUAccessType access_type, bool pmp_violation,
                                 bool first_stage, bool two_stage,
@@ -1756,6 +1759,7 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
     env->two_stage_lookup = two_stage;
     env->two_stage_indirect_lookup = two_stage_indirect;
 }
+#endif
 
 hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)
 {
@@ -1780,6 +1784,7 @@ hwaddr riscv_cpu_get_phys_addr_debug(CPUState *cs, vaddr addr)
     return phys_addr;
 }
 
+#ifdef CONFIG_TCG
 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                      vaddr addr, unsigned size,
                                      MMUAccessType access_type,
@@ -2004,6 +2009,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 
     return true;
 }
+#endif
 
 static target_ulong riscv_transformed_insn(CPURISCVState *env,
                                            target_ulong insn,
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5514e0f455..df5dff2c11 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2135,15 +2135,22 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
 
 static target_ulong get_next_pc(CPURISCVState *env, uintptr_t ra)
 {
+    /* Outside of a running cpu, env contains the next pc. */
+    if (ra == 0) {
+        return env->pc;
+    }
+#ifdef CONFIG_TCG
     uint64_t data[INSN_START_WORDS];
 
-    /* Outside of a running cpu, env contains the next pc. */
-    if (ra == 0 || !cpu_unwind_state_data(env_cpu(env), ra, data)) {
+    if (!cpu_unwind_state_data(env_cpu(env), ra, data)) {
         return env->pc;
     }
 
     /* Within unwind data, [0] is pc and [1] is the opcode. */
     return data[0] + insn_len(data[1]);
+#else
+    qemu_build_not_reached();
+#endif
 }
 
 static RISCVException write_misa(CPURISCVState *env, int csrno,
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 79f36abd63..c2b2f61ad9 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -9,7 +9,7 @@ gen = [
 ]
 
 riscv_ss = ss.source_set()
-riscv_ss.add(gen)
+riscv_ss.add(when: 'CONFIG_TCG', if_true: gen)
 
 riscv_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',
 		     if_true: files('common-semi-target.c'))
@@ -18,11 +18,14 @@ riscv_ss.add(files(
   'cpu.c',
   'cpu_helper.c',
   'csr.c',
-  'fpu_helper.c',
   'gdbstub.c',
+  'vector_internals.c',
+))
+
+riscv_ss.add(when: 'CONFIG_TCG', if_true: files(
+  'fpu_helper.c',
   'op_helper.c',
   'vector_helper.c',
-  'vector_internals.c',
   'bitmanip_helper.c',
   'translate.c',
   'm128_helper.c',
-- 
2.43.0

Re: [PATCH v2 1/5] target/riscv: Remove unused tcg/tcg.h include

[Philippe Mathieu-Daudé]

On 26/5/26 13:04, Zephyr Li wrote:
> Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
> ---
>   target/riscv/cpu.c | 1 -
>   1 file changed, 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH v2 4/5] target/riscv: Reject x-misa-w without TCG

[Philippe Mathieu-Daudé]

On 26/5/26 13:04, Zephyr Li wrote:
> Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
> ---
>   target/riscv/cpu.c         |  7 +++++++
>   target/riscv/tcg/tcg-cpu.h | 10 ++++++++++
>   2 files changed, 17 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1dea66972d..8f54610097 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -955,6 +955,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>       RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
>       Error *local_err = NULL;
>   
> +#ifndef CONFIG_TCG
> +    if (cpu->cfg.misa_w) {
> +        error_setg(errp, "x-misa-w requires TCG");
> +        return;
> +    }
> +#endif
> +
>       cpu_exec_realizefn(cs, &local_err);
>       if (local_err != NULL) {
>           error_propagate(errp, local_err);
> diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
> index a23716a5ac..20ad294f88 100644
> --- a/target/riscv/tcg/tcg-cpu.h
> +++ b/target/riscv/tcg/tcg-cpu.h
> @@ -22,7 +22,17 @@
>   
>   #include "cpu.h"
>   
> +#ifdef CONFIG_TCG
>   void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
> +#else
> +static inline void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> +                                                     Error **errp)
> +{
> +    (void)cpu;
> +    (void)errp;
> +    qemu_build_not_reached();

By stub I meant a new unit file added to the stub_ss[] meson source set.

Anyway, I'm not familiar enough with RISCV but if it works similarly to
ARM I'd expect an accelerated 'host' CPU type to have all host-enabled
features, with the ability to deselect few of them. In that case, the
riscv_cpu_validate_set_extensions() helper wouldn't be TCG specific
(since validating the architecture restrictions).

If you need accelerator-specific CPU feature validators, you could
dispatch in riscv_cpu_validate_set_extensions, eventually expanding
AccelOpsClass.

> +}
> +#endif
>   void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
>   bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
>   

Re: [PATCH v2 0/5] target/riscv: Fix no-TCG build

[Philippe Mathieu-Daudé]

On 26/5/26 13:04, Zephyr Li wrote:
> This series fixes the riscv64-softmmu --disable-tcg build by keeping
> TCG-only files and code out of no-TCG builds, while keeping common
> helpers available for non-TCG configurations.
> 
> The first patches move common helpers out of TCG-only helper files. The
> later patches reject x-misa-w when TCG is unavailable, provide a no-TCG
> stub for riscv_cpu_validate_set_extensions(), and build RISC-V TCG-only
> sources only when TCG is enabled.
> 
> Changes in v2:
> - Split the original patch into smaller logical patches.
> - Drop the unused tcg/tcg.h include.
> - Add a no-TCG stub for riscv_cpu_validate_set_extensions().
> - Keep x-misa-w rejected during CPU realize when TCG is unavailable.
> 
> Testing:
> - riscv64-softmmu --enable-kvm --disable-tcg --enable-debug builds
>    successfully.

To complete this effort we need to add coverage. See the last patch
of this series (which was unfortunately not merged back then):
https://lore.kernel.org/qemu-devel/20230711121453.59138-17-philmd@linaro.org/

> - riscv64-softmmu --enable-debug builds successfully.
> - qemu-system-riscv64 -M virt,accel=qtest -cpu rv64,x-misa-w=true \
>    -S -nographic reports "x-misa-w requires TCG".
> 
> Zephyr Li (5):
>    target/riscv: Remove unused tcg/tcg.h include
>    target/riscv: Move fflags helpers to common code
>    target/riscv: Move riscv_raise_exception() to common code
>    target/riscv: Reject x-misa-w without TCG
>    target/riscv: Build TCG-only code only with TCG
> 
>   target/riscv/cpu.c         |  8 +++++-
>   target/riscv/cpu_helper.c  | 53 ++++++++++++++++++++++++++++++++++++++
>   target/riscv/csr.c         | 11 ++++++--
>   target/riscv/fpu_helper.c  | 27 -------------------
>   target/riscv/meson.build   |  9 ++++---
>   target/riscv/op_helper.c   | 15 -----------
>   target/riscv/tcg/tcg-cpu.h | 10 +++++++
>   7 files changed, 85 insertions(+), 48 deletions(-)
> 

Re: [PATCH v2 4/5] target/riscv: Reject x-misa-w without TCG

[Alistair Francis]

On Tue, 2026-05-26 at 14:19 +0200, Philippe Mathieu-Daudé wrote:
> On 26/5/26 13:04, Zephyr Li wrote:
> > Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
> > ---
> >   target/riscv/cpu.c         |  7 +++++++
> >   target/riscv/tcg/tcg-cpu.h | 10 ++++++++++
> >   2 files changed, 17 insertions(+)
> > 
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1dea66972d..8f54610097 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -955,6 +955,13 @@ static void riscv_cpu_realize(DeviceState
> > *dev, Error **errp)
> >       RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> >       Error *local_err = NULL;
> >   
> > +#ifndef CONFIG_TCG
> > +    if (cpu->cfg.misa_w) {
> > +        error_setg(errp, "x-misa-w requires TCG");
> > +        return;
> > +    }
> > +#endif
> > +
> >       cpu_exec_realizefn(cs, &local_err);
> >       if (local_err != NULL) {
> >           error_propagate(errp, local_err);
> > diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-
> > cpu.h
> > index a23716a5ac..20ad294f88 100644
> > --- a/target/riscv/tcg/tcg-cpu.h
> > +++ b/target/riscv/tcg/tcg-cpu.h
> > @@ -22,7 +22,17 @@
> >   
> >   #include "cpu.h"
> >   
> > +#ifdef CONFIG_TCG
> >   void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error
> > **errp);
> > +#else
> > +static inline void riscv_cpu_validate_set_extensions(RISCVCPU
> > *cpu,
> > +                                                     Error **errp)
> > +{
> > +    (void)cpu;
> > +    (void)errp;
> > +    qemu_build_not_reached();
> 
> By stub I meant a new unit file added to the stub_ss[] meson source
> set.
> 
> Anyway, I'm not familiar enough with RISCV but if it works similarly
> to
> ARM I'd expect an accelerated 'host' CPU type to have all host-
> enabled
> features, with the ability to deselect few of them. In that case, the
> riscv_cpu_validate_set_extensions() helper wouldn't be TCG specific
> (since validating the architecture restrictions).

Agreed. This at least needs a commit comment describing why this should
be disabled

Alistair

> 
> If you need accelerator-specific CPU feature validators, you could
> dispatch in riscv_cpu_validate_set_extensions, eventually expanding
> AccelOpsClass.
> 
> > +}
> > +#endif
> >   void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
> > **errp);
> >   bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
> >   

Re: [PATCH v2 1/5] target/riscv: Remove unused tcg/tcg.h include

[Alistair Francis]

On Tue, 2026-05-26 at 19:04 +0800, Zephyr Li wrote:
> Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 862834b480..1dea66972d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -36,7 +36,6 @@
>  #include "system/tcg.h"
>  #include "kvm/kvm_riscv.h"
>  #include "tcg/tcg-cpu.h"
> -#include "tcg/tcg.h"
>  
>  /* RISC-V CPU definitions */
>  static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";

Re: [PATCH v2 4/5] target/riscv: Reject x-misa-w without TCG

[Zephyr Li]

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Thanks Philippe and Alistair.

I see, I misunderstood the stub suggestion and also treated
riscv_cpu_validate_set_extensions() too much as a TCG-only helper.

I'll take another look at the validation logic. If the checks are common
architecture feature restrictions, I'll avoid hiding the helper behind a
no-TCG unreachable stub and instead try to move or split the validation
so the common part is available outside TCG as well.

If I still need to reject some no-TCG configuration, I'll make the reason
explicit in the commit message.

Thanks,
Zephyr

On Wed, May 27, 2026 at 7:52 AM Alistair Francis <Alistair.Francis@wdc.com>
wrote:

> On Tue, 2026-05-26 at 14:19 +0200, Philippe Mathieu-Daudé wrote:
> > On 26/5/26 13:04, Zephyr Li wrote:
> > > Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
> > > ---
> > >   target/riscv/cpu.c         |  7 +++++++
> > >   target/riscv/tcg/tcg-cpu.h | 10 ++++++++++
> > >   2 files changed, 17 insertions(+)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index 1dea66972d..8f54610097 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -955,6 +955,13 @@ static void riscv_cpu_realize(DeviceState
> > > *dev, Error **errp)
> > >       RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> > >       Error *local_err = NULL;
> > >
> > > +#ifndef CONFIG_TCG
> > > +    if (cpu->cfg.misa_w) {
> > > +        error_setg(errp, "x-misa-w requires TCG");
> > > +        return;
> > > +    }
> > > +#endif
> > > +
> > >       cpu_exec_realizefn(cs, &local_err);
> > >       if (local_err != NULL) {
> > >           error_propagate(errp, local_err);
> > > diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-
> > > cpu.h
> > > index a23716a5ac..20ad294f88 100644
> > > --- a/target/riscv/tcg/tcg-cpu.h
> > > +++ b/target/riscv/tcg/tcg-cpu.h
> > > @@ -22,7 +22,17 @@
> > >
> > >   #include "cpu.h"
> > >
> > > +#ifdef CONFIG_TCG
> > >   void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error
> > > **errp);
> > > +#else
> > > +static inline void riscv_cpu_validate_set_extensions(RISCVCPU
> > > *cpu,
> > > +                                                     Error **errp)
> > > +{
> > > +    (void)cpu;
> > > +    (void)errp;
> > > +    qemu_build_not_reached();
> >
> > By stub I meant a new unit file added to the stub_ss[] meson source
> > set.
> >
> > Anyway, I'm not familiar enough with RISCV but if it works similarly
> > to
> > ARM I'd expect an accelerated 'host' CPU type to have all host-
> > enabled
> > features, with the ability to deselect few of them. In that case, the
> > riscv_cpu_validate_set_extensions() helper wouldn't be TCG specific
> > (since validating the architecture restrictions).
>
> Agreed. This at least needs a commit comment describing why this should
> be disabled
>
> Alistair
>
> >
> > If you need accelerator-specific CPU feature validators, you could
> > dispatch in riscv_cpu_validate_set_extensions, eventually expanding
> > AccelOpsClass.
> >
> > > +}
> > > +#endif
> > >   void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
> > > **errp);
> > >   bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
> > >
>

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