[PATCH v2 0/4] arm64: dts: am62p5-var-som-symphony: align DTS with hardware revision

[PATCH v2 0/4] arm64: dts: am62p5-var-som-symphony: align DTS with hardware revision

[Stefano Radaelli]

This series updates the device tree description for the Variscite
VAR-SOM-AM62P and Symphony carrier board to better reflect the current
board configuration.

It aligns the Ethernet PHY description, updates the audio codec
configuration, and adds the touchscreen and TPM devices together with
their required board-level resources.

v1->v2:
 - Remove unused eth property
 - Remove wrong dmic property
 - Fix commit message

Stefano Radaelli (4):
  arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration
  arm64: dts: ti: var-som-am62p: update audio codec configuration
  arm64: dts: am62p5-var-som-symphony: add touchscreen support
  arm64: dts: am62p5-var-som-symphony: add TPM support

 .../dts/ti/k3-am62p5-var-som-symphony.dts     | 43 +++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 35 +++++++++++++--
 2 files changed, 74 insertions(+), 4 deletions(-)


base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43
-- 
2.47.3

[PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

[Stefano Radaelli]

From: Stefano Radaelli <stefano.r@variscite.com>

Fix the Ethernet device tree description on the VAR-SOM-AM62P.

Enable the CPSW Ethernet controller and correct the Ethernet PHY
description by modelling the PHY power supply and adding the required
board-specific PHY properties.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v1->v2:
 - Remove unused eth property

 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
index fc5a3942cde0..ca2483a04b9d 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
@@ -113,6 +113,15 @@ reg_3v3_phy: regulator-3v3-phy {
 		regulator-always-on;
 	};
 
+	reg_eth_phy_vdd: regulator-eth-vdd {
+		compatible = "regulator-fixed";
+		regulator-name = "reg_eth_phy_vdd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&main_gpio0 46 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	sound {
 		compatible = "simple-audio-card";
 		simple-audio-card,bitclock-master = <&codec_dai>;
@@ -149,6 +158,7 @@ &audio_refclk1 {
 &cpsw3g {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_rgmii1>;
+	status = "okay";
 };
 
 &cpsw3g_mdio {
@@ -159,9 +169,9 @@ &cpsw3g_mdio {
 	cpsw3g_phy0: ethernet-phy@4 {
 		compatible = "ethernet-phy-id0283.bc30";
 		reg = <4>;
-		reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
-		reset-assert-us = <10000>;
-		reset-deassert-us = <100000>;
+		bootph-all;
+		enet-phy-lane-no-swap;
+		vdd-supply = <&reg_eth_phy_vdd>;
 	};
 };
 
-- 
2.47.3

Re: [PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Converting the Ethernet PHY reset pin to an unclaimed `vdd-supply` regulator permanently breaks Ethernet.
- [Medium] Removal of hardware reset timing delays causes potential MDIO probe failures.
- [Medium] The `enet-phy-lane-no-swap` property is added but is not supported by the ADIN1300 PHY driver.
--

commit 3ee90bfeecffa9ab90466e7f1bf6b5a34e3bdc8e
Author: Stefano Radaelli <stefano.r@variscite.com>

arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

This patch fixes the Ethernet device tree description on the VAR-SOM-AM62P.
It enables the CPSW Ethernet controller and corrects the Ethernet PHY
description by modelling the PHY power supply and adding board-specific
properties.

> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> index fc5a3942cde00..ca2483a04b9d9 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> @@ -113,6 +113,15 @@ reg_3v3_phy: regulator-3v3-phy {
>  		regulator-always-on;
>  	};
>  
> +	reg_eth_phy_vdd: regulator-eth-vdd {
> +		compatible = "regulator-fixed";
> +		regulator-name = "reg_eth_phy_vdd";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&main_gpio0 46 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +

[Severity: Medium]
Will this lack of startup delay cause MDIO probe failures?

The original PHY node explicitly defined reset-assert-us and reset-deassert-us
delays to satisfy the PHY's physical startup timing requirements. By shifting
the reset pin control to the regulator framework, these explicit delays were
lost. 

The new regulator definition lacks the equivalent startup-delay-us = <100000>
property, which means the kernel might immediately probe the MDIO bus without
waiting for the PHY to initialize.

[ ... ]

> @@ -159,9 +169,9 @@ &cpsw3g_mdio {
>  	cpsw3g_phy0: ethernet-phy@4 {
>  		compatible = "ethernet-phy-id0283.bc30";
>  		reg = <4>;
> -		reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> -		reset-assert-us = <10000>;
> -		reset-deassert-us = <100000>;
> +		bootph-all;
> +		enet-phy-lane-no-swap;

[Severity: Medium]
Does the ADIN1300 driver support the enet-phy-lane-no-swap property?

This property is added to the cpsw3g_phy0 node (an ADIN1300 PHY), but it
appears to only be parsed and implemented by specific drivers like the TI
DP83867 PHY driver. The ADIN1300 driver in drivers/net/phy/adin.c does not
seem to parse this property, so the lane-swap configuration might be silently
ignored.

> +		vdd-supply = <&reg_eth_phy_vdd>;

[Severity: High]
Could this permanently break Ethernet by holding the PHY in reset?

The commit moves control of the active-low PHY reset pin to a regulator-fixed
node assigned to vdd-supply. However, neither the Linux generic PHY framework
nor the ADIN1300 driver parses or claims vdd-supply.

During late initcall, the regulator framework automatically disables unclaimed
regulators that lack regulator-always-on. Disabling this active-high regulator
would drive GPIO 46 low, asserting reset on the PHY indefinitely.

>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782680023.git.stefano.r@variscite.com?part=1

Re: [PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

[Vignesh Raghavendra]

On 29/06/26 02:26, Stefano Radaelli wrote:
> From: Stefano Radaelli <stefano.r@variscite.com>
> 
> Fix the Ethernet device tree description on the VAR-SOM-AM62P.
> 
> Enable the CPSW Ethernet controller and correct the Ethernet PHY
> description by modelling the PHY power supply and adding the required
> board-specific PHY properties.
> 
> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
> ---
> v1->v2:
>  - Remove unused eth property
> 
>  arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> index fc5a3942cde0..ca2483a04b9d 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> @@ -113,6 +113,15 @@ reg_3v3_phy: regulator-3v3-phy {
>  		regulator-always-on;
>  	};
>  
> +	reg_eth_phy_vdd: regulator-eth-vdd {
> +		compatible = "regulator-fixed";
> +		regulator-name = "reg_eth_phy_vdd";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&main_gpio0 46 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +	};
> +
>  	sound {
>  		compatible = "simple-audio-card";
>  		simple-audio-card,bitclock-master = <&codec_dai>;
> @@ -149,6 +158,7 @@ &audio_refclk1 {
>  &cpsw3g {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_rgmii1>;
> +	status = "okay";
>  };
>  
>  &cpsw3g_mdio {
> @@ -159,9 +169,9 @@ &cpsw3g_mdio {
>  	cpsw3g_phy0: ethernet-phy@4 {
>  		compatible = "ethernet-phy-id0283.bc30";
>  		reg = <4>;
> -		reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> -		reset-assert-us = <10000>;
> -		reset-deassert-us = <100000>;

So are the reset delays no longer required? Or they taken care of
somewhere else?

> +		bootph-all;
> +		enet-phy-lane-no-swap;
> +		vdd-supply = <&reg_eth_phy_vdd>;
>  	};
>  };
>  

-- 
Regards
Vignesh
https://ti.com/opensource

Re: [PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

[Stefano Radaelli]

On Mon, Jul 13, 2026 at 04:02:34PM +0530, Vignesh Raghavendra wrote:
> >  
> >  &cpsw3g_mdio {
> > @@ -159,9 +169,9 @@ &cpsw3g_mdio {
> >  	cpsw3g_phy0: ethernet-phy@4 {
> >  		compatible = "ethernet-phy-id0283.bc30";
> >  		reg = <4>;
> > -		reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>;
> > -		reset-assert-us = <10000>;
> > -		reset-deassert-us = <100000>;
> 
> So are the reset delays no longer required? Or they taken care of
> somewhere else?
> 
> > +		bootph-all;
> > +		enet-phy-lane-no-swap;
> > +		vdd-supply = <&reg_eth_phy_vdd>;
> >  	};
> >  };
> >  
> 
> -- 
> Regards
> Vignesh
> https://ti.com/opensource
> 

Hi Vignesh,

No, because this GPIO actually is not used as a PHY reset.

After reviewing the hardware, it turned out that this signal is a
board-level enable signal required for the PHY to operate, rather than
a reset line.
The previous reset-assert-us and reset-deassert-us values were
associated with the incorrect modelling of this GPIO as a reset, and
are not longer needed.

Thank you!

Best Regards,
Stefano

Re: [PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

[Vignesh Raghavendra]

On 2026-07-13 15:32:00+02:00, Stefano Radaelli wrote:
> On Mon, Jul 13, 2026 at 04:02:34PM +0530, Vignesh Raghavendra wrote:
> 
> > >  
> > 
> > So are the reset delays no longer required? Or they taken care of
> > somewhere else?
> > 
> > 
> 
> Hi Vignesh,
> 
> No, because this GPIO actually is not used as a PHY reset.
> 
> After reviewing the hardware, it turned out that this signal is a
> board-level enable signal required for the PHY to operate, rather than
> a reset line.
> The previous reset-assert-us and reset-deassert-us values were
> associated with the incorrect modelling of this GPIO as a reset, and
> are not longer needed.
> 

Along the same lines does [0] need update to how the cpsw3g_phy0 is
described then as its seems very similar to what this patch is addressing?

[0] https://lore.kernel.org/linux-arm-kernel/0a7bdfda80309eaa207b5b369d72f4bcb16e0604.1783864932.git.stefano.r@variscite.com/

> 
> Best Regards,
> Stefano

Re: [PATCH v2 1/4] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration

[Stefano Radaelli]

On Tue, Jul 14, 2026 at 11:36:29AM +0530, Vignesh Raghavendra wrote:
> On 2026-07-13 15:32:00+02:00, Stefano Radaelli wrote:
> > On Mon, Jul 13, 2026 at 04:02:34PM +0530, Vignesh Raghavendra wrote:
> > 
> > > >  
> > > 
> > > So are the reset delays no longer required? Or they taken care of
> > > somewhere else?
> > > 
> > > 
> > 
> > Hi Vignesh,
> > 
> > No, because this GPIO actually is not used as a PHY reset.
> > 
> > After reviewing the hardware, it turned out that this signal is a
> > board-level enable signal required for the PHY to operate, rather than
> > a reset line.
> > The previous reset-assert-us and reset-deassert-us values were
> > associated with the incorrect modelling of this GPIO as a reset, and
> > are not longer needed.
> > 
> 
> Along the same lines does [0] need update to how the cpsw3g_phy0 is
> described then as its seems very similar to what this patch is addressing?
> 
> [0] https://lore.kernel.org/linux-arm-kernel/0a7bdfda80309eaa207b5b369d72f4bcb16e0604.1783864932.git.stefano.r@variscite.com/
> 
> > 
> > Best Regards,
> > Stefano
> 

Hi Vignesh,

No, the AM62 DTS referenced in [0] does not need the same update.

The VAR-SOM-AM62 uses a different Ethernet PHY and has separate signals
for the PHY supply enable and PHY reset. In that design, GPIO0_45
controls the PHY 3.3 V supply, while GPIO0_46 is connected to the PHY
reset input, so the existing reset-gpios description is correct.

The issue addressed by this patch is specific to the VAR-SOM-AM62P.

Thank you for your review,
Best Regards,
Stefano

[PATCH v2 2/4] arm64: dts: ti: var-som-am62p: update audio codec configuration

[Stefano Radaelli]

From: Stefano Radaelli <stefano.r@variscite.com>

Update the WM8904 audio codec configuration on the VAR-SOM-AM62P.

Set the audio reference clock rate to 12 MHz and add the codec DRC, GPIO
and DMIC configuration required by the board.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v1->v2:
 - Remove wrong dmic property

 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
index ca2483a04b9d..8a8dec80cb30 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
@@ -152,7 +152,7 @@ simple-audio-card,cpu {
 };
 
 &audio_refclk1 {
-	assigned-clock-rates = <100000000>;
+	assigned-clock-rates = <12000000>;
 };
 
 &cpsw3g {
@@ -203,6 +203,23 @@ wm8904: audio-codec@1a {
 		DBVDD-supply = <&reg_3v3>;
 		DCVDD-supply = <&reg_1v8>;
 		MICVDD-supply = <&reg_1v8>;
+		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+				    "soft", "music";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
+		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
+		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
 	};
 };
 
-- 
2.47.3

Re: [PATCH v2 2/4] arm64: dts: ti: var-som-am62p: update audio codec configuration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The DMIC configuration is incomplete; it configures the DMIC clock but omits the corresponding DMIC data input pin properties, rendering the digital microphone path non-functional.
--

commit 44edbb6a5df165de90ef2fca3bdea4c204ee25b6
Author: Stefano Radaelli <stefano.r@variscite.com>
Subject: arm64: dts: ti: var-som-am62p: update audio codec configuration

This commit updates the WM8904 audio codec configuration on the VAR-SOM-AM62P
board. It sets the audio reference clock rate to 12 MHz and adds the codec DRC,
GPIO, and DMIC configurations required by the board.

> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> index ca2483a04b9d9..8a8dec80cb30e 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi

[ ... ]

> @@ -203,6 +203,23 @@ wm8904: audio-codec@1a {
>  		DBVDD-supply = <&reg_3v3>;
>  		DCVDD-supply = <&reg_1v8>;
>  		MICVDD-supply = <&reg_1v8>;
> +		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
> +				    "soft", "music";
> +		/*
> +		 * Config registers per name, respectively:
> +		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
> +		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
> +		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
> +		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
> +		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
> +		 */
> +		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
> +				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
> +				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
> +				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
> +				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
> +		/* GPIO1 = DMIC_CLK, don't touch others */
> +		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;

[Severity: Medium]
Will this introduce a regression where the digital microphone path is left
non-functional?

The patch configures GPIO1 to output the DMIC clock, but appears to omit the
required DMIC data input properties like wlf,in1l-as-dmicdat1 or
wlf,in1r-as-dmicdat2.

Looking at the wm8904_handle_dmic_pdata() probe routine, if both data inputs
are missing from the device tree, the driver explicitly disables the DMIC
core by clearing the WM8904_DMIC_ENA_MASK flag.

Because the DMIC core is disabled, the hardware holds the DMIC_CLK output
low entirely on GPIO1, which prevents the microphone from working.

Could this regression be prevented by adding the corresponding data input
pin properties so the codec driver leaves the DMIC core enabled?

>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/cover.1782680023.git.stefano.r@variscite.com?part=2

[PATCH v2 3/4] arm64: dts: am62p5-var-som-symphony: add touchscreen support

[Stefano Radaelli]

From: Stefano Radaelli <stefano.r@variscite.com>

Add support for the capacitive touchscreen on the Symphony carrier
board.

Describe the FT5x06 touchscreen controller, configure its interrupt,
and mark it as a wakeup source.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v1->v2:
 - Fix commit message

 .../dts/ti/k3-am62p5-var-som-symphony.dts     | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
index 5ba4ed56755b..5c41647ff43f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
@@ -293,6 +293,21 @@ &main_i2c1 {
 	clock-frequency = <400000>;
 	status = "okay";
 
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch_pins>;
+		interrupt-parent = <&main_gpio1>;
+		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};
+
 	rtc@68 {
 		compatible = "dallas,ds1337";
 		reg = <0x68>;
@@ -307,6 +322,12 @@ &main_mcan0 {
 };
 
 &main_pmx0 {
+	pinctrl_captouch_pins: main-captouch-default-pins {
+		pinctrl-single,pins = <
+			AM62PX_IOPAD(0x01b8, PIN_INPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */
+		>;
+	};
+
 	pinctrl_extcon: main-extcon-pins {
 		pinctrl-single,pins = <
 			AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */
-- 
2.47.3

[PATCH v2 4/4] arm64: dts: am62p5-var-som-symphony: add TPM support

[Stefano Radaelli]

From: Stefano Radaelli <stefano.r@variscite.com>

Add the ST33KTPM2XI2C TPM device on the Symphony carrier board.

The TPM reset signal is driven through a PCAL6408 GPIO expander, so add
the corresponding GPIO expander node. Configure the RGB_SEL board signal
through a GPIO hog to keep the board in the expected configuration.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
v1->v2:
 - 

 .../dts/ti/k3-am62p5-var-som-symphony.dts     | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
index 5c41647ff43f..8fe8ec903d3d 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts
@@ -293,6 +293,28 @@ &main_i2c1 {
 	clock-frequency = <400000>;
 	status = "okay";
 
+	pcal6408: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		/* RGB_SEL */
+		lvds-brg-enable-hog {
+			gpio-hog;
+			gpios = <7 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "lvds_brg_en";
+		};
+	};
+
+	st33ktpm2xi2c: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		label = "tpm";
+		reg = <0x2e>;
+		reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
+	};
+
 	/* Capacitive touch controller */
 	ft5x06_ts: touchscreen@38 {
 		compatible = "edt,edt-ft5206";
-- 
2.47.3