From: "Naveen N Rao (AMD)" <naveen@kernel.org>
To: Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>
Cc: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Nikunj A Dadhania <nikunj@amd.com>,
Manali Shukla <manali.shukla@amd.com>,
Bharata B Rao <bharata@amd.com>, "H. Peter Anvin" <hpa@zytor.com>
Subject: [PATCH v4 0/3] Support additional AMD EILVT registers
Date: Thu, 23 Jul 2026 11:14:05 +0530 [thread overview]
Message-ID: <cover.1784785046.git.naveen@kernel.org> (raw)
Add support for additional APIC EILVT registers being introduced in
future AMD processors:
https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
Since v3 (http://lore.kernel.org/r/cover.1784619898.git.naveen@kernel.org):
- Move apic_eilvt_count into 'struct apic' (Thomas Gleixner)
- Rename apic_eilvt_count to eilvt_regs_count to more accurately reflect
its purpose.
- Naveen
Naveen N Rao (AMD) (3):
perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
x86/apic: Introduce a variable to track the number of EILVT registers
x86/apic: Drop APIC_EILVT_NR_MAX
arch/x86/include/asm/apic.h | 2 ++
arch/x86/include/asm/apicdef.h | 2 +-
arch/x86/events/amd/ibs.c | 4 ++--
arch/x86/kernel/apic/apic.c | 17 +++++++++++++++--
4 files changed, 20 insertions(+), 5 deletions(-)
base-commit: 385a91beefc86cb6b7f05b2c3a59b2b82c38c92e
--
2.54.0
next reply other threads:[~2026-07-23 5:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 5:44 Naveen N Rao (AMD) [this message]
2026-07-23 5:44 ` [PATCH v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Naveen N Rao (AMD)
2026-07-23 8:02 ` Ingo Molnar
2026-07-23 11:52 ` Naveen N Rao
2026-07-23 5:44 ` [PATCH v4 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Naveen N Rao (AMD)
2026-07-23 5:44 ` [PATCH v4 3/3] x86/apic: Drop APIC_EILVT_NR_MAX Naveen N Rao (AMD)
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