[PATCH 0/5] Add AMD Versal CPM/QDMA PCIe support

[PATCH 0/5] Add AMD Versal CPM/QDMA PCIe support

[Pranav Sanwal]

This series adds PCIe root port support for the AMD Versal CPM4, CPM5
and QDMA PL (soft IP) host bridges, and enables it along with NVMe
storage on the xilinx_versal_virt platform.

Patch 1 adds a generic mmap config-space write helper for host bridges
that only decode 32-bit accesses.
Patches 2 and 3 add the QDMA PL and CPM4/CPM5 host bridge drivers,
respectively.
Patch 4 maps the CPM5 ECAM windows as device memory so config space
accesses are not cached or reordered.
Patch 5 wires everything up in the versal_virt defconfig and adds NVMe
as a distro boot target.

Pranav Sanwal (5):
  pci: Add pci_generic_mmap_write_config32() helper
  pci: Add support for AMD QDMA PL PCIe root port
  pci: Add support for CPM4 and CPM5 PCIe controllers
  arm64: versal: Add MMU mappings for CPM5 ECAM config space
  arm64: versal: Enable PCIe/NVMe support and add NVMe boot target

 MAINTAINERS                          |  10 +
 arch/arm/mach-versal/cpu.c           |  20 ++
 configs/xilinx_versal_virt_defconfig |   6 +
 drivers/pci/Kconfig                  |  19 ++
 drivers/pci/Makefile                 |   2 +
 drivers/pci/pci-uclass.c             |  42 ++++
 drivers/pci/pcie_amd_cpm.c           | 363 +++++++++++++++++++++++++++
 drivers/pci/pcie_amd_qdma_pl.c       | 205 +++++++++++++++
 include/configs/xilinx_versal.h      |   7 +
 include/pci.h                        |  26 ++
 10 files changed, 700 insertions(+)
 create mode 100644 drivers/pci/pcie_amd_cpm.c
 create mode 100644 drivers/pci/pcie_amd_qdma_pl.c

-- 
2.43.7

[PATCH 1/5] pci: Add pci_generic_mmap_write_config32() helper

[Pranav Sanwal]

Some memory-mapped PCI host bridges only decode 32-bit accesses to
their configuration space and either drop or corrupt neighbouring
bytes on a narrower access. Because such hardware only ever reliably
commits a full 32-bit transaction, the only safe way to perform a
narrower write is to synthesize it in software: read the containing
word, patch in the requested bits, and write the whole word back.

Add pci_generic_mmap_write_config32(), a counterpart to
pci_generic_mmap_write_config(), that does exactly this: it
transparently promotes 8-bit and 16-bit writes to a 32-bit
read-modify-write of the word containing the requested offset,
leaving 32-bit writes untouched. This mirrors Linux's
pci_generic_config_write32() (drivers/pci/access.c), used for the
same class of host bridge.

Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
---
 drivers/pci/pci-uclass.c | 42 ++++++++++++++++++++++++++++++++++++++++
 include/pci.h            | 26 +++++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 4bdd1f7477f..f4ce630118f 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -618,6 +618,48 @@ int pci_generic_mmap_write_config(
 	}
 }
 
+int pci_generic_mmap_write_config32(
+	const struct udevice *bus,
+	int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
+		      void **addrp),
+	pci_dev_t bdf,
+	uint offset,
+	ulong value,
+	enum pci_size_t size)
+{
+	u32 shift, mask, tmp;
+	void *address;
+
+	if (addr_f(bus, bdf, ALIGN_DOWN(offset, 4), &address) < 0) {
+		debug("%s: failed to get config address for offset 0x%x\n",
+		      __func__, offset);
+		return 0;
+	}
+
+	switch (size) {
+	case PCI_SIZE_32:
+		writel(value, address);
+		return 0;
+	case PCI_SIZE_8:
+	case PCI_SIZE_16:
+		/*
+		 * Some host bridges only decode 32-bit accesses to their
+		 * config space and silently corrupt neighbouring bytes on a
+		 * narrower write. Widen the access to a 32-bit
+		 * read-modify-write of the word containing the requested
+		 * offset.
+		 */
+		shift = (offset % 4) * BITS_PER_BYTE;
+		mask = pci_get_ff(size) << shift;
+		tmp = readl(address) & ~mask;
+		tmp |= (value << shift) & mask;
+		writel(tmp, address);
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
 int pci_generic_mmap_read_config(
 	const struct udevice *bus,
 	int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
diff --git a/include/pci.h b/include/pci.h
index 4b0facd6dcf..108d97a5d54 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1151,6 +1151,32 @@ int pci_generic_mmap_write_config(
 	ulong value,
 	enum pci_size_t size);
 
+/**
+ * pci_generic_mmap_write_config32() - Generic helper for writing to
+ * memory-mapped PCI configuration space that only supports 32-bit accesses.
+ * @bus: Pointer to the PCI bus
+ * @addr_f: Callback for calculating the config space address
+ * @bdf: Identifies the PCI device to access
+ * @offset: The offset into the device's configuration space
+ * @value: The value to write
+ * @size: Indicates the size of access to perform
+ *
+ * Like pci_generic_mmap_write_config(), but for host bridges whose
+ * configuration space does not decode 8-bit or 16-bit accesses correctly.
+ * Accesses narrower than 32 bits are promoted to a 32-bit
+ * read-modify-write of the word containing @offset.
+ *
+ * Return: 0 on success, else -EINVAL
+ */
+int pci_generic_mmap_write_config32(
+	const struct udevice *bus,
+	int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
+		      void **addrp),
+	pci_dev_t bdf,
+	uint offset,
+	ulong value,
+	enum pci_size_t size);
+
 /**
  * pci_generic_mmap_read_config() - Generic helper for reading from
  * memory-mapped PCI configuration space.
-- 
2.43.7

[PATCH 2/5] pci: Add support for AMD QDMA PL PCIe root port

[Pranav Sanwal]

Add PCIe host bridge driver for AMD QDMA PL (Programmable Logic) soft
IP PCIe5 controller. This driver enables PCIe root port functionality
for QDMA IP instantiated in the PL fabric.

Co-developed-by: Uday Hegde <udayh@amd.com>
Signed-off-by: Uday Hegde <udayh@amd.com>
Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
---
 MAINTAINERS                    |   5 +
 drivers/pci/Kconfig            |  10 ++
 drivers/pci/Makefile           |   1 +
 drivers/pci/pcie_amd_qdma_pl.c | 205 +++++++++++++++++++++++++++++++++
 4 files changed, 221 insertions(+)
 create mode 100644 drivers/pci/pcie_amd_qdma_pl.c

diff --git a/MAINTAINERS b/MAINTAINERS
index eb48eea55c5..4f184a39a9d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -71,6 +71,11 @@ F:	include/alist.h
 F:	lib/alist.c
 F:	test/lib/alist.c
 
+AMD QDMA PL PCIE DRIVER
+M:	Pranav Sanwal <pranav.sanwal@amd.com>
+S:	Maintained
+F:	drivers/pci/pcie_amd_qdma_pl.c
+
 AMD VERSAL2 PCIE DRIVER
 M:	Pranav Sanwal <pranav.sanwal@amd.com>
 S:	Maintained
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 2b2ccdf4745..da2bebafe9a 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -444,6 +444,16 @@ config PCIE_XILINX_NWL
 	  Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
 	  controller as Root Port.
 
+config PCIE_AMD_QDMA_PL
+	bool "AMD QDMA PL PCIe host bridge support"
+	depends on ARCH_VERSAL
+	select SYS_PCI_64BIT
+	help
+	  Say 'Y' here if you want support for the Xilinx/AMD QDMA
+	  PL PCIe host bridge. The controller is a Soft IP instantiated
+	  in the PL fabric which can act as a PCIe Root Port. It provides
+	  ECAM-based configuration space access for device enumeration.
+
 config PCIE_PLDA_COMMON
 	bool
 
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e6d71fd172b..a6891154e9e 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
+obj-$(CONFIG_PCIE_AMD_QDMA_PL) += pcie_amd_qdma_pl.o
 obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
 obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
 obj-$(CONFIG_PCIE_DW_AMD) += pcie_dw_amd.o
diff --git a/drivers/pci/pcie_amd_qdma_pl.c b/drivers/pci/pcie_amd_qdma_pl.c
new file mode 100644
index 00000000000..2143b0a1a27
--- /dev/null
+++ b/drivers/pci/pcie_amd_qdma_pl.c
@@ -0,0 +1,205 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PCIe host bridge driver for AMD QDMA PL PCIe bridge (no XDMA support)
+ *
+ * Copyright (C) 2026 Advanced Micro Devices, Inc.
+ */
+
+#define LOG_CATEGORY UCLASS_PCI
+
+#include <dm.h>
+#include <pci.h>
+
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+/* Register definitions */
+#define AMD_QDMA_REG_IDR			0x138
+#define AMD_QDMA_REG_IMR			0x13c
+#define AMD_QDMA_REG_PSCR			0x144
+#define AMD_QDMA_REG_RPSC			0x148
+
+#define AMD_QDMA_IMR_ALL_MASK		0x0ff30fe9
+#define AMD_QDMA_IDR_ALL_MASK		0xffffffff
+
+/* Root Port Status/control Register definitions */
+#define AMD_QDMA_REG_RPSC_BEN		BIT(0)
+
+/* Phy Status/Control Register definitions */
+#define AMD_QDMA_REG_PSCR_LNKUP		BIT(11)
+#define QDMA_BRIDGE_BASE_OFF			0xcd8
+
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES			10
+#define LINK_WAIT_DELAY_US			90000
+
+/**
+ * struct amd_qdma_pcie - AMD QDMA PL PCIe bridge private data
+ * @dev: PCIe host bridge device
+ * @breg_base: Bridge register base address
+ * @ecam_base: ECAM configuration space base address
+ */
+struct amd_qdma_pcie {
+	struct udevice *dev;
+	void __iomem *breg_base;
+	void __iomem *ecam_base;
+};
+
+static inline u32 amd_qdma_pcie_read(struct amd_qdma_pcie *pcie, u32 reg)
+{
+	u32 val = readl(pcie->breg_base + reg + QDMA_BRIDGE_BASE_OFF);
+
+	dev_dbg(pcie->dev, "rd reg 0x%03x = 0x%08x\n", reg, val);
+
+	return val;
+}
+
+static inline void amd_qdma_pcie_write(struct amd_qdma_pcie *pcie, u32 val,
+				       u32 reg)
+{
+	dev_dbg(pcie->dev, "wr reg 0x%03x = 0x%08x\n", reg, val);
+	writel(val, pcie->breg_base + reg + QDMA_BRIDGE_BASE_OFF);
+}
+
+static bool amd_qdma_pcie_link_up(struct amd_qdma_pcie *pcie)
+{
+	return !!(amd_qdma_pcie_read(pcie, AMD_QDMA_REG_PSCR) &
+		  AMD_QDMA_REG_PSCR_LNKUP);
+}
+
+static int amd_qdma_pcie_config_address(const struct udevice *bus,
+					pci_dev_t bdf, uint offset,
+					void **paddress)
+{
+	struct amd_qdma_pcie *priv = dev_get_priv(bus);
+	u32 busnum = PCI_BUS(bdf) - dev_seq(bus);
+	void *addr;
+
+	if (busnum == 0) {
+		if (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0)
+			return -ENODEV;
+	} else {
+		if (!amd_qdma_pcie_link_up(priv))
+			return -ENODEV;
+	}
+
+	addr = priv->ecam_base;
+	addr += PCIE_ECAM_OFFSET(busnum, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+	*paddress = addr;
+
+	return 0;
+}
+
+static int amd_qdma_pcie_read_config(const struct udevice *bus,
+				     pci_dev_t bdf, uint offset,
+				     ulong *valuep, enum pci_size_t size)
+{
+	return pci_generic_mmap_read_config(bus, amd_qdma_pcie_config_address,
+					     bdf, offset, valuep, size);
+}
+
+static int amd_qdma_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+				      uint offset, ulong value,
+				      enum pci_size_t size)
+{
+	/*
+	 * The QDMA PL bridge's config space only decodes 32-bit accesses;
+	 * narrower writes must be promoted to a 32-bit read-modify-write.
+	 */
+	return pci_generic_mmap_write_config32(bus, amd_qdma_pcie_config_address,
+						bdf, offset, value, size);
+}
+
+static const struct dm_pci_ops amd_qdma_pcie_ops = {
+	.read_config = amd_qdma_pcie_read_config,
+	.write_config = amd_qdma_pcie_write_config,
+};
+
+static int amd_qdma_pcie_bridge_init(struct amd_qdma_pcie *pcie)
+{
+	int retries;
+	u32 val;
+
+	/* Check if the link is up or not */
+	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+		if (amd_qdma_pcie_link_up(pcie))
+			break;
+		udelay(LINK_WAIT_DELAY_US);
+	}
+
+	if (retries >= LINK_WAIT_MAX_RETRIES) {
+		dev_warn(pcie->dev, "PHY link never came up\n");
+		return -ETIMEDOUT;
+	}
+
+	dev_dbg(pcie->dev, "PCIe Link is UP\n");
+
+	/* Disable all interrupts */
+	amd_qdma_pcie_write(pcie, ~AMD_QDMA_IDR_ALL_MASK, AMD_QDMA_REG_IMR);
+
+	/* Clear pending interrupts */
+	val = amd_qdma_pcie_read(pcie, AMD_QDMA_REG_IDR) & AMD_QDMA_IMR_ALL_MASK;
+	amd_qdma_pcie_write(pcie, val, AMD_QDMA_REG_IDR);
+
+	/* Set the Bridge enable bit */
+	val = amd_qdma_pcie_read(pcie, AMD_QDMA_REG_RPSC);
+	amd_qdma_pcie_write(pcie, val | AMD_QDMA_REG_RPSC_BEN, AMD_QDMA_REG_RPSC);
+
+	return 0;
+}
+
+static int amd_qdma_pcie_parse_dt(struct amd_qdma_pcie *priv)
+{
+	struct udevice *dev = priv->dev;
+
+	priv->breg_base = dev_read_addr_name_ptr(dev, "breg");
+	if (!priv->breg_base) {
+		dev_err(dev, "failed to get breg address\n");
+		return -EINVAL;
+	}
+
+	priv->ecam_base = dev_read_addr_name_ptr(dev, "cfg");
+	if (!priv->ecam_base) {
+		dev_err(dev, "failed to get cfg address\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int amd_qdma_pcie_probe(struct udevice *dev)
+{
+	struct amd_qdma_pcie *priv = dev_get_priv(dev);
+	int err;
+
+	priv->dev = dev;
+
+	err = amd_qdma_pcie_parse_dt(priv);
+	if (err) {
+		dev_err(dev, "Parsing DT failed\n");
+		return err;
+	}
+
+	err = amd_qdma_pcie_bridge_init(priv);
+	if (err) {
+		dev_err(dev, "HW Initialization failed\n");
+		return err;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id amd_qdma_pcie_of_match[] = {
+	{ .compatible = "xlnx,qdma-host-3.00", },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(amd_qdma_pcie) = {
+	.name = "amd_qdma_pcie",
+	.id = UCLASS_PCI,
+	.of_match = amd_qdma_pcie_of_match,
+	.probe = amd_qdma_pcie_probe,
+	.priv_auto = sizeof(struct amd_qdma_pcie),
+	.ops = &amd_qdma_pcie_ops,
+};
-- 
2.43.7

[PATCH 3/5] pci: Add support for CPM4 and CPM5 PCIe controllers

[Pranav Sanwal]

Add a host controller driver for the AMD Versal CPM4 and CPM5 PCIe
bridges, selected via the DT compatible string and enabled with
CONFIG_PCIE_AMD_CPM. The driver maps the bridge/ECAM regions,
services ECAM-based config space accesses, masks off all local
interrupts, and brings up the root port bridge. CPM5 variants also
support an optional PERST#-driven IP reset sequence ahead of link
bring-up.

Co-developed-by: Uday Hegde <udayh@amd.com>
Signed-off-by: Uday Hegde <udayh@amd.com>
Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
---
 MAINTAINERS                |   5 +
 drivers/pci/Kconfig        |   9 +
 drivers/pci/Makefile       |   1 +
 drivers/pci/pcie_amd_cpm.c | 363 +++++++++++++++++++++++++++++++++++++
 4 files changed, 378 insertions(+)
 create mode 100644 drivers/pci/pcie_amd_cpm.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 4f184a39a9d..0cc8670cfe4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -71,6 +71,11 @@ F:	include/alist.h
 F:	lib/alist.c
 F:	test/lib/alist.c
 
+AMD CPM PCIE DRIVER
+M:	Pranav Sanwal <pranav.sanwal@amd.com>
+S:	Maintained
+F:	drivers/pci/pcie_amd_cpm.c
+
 AMD QDMA PL PCIE DRIVER
 M:	Pranav Sanwal <pranav.sanwal@amd.com>
 S:	Maintained
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index da2bebafe9a..64bab2b9dd6 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -444,6 +444,15 @@ config PCIE_XILINX_NWL
 	  Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
 	  controller as Root Port.
 
+config PCIE_AMD_CPM
+	bool "AMD Versal CPM PCIe host bridge support"
+	depends on ARCH_VERSAL
+	depends on DM_GPIO
+	select SYS_PCI_64BIT
+	help
+	  Say 'Y' here if you want support for the AMD Versal
+	  CPM PCIe host bridge.
+
 config PCIE_AMD_QDMA_PL
 	bool "AMD QDMA PL PCIe host bridge support"
 	depends on ARCH_VERSAL
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index a6891154e9e..3873f357a45 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
+obj-$(CONFIG_PCIE_AMD_CPM) += pcie_amd_cpm.o
 obj-$(CONFIG_PCIE_AMD_QDMA_PL) += pcie_amd_qdma_pl.o
 obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
 obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_amd_cpm.c b/drivers/pci/pcie_amd_cpm.c
new file mode 100644
index 00000000000..8377e772792
--- /dev/null
+++ b/drivers/pci/pcie_amd_cpm.c
@@ -0,0 +1,363 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PCIe host controller driver for AMD CPM
+ *
+ * Copyright (C) 2026 Advanced Micro Devices, Inc.
+ */
+
+#define LOG_CATEGORY UCLASS_PCI
+
+#include <dm.h>
+#include <pci.h>
+
+#include <asm/gpio.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+/*
+ * End of conventional reset (PERST# de-asserted) to first configuration
+ * request (device able to respond with a "Request Retry Status" completion),
+ * from PCIe r6.0, sec 6.6.1.
+ */
+#define PCIE_T_RRS_READY_MS	100
+
+/*
+ * "PERST# active time", as per Table 2-10: Power Sequencing and Reset
+ * Signal Timings of the PCIe Electromechanical Specification,
+ * Revision 6.0, symbol "T_PERST".
+ */
+#define PCIE_T_PERST_US		100
+
+/* Register definitions */
+#define AMD_CPM_PCIE0_RST		0x00000308
+#define AMD_CPM5_PCIE0_RST		0x00000318
+#define AMD_CPM5_PCIE1_RST		0x0000031C
+
+#define AMD_CPM_PCIE_REG_IDR		0x00000E10
+#define AMD_CPM_PCIE_REG_IMR		0x00000E14
+#define AMD_CPM_PCIE_REG_PSCR		0x00000E1C
+#define AMD_CPM_PCIE_REG_RPSC		0x00000E20
+
+/* Interrupt registers definitions */
+#define AMD_CPM_INTR_LINK_DOWN		0
+#define AMD_CPM_INTR_HOT_RESET		3
+#define AMD_CPM_INTR_CFG_PCIE_TIMEOUT	4
+#define AMD_CPM_INTR_CFG_TIMEOUT	8
+#define AMD_CPM_INTR_CORRECTABLE	9
+#define AMD_CPM_INTR_NONFATAL		10
+#define AMD_CPM_INTR_FATAL		11
+#define AMD_CPM_INTR_CFG_ERR_POISON	12
+#define AMD_CPM_INTR_PME_TO_ACK_RCVD	15
+#define AMD_CPM_INTR_INTX		16
+#define AMD_CPM_INTR_PM_PME_RCVD	17
+#define AMD_CPM_INTR_MSI		17
+#define AMD_CPM_INTR_SLV_UNSUPP		20
+#define AMD_CPM_INTR_SLV_UNEXP		21
+#define AMD_CPM_INTR_SLV_COMPL		22
+#define AMD_CPM_INTR_SLV_ERRP		23
+#define AMD_CPM_INTR_SLV_CMPABT		24
+#define AMD_CPM_INTR_SLV_ILLBUR		25
+#define AMD_CPM_INTR_MST_DECERR		26
+#define AMD_CPM_INTR_MST_SLVERR		27
+#define AMD_CPM_INTR_SLV_PCIE_TIMEOUT	28
+
+#define IMR(x) BIT(AMD_CPM_INTR_ ##x)
+
+#define AMD_CPM_PCIE_IMR_ALL_MASK		\
+	(IMR(LINK_DOWN)		| \
+	 IMR(HOT_RESET)		| \
+	 IMR(CFG_PCIE_TIMEOUT)	| \
+	 IMR(CFG_TIMEOUT)	| \
+	 IMR(CORRECTABLE)	| \
+	 IMR(NONFATAL)		| \
+	 IMR(FATAL)		| \
+	 IMR(CFG_ERR_POISON)	| \
+	 IMR(PME_TO_ACK_RCVD)	| \
+	 IMR(INTX)		| \
+	 IMR(PM_PME_RCVD)	| \
+	 IMR(SLV_UNSUPP)	| \
+	 IMR(SLV_UNEXP)		| \
+	 IMR(SLV_COMPL)		| \
+	 IMR(SLV_ERRP)		| \
+	 IMR(SLV_CMPABT)	| \
+	 IMR(SLV_ILLBUR)	| \
+	 IMR(MST_DECERR)	| \
+	 IMR(MST_SLVERR)	| \
+	 IMR(SLV_PCIE_TIMEOUT))
+
+#define AMD_CPM_PCIE_IDR_ALL_MASK		0xFFFFFFFF
+
+#define AMD_CPM_PCIE_REG_RPSC_BEN		BIT(0)
+
+#define AMD_CPM_PCIE_REG_PSCR_LNKUP		BIT(11)
+
+enum amd_cpm_version {
+	AMD_CPM_VER_1,
+	AMD_CPM_VER_5_HOST0,
+	AMD_CPM_VER_5_HOST1,
+};
+
+/**
+ * struct amd_cpm_variant - CPM variant information
+ * @version: CPM version
+ * @cpm_pcie_rst: Offset for the PCIe IP reset
+ */
+struct amd_cpm_variant {
+	enum amd_cpm_version version;
+	u32 cpm_pcie_rst;
+};
+
+/**
+ * struct amd_cpm_pcie - AMD CPM PCIe bridge private data
+ * @dev: PCIe host bridge device
+ * @reg_base: Bridge register base address
+ * @cfg_base: ECAM configuration space base address
+ * @crx_base: CPM5 reset control base address (optional)
+ * @variant: CPM version check pointer
+ */
+struct amd_cpm_pcie {
+	struct udevice *dev;
+	void __iomem *reg_base;
+	void __iomem *cfg_base;
+	void __iomem *crx_base;
+	const struct amd_cpm_variant *variant;
+};
+
+static inline u32 amd_cpm_pcie_read(struct amd_cpm_pcie *pcie, u32 reg)
+{
+	u32 val = readl(pcie->reg_base + reg);
+
+	dev_dbg(pcie->dev, "rd reg 0x%03x = 0x%08x\n", reg, val);
+
+	return val;
+}
+
+static inline void amd_cpm_pcie_write(struct amd_cpm_pcie *pcie,
+				      u32 val, u32 reg)
+{
+	dev_dbg(pcie->dev, "wr reg 0x%03x = 0x%08x\n", reg, val);
+	writel(val, pcie->reg_base + reg);
+}
+
+static bool amd_cpm_pcie_link_up(struct amd_cpm_pcie *pcie)
+{
+	return !!(amd_cpm_pcie_read(pcie, AMD_CPM_PCIE_REG_PSCR) &
+		  AMD_CPM_PCIE_REG_PSCR_LNKUP);
+}
+
+static int amd_cpm_pcie_config_address(const struct udevice *bus,
+				       pci_dev_t bdf, uint offset,
+				       void **paddress)
+{
+	struct amd_cpm_pcie *priv = dev_get_priv(bus);
+	u32 busnum = PCI_BUS(bdf) - dev_seq(bus);
+	void *addr;
+
+	addr = priv->cfg_base;
+	addr += PCIE_ECAM_OFFSET(busnum, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+	dev_dbg(priv->dev, "cfg bdf=%02x:%02x.%x offset=0x%x addr=%p\n",
+		PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset, addr);
+	*paddress = addr;
+
+	return 0;
+}
+
+/*
+ * The root port's own function (bus 0, device 0, function 0) reports a
+ * bogus 64-bit BAR0 that autoconfig can never place. Mask it off so it
+ * always reads back as not implemented.
+ */
+static bool amd_cpm_pcie_is_own_bar(const struct udevice *bus, pci_dev_t bdf,
+				    uint offset)
+{
+	u32 busnum = PCI_BUS(bdf) - dev_seq(bus);
+
+	return busnum == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+	       offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_2;
+}
+
+static int amd_cpm_pcie_read_config(const struct udevice *bus,
+				    pci_dev_t bdf, uint offset,
+				    ulong *valuep, enum pci_size_t size)
+{
+	if (amd_cpm_pcie_is_own_bar(bus, bdf, offset)) {
+		*valuep = 0;
+		return 0;
+	}
+
+	return pci_generic_mmap_read_config(bus, amd_cpm_pcie_config_address,
+					    bdf, offset, valuep, size);
+}
+
+static int amd_cpm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
+				     uint offset, ulong value,
+				     enum pci_size_t size)
+{
+	if (amd_cpm_pcie_is_own_bar(bus, bdf, offset))
+		return 0;
+
+	return pci_generic_mmap_write_config(bus, amd_cpm_pcie_config_address,
+					     bdf, offset, value, size);
+}
+
+static const struct dm_pci_ops amd_cpm_pcie_ops = {
+	.read_config = amd_cpm_pcie_read_config,
+	.write_config = amd_cpm_pcie_write_config,
+};
+
+static int amd_cpm_pcie_host_init(struct amd_cpm_pcie *pcie)
+{
+	const struct amd_cpm_variant *variant = pcie->variant;
+	struct udevice *dev = pcie->dev;
+	struct gpio_desc *reset_gpio;
+	u32 val;
+
+	if (pcie->crx_base) {
+		reset_gpio = devm_gpiod_get_optional(dev, "reset",
+						     GPIOD_IS_OUT |
+						     GPIOD_IS_OUT_ACTIVE);
+		if (reset_gpio) {
+			/* Assert the PCIe IP reset */
+			writel(BIT(0), pcie->crx_base + variant->cpm_pcie_rst);
+
+			udelay(PCIE_T_PERST_US);
+
+			/* Deassert the PCIe IP reset */
+			writel(0, pcie->crx_base + variant->cpm_pcie_rst);
+
+			/* Deassert the reset signal */
+			dm_gpio_set_value(reset_gpio, 0);
+			mdelay(PCIE_T_RRS_READY_MS);
+		}
+	}
+
+	dev_dbg(dev, "PCIe link %s\n",
+		amd_cpm_pcie_link_up(pcie) ? "up" : "down");
+
+	/* Disable all interrupts */
+	amd_cpm_pcie_write(pcie, ~AMD_CPM_PCIE_IDR_ALL_MASK,
+			   AMD_CPM_PCIE_REG_IMR);
+
+	/* Clear pending interrupts */
+	val = amd_cpm_pcie_read(pcie, AMD_CPM_PCIE_REG_IDR);
+	amd_cpm_pcie_write(pcie, val & AMD_CPM_PCIE_IMR_ALL_MASK,
+			   AMD_CPM_PCIE_REG_IDR);
+
+	/* Enable root port bridge */
+	val = amd_cpm_pcie_read(pcie, AMD_CPM_PCIE_REG_RPSC);
+	amd_cpm_pcie_write(pcie, val | AMD_CPM_PCIE_REG_RPSC_BEN,
+			   AMD_CPM_PCIE_REG_RPSC);
+
+	return 0;
+}
+
+static int amd_cpm_pcie_map_res(struct udevice *dev, const char *name,
+				void __iomem **map)
+{
+	struct resource res;
+	int ret;
+
+	ret = dev_read_resource_byname(dev, name, &res);
+	if (ret)
+		return ret;
+
+	*map = devm_ioremap(dev, res.start, resource_size(&res));
+	if (!*map)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static int amd_cpm_pcie_parse_dt(struct amd_cpm_pcie *pcie)
+{
+	struct udevice *dev = pcie->dev;
+	int ret;
+
+	ret = amd_cpm_pcie_map_res(dev, "cfg", &pcie->cfg_base);
+	if (ret)
+		return ret;
+
+	if (pcie->variant->version == AMD_CPM_VER_1) {
+		/*
+		 * On original CPM the ECAM and bridge registers share the same
+		 * region; cfg_base and reg_base both point into it.
+		 */
+		pcie->reg_base = pcie->cfg_base;
+	} else {
+		ret = amd_cpm_pcie_map_res(dev, "cpm_csr", &pcie->reg_base);
+		if (ret)
+			return ret;
+	}
+
+	/* cpm_crx is optional; absence means no PCIe IP reset sequence */
+	amd_cpm_pcie_map_res(dev, "cpm_crx", &pcie->crx_base);
+
+	return 0;
+}
+
+static int amd_cpm_pcie_probe(struct udevice *dev)
+{
+	struct amd_cpm_pcie *priv = dev_get_priv(dev);
+	int err;
+
+	priv->dev = dev;
+	priv->variant = (const struct amd_cpm_variant *)dev_get_driver_data(dev);
+	if (!priv->variant)
+		return -EINVAL;
+
+	err = amd_cpm_pcie_parse_dt(priv);
+	if (err) {
+		dev_err(dev, "failed to parse DT: %d\n", err);
+		return err;
+	}
+
+	err = amd_cpm_pcie_host_init(priv);
+	if (err) {
+		dev_err(dev, "failed to initialize host: %d\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
+static const struct amd_cpm_variant cpm_host = {
+	.version = AMD_CPM_VER_1,
+	.cpm_pcie_rst = AMD_CPM_PCIE0_RST,
+};
+
+static const struct amd_cpm_variant cpm5_host = {
+	.version = AMD_CPM_VER_5_HOST0,
+	.cpm_pcie_rst = AMD_CPM5_PCIE0_RST,
+};
+
+static const struct amd_cpm_variant cpm5_host1 = {
+	.version = AMD_CPM_VER_5_HOST1,
+	.cpm_pcie_rst = AMD_CPM5_PCIE1_RST,
+};
+
+static const struct udevice_id amd_cpm_pcie_of_match[] = {
+	{
+		.compatible = "xlnx,versal-cpm-host-1.00",
+		.data = (ulong)&cpm_host,
+	},
+	{
+		.compatible = "xlnx,versal-cpm5-host",
+		.data = (ulong)&cpm5_host,
+	},
+	{
+		.compatible = "xlnx,versal-cpm5-host1",
+		.data = (ulong)&cpm5_host1,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(amd_cpm_pcie) = {
+	.name = "amd_cpm_pcie",
+	.id = UCLASS_PCI,
+	.of_match = amd_cpm_pcie_of_match,
+	.probe = amd_cpm_pcie_probe,
+	.priv_auto = sizeof(struct amd_cpm_pcie),
+	.ops = &amd_cpm_pcie_ops,
+};
-- 
2.43.7

[PATCH 4/5] arm64: versal: Add MMU mappings for CPM5 ECAM config space

[Pranav Sanwal]

CPM5 Host0 and Host1 each expose PCIe config space (ECAM) inside their
4 GiB NoC address slot, at 0x600000000 and 0x700000000 respectively.
Per the DT "cfg" reg and the PCIe ECAM spec (256 bus numbers x 1 MiB
per bus), each window is 256 MiB. Config space accesses must not be
cached, reordered, or speculatively issued, so map each ECAM window as
Device memory (MT_DEVICE_NGNRNE).

Rather than mapping 0x600000000-0xe00000000 only when
CONFIG_PCIE_AMD_CPM is enabled, add it as a baseline Normal/cacheable
entry unconditionally: this NoC/PL address space is shared by more
than CPM (PL fabric AXI space, other NoC-attached peripherals, etc.),
so it needs coverage regardless of which PCIe controllers are built
in. The two CPM5 ECAM sub-ranges are then overlaid as Device memory on
top of that baseline only when PCIE_AMD_CPM is enabled.

Update VERSAL_MEM_MAP_USED to match: 3 entries when PCIE_AMD_CPM is
disabled, 5 when it's enabled (+2 ECAM overlays).

Co-developed-by: Uday Hegde <udayh@amd.com>
Signed-off-by: Uday Hegde <udayh@amd.com>
Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
---
 arch/arm/mach-versal/cpu.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
index 7521d45bc1a..5dbd0fcc438 100644
--- a/arch/arm/mach-versal/cpu.c
+++ b/arch/arm/mach-versal/cpu.c
@@ -20,7 +20,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(PCIE_AMD_CPM)
+#define VERSAL_MEM_MAP_USED	5
+#else
 #define VERSAL_MEM_MAP_USED	3
+#endif
 
 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
 
@@ -55,6 +59,22 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = {
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+#if CONFIG_IS_ENABLED(PCIE_AMD_CPM)
+	}, {
+		.virt = 0x600000000UL,
+		.phys = 0x600000000UL,
+		.size = 0x010000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x700000000UL,
+		.phys = 0x700000000UL,
+		.size = 0x010000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+#endif
 	}
 };
 
-- 
2.43.7

[PATCH 5/5] arm64: versal: Enable PCIe/NVMe support and add NVMe boot target

[Pranav Sanwal]

Enable the AMD Versal CPM/QDMA PCIe host controllers and NVMe storage
in the virtual platform defconfig.

Add BOOT_TARGET_DEVICES_NVME to xilinx_versal.h so NVMe is included
in the distro boot target list when CONFIG_NVME is enabled.

Signed-off-by: Pranav Sanwal <pranav.sanwal@amd.com>
---
 configs/xilinx_versal_virt_defconfig | 6 ++++++
 include/configs/xilinx_versal.h      | 7 +++++++
 2 files changed, 13 insertions(+)

diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index a94468d9b9b..647e0455f85 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -16,6 +16,7 @@ CONFIG_SYS_LOAD_ADDR=0x8000000
 CONFIG_ENV_OFFSET_REDUND=0x7F00000
 CONFIG_CMD_FRU=y
 CONFIG_DEFINE_TCM_OCM_MMAP=y
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x00000000
 CONFIG_SYS_MEMTEST_END=0x00001000
 CONFIG_REMAKE_ELF=y
@@ -47,9 +48,11 @@ CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_LSBLK=y
 CONFIG_CMD_MMC=y
 CONFIG_MMC_SPEED_MODE_SET=y
 CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_NFS=y
@@ -135,6 +138,9 @@ CONFIG_PHY_NATSEMI=y
 CONFIG_PHY_REALTEK=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_FIXED=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_AMD_CPM=y
+CONFIG_PCIE_AMD_QDMA_PL=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_ZYNQMP_POWER_DOMAIN=y
 CONFIG_RESET_ZYNQMP=y
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index 64f123424cf..cea3340cf2e 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -118,10 +118,17 @@
 #define BOOTENV_DEV_NAME_USB_THOR(devtypeu, devtypel, instance) \
 	""
 
+#if defined(CONFIG_NVME)
+# define BOOT_TARGET_DEVICES_NVME(func)	func(NVME, nvme, 0)
+#else
+# define BOOT_TARGET_DEVICES_NVME(func)
+#endif
+
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_DEVICES_JTAG(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_XSPI(func) \
+	BOOT_TARGET_DEVICES_NVME(func) \
 	BOOT_TARGET_DEVICES_USB_DFU(func) \
 	BOOT_TARGET_DEVICES_USB_THOR(func) \
 	BOOT_TARGET_DEVICES_USB(func) \
-- 
2.43.7

Re: [PATCH 0/5] Add AMD Versal CPM/QDMA PCIe support

[Michal Simek]

On 8/24/26 09:21, Pranav Sanwal wrote:
> This series adds PCIe root port support for the AMD Versal CPM4, CPM5
> and QDMA PL (soft IP) host bridges, and enables it along with NVMe
> storage on the xilinx_versal_virt platform.
> 
> Patch 1 adds a generic mmap config-space write helper for host bridges
> that only decode 32-bit accesses.
> Patches 2 and 3 add the QDMA PL and CPM4/CPM5 host bridge drivers,
> respectively.
> Patch 4 maps the CPM5 ECAM windows as device memory so config space
> accesses are not cached or reordered.
> Patch 5 wires everything up in the versal_virt defconfig and adds NVMe
> as a distro boot target.
> 
> Pranav Sanwal (5):
>    pci: Add pci_generic_mmap_write_config32() helper
>    pci: Add support for AMD QDMA PL PCIe root port
>    pci: Add support for CPM4 and CPM5 PCIe controllers
>    arm64: versal: Add MMU mappings for CPM5 ECAM config space
>    arm64: versal: Enable PCIe/NVMe support and add NVMe boot target
> 
>   MAINTAINERS                          |  10 +
>   arch/arm/mach-versal/cpu.c           |  20 ++
>   configs/xilinx_versal_virt_defconfig |   6 +
>   drivers/pci/Kconfig                  |  19 ++
>   drivers/pci/Makefile                 |   2 +
>   drivers/pci/pci-uclass.c             |  42 ++++
>   drivers/pci/pcie_amd_cpm.c           | 363 +++++++++++++++++++++++++++
>   drivers/pci/pcie_amd_qdma_pl.c       | 205 +++++++++++++++
>   include/configs/xilinx_versal.h      |   7 +
>   include/pci.h                        |  26 ++
>   10 files changed, 700 insertions(+)
>   create mode 100644 drivers/pci/pcie_amd_cpm.c
>   create mode 100644 drivers/pci/pcie_amd_qdma_pl.c
> 

Applied.
M