[PATCH 00/11] xilinx: mbv: Various updates

[PATCH 00/11] xilinx: mbv: Various updates

[Michal Simek]

Hi,

I am sending various changes which lands in downstream repository
based on tests which were done against the latest RTL.

Thanks,
Michal


Michal Simek (5):
  riscv: dts: mbv: Update bootph-all in xilinx-mbv64 DT
  xilinx: mbv: Enable GPIO driver and command
  xilinx: mbv: Enable CMD_EXCEPTION
  xilinx: mbv: Add support for using bigger boot images via bootm
  xilinx: mbv: Enable MTD command by default

Padmarao Begari (4):
  xilinx: mbv: Enable Timer, Ethernet support
  xilinx: mbv: Update stack, heap, and OpenSBI memory
  xilinx: mbv: Disable SPL raw image support
  xilinx: mbv: Add SPI-related board config

Sandeep Gundlupet Raju (2):
  riscv: dts: mbv: Update mem size to 2GB
  xilinx: mbv: Add sys prompt for mbv32 and mbv64

 arch/riscv/dts/xilinx-mbv64.dts      |  8 +++++---
 configs/xilinx_mbv32_defconfig       | 26 +++++++++++++++++++++-----
 configs/xilinx_mbv32_smode_defconfig |  2 +-
 configs/xilinx_mbv64_defconfig       |  1 +
 configs/xilinx_mbv64_smode_defconfig |  2 +-
 configs/xilinx_mbv_spi.config        | 14 ++++++++++++++
 6 files changed, 43 insertions(+), 10 deletions(-)
 create mode 100644 configs/xilinx_mbv_spi.config

---

-- 
2.43.0

[PATCH 01/11] riscv: dts: mbv: Update mem size to 2GB

[Michal Simek]

From: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>

Currently memory size is set to 1GB, increase the mem size to 2GB to be
aligned with uboot-test-hooks setting which is using -m 2G.

Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/riscv/dts/xilinx-mbv64.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index e6235ed2f525..cac7f65cd569 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -47,7 +47,7 @@
 
 	memory@80000000 {
 		device_type = "memory";
-		reg = <0 0x80000000 0 0x40000000>;
+		reg = <0 0x80000000 0 0x80000000>;
 	};
 
 	clk100: clock {
-- 
2.43.0

[PATCH 02/11] riscv: dts: mbv: Update bootph-all in xilinx-mbv64 DT

[Michal Simek]

Mark cpus and clk100 with bootph-all to have them available during SPL.
Also remove it from axi timer because RISC-V timer should be used instead.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/riscv/dts/xilinx-mbv64.dts | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index cac7f65cd569..46950155bbe6 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek@amd.com>
  */
@@ -19,6 +19,8 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		timebase-frequency = <100000000>;
+		bootph-all;
+
 		cpu_0: cpu@0 {
 			compatible = "amd,mbv64", "riscv";
 			device_type = "cpu";
@@ -51,6 +53,7 @@
 	};
 
 	clk100: clock {
+		bootph-all;
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <100000000>;
@@ -78,7 +81,6 @@
 			reg = <0 0x41c00000 0 0x1000>;
 			interrupt-parent = <&axi_intc>;
 			interrupts = <0 2>;
-			bootph-all;
 			xlnx,one-timer-only = <0>;
 			clock-names = "s_axi_aclk";
 			clocks = <&clk100>;
-- 
2.43.0

[PATCH 03/11] xilinx: mbv: Enable Timer, Ethernet support

[Michal Simek]

From: Padmarao Begari <padmarao.begari@amd.com>

Enable RISC-V timer and Ethernet support.

Both the RISC-V timer and the Xilinx AXI timer are enabled by
default to support whichever timer is enabled in the device tree.
At runtime, U-Boot selects the appropriate timer based on the
available device node.

The QEMU model does not support the RISC-V timer, which is why
the AXI timer is used instead. RISC-V timer can be used for
minimal footprint and early availability.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 47cecd6878a7..c84b1a41655f 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -43,16 +43,23 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
 # CONFIG_SPL_CPU is not set
 CONFIG_SPL_REMAKE_ELF=y
-# CONFIG_CMD_MII is not set
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_TIMER=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_LWIP=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DM_MTD=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_XILINX_AXIEMAC=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_TI_DP83867=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_EMULATION=y
 CONFIG_XILINX_UARTLITE=y
-CONFIG_XILINX_TIMER=y
+CONFIG_RISCV_TIMER=y
 # CONFIG_BINMAN_FDT is not set
 CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
 CONFIG_PANIC_HANG=y
-- 
2.43.0

[PATCH 04/11] xilinx: mbv: Enable GPIO driver and command

[Michal Simek]

Enable GPIO command and Xilinx GPIO driver.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index c84b1a41655f..a65ed7966af5 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
 CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
 CONFIG_SPL_STACK=0x80200000
 CONFIG_SPL_TEXT_BASE=0x0
@@ -43,12 +44,17 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
 # CONFIG_SPL_CPU is not set
 CONFIG_SPL_REMAKE_ELF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPIO_READ=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_TIMER=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_LWIP=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_GPIO_HOG=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_XILINX_GPIO=y
 CONFIG_DM_MTD=y
 CONFIG_DM_MDIO=y
 CONFIG_DM_ETH_PHY=y
-- 
2.43.0

[PATCH 05/11] xilinx: mbv: Enable CMD_EXCEPTION

[Michal Simek]

Command is useful for testing the system and checking that exceptions are
working property that's why enable it by default.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index a65ed7966af5..4195fe0f05a1 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPL_REMAKE_ELF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPIO_READ=y
 CONFIG_CMD_SNTP=y
+CONFIG_CMD_EXCEPTION=y
 CONFIG_CMD_TIMER=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_LWIP=y
-- 
2.43.0

[PATCH 06/11] xilinx: mbv: Update stack, heap, and OpenSBI memory

[Michal Simek]

From: Padmarao Begari <padmarao.begari@amd.com>

A 2 MB region of DDR memory is allocated for U‑Boot SPL, with the
heap starting at address 0x80000000 and the stack at 0x80200000.
However, U‑Boot fails when using OpenSBI v1.8 because OpenSBI begins
execution at 0x80100000, causing an overlap between the SPL stack
and the malloc region.
To resolve this conflict, the SPL heap and stack are moved to
higher memory addresses, and OpenSBI is relocated to 0x80000000.
The SPL heap now starts at 0x8C000000, and the stack is placed
at 0x8F000000. The MB-V requires at least 256MB of DDR to run U-Boot.

	_________________
	|		|0x8FFFFFFF
	|_______________|
	|  SPL- Stack	|0x8F000000
	|		|
	|		|
	|  SPL - Heap	|
	|_______________|0x8C000000
	|		|
	|		|
	| Full U-Boot	|
	|_______________|0x81200000
	|Load FIT Image |
	|_______________|0x80200000
	|   OpenSBI     |
	|_______________|0x80000000

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig       | 4 ++--
 configs/xilinx_mbv32_smode_defconfig | 2 +-
 configs/xilinx_mbv64_smode_defconfig | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 4195fe0f05a1..d75d7e2e8ed4 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -9,7 +9,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
-CONFIG_SPL_STACK=0x80200000
+CONFIG_SPL_STACK=0x8F000000
 CONFIG_SPL_TEXT_BASE=0x0
 CONFIG_SPL_BSS_START_ADDR=0xf000
 CONFIG_SPL_BSS_MAX_SIZE=0x1000
@@ -40,7 +40,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 CONFIG_SPL_MAX_SIZE=0xf000
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
-CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x8C000000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
 # CONFIG_SPL_CPU is not set
 CONFIG_SPL_REMAKE_ELF=y
diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig
index dd1221a6904f..a72f13851acc 100644
--- a/configs/xilinx_mbv32_smode_defconfig
+++ b/configs/xilinx_mbv32_smode_defconfig
@@ -1,5 +1,5 @@
 #include <configs/xilinx_mbv32_defconfig>
 
-CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80000000
 CONFIG_RISCV_SMODE=y
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
diff --git a/configs/xilinx_mbv64_smode_defconfig b/configs/xilinx_mbv64_smode_defconfig
index 56bf0bdc7e4f..d7cf108692d6 100644
--- a/configs/xilinx_mbv64_smode_defconfig
+++ b/configs/xilinx_mbv64_smode_defconfig
@@ -1,5 +1,5 @@
 #include <configs/xilinx_mbv64_defconfig>
 
-CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
+CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80000000
 CONFIG_RISCV_SMODE=y
 CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
-- 
2.43.0

[PATCH 07/11] xilinx: mbv: Add support for using bigger boot images via bootm

[Michal Simek]

Current limit is 8MB which is quite low that's why increase it to 128MB
(default value) which should be more then enough for the kernel with cpio.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index d75d7e2e8ed4..258b65ceaa68 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -13,7 +13,6 @@ CONFIG_SPL_STACK=0x8F000000
 CONFIG_SPL_TEXT_BASE=0x0
 CONFIG_SPL_BSS_START_ADDR=0xf000
 CONFIG_SPL_BSS_MAX_SIZE=0x1000
-CONFIG_SYS_BOOTM_LEN=0x800000
 CONFIG_SYS_LOAD_ADDR=0x80200000
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_HAVE_INIT_STACK=y
-- 
2.43.0

[PATCH 08/11] xilinx: mbv: Add sys prompt for mbv32 and mbv64

[Michal Simek]

From: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>

Define CONFIG_SYS_PROMPT for the mbv32 and mbv64 device so the
U-Boot prompt is consistent with other AMD devices.

Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig | 1 +
 configs/xilinx_mbv64_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 258b65ceaa68..3543ff345f45 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -43,6 +43,7 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x8C000000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
 # CONFIG_SPL_CPU is not set
 CONFIG_SPL_REMAKE_ELF=y
+CONFIG_SYS_PROMPT="mbv32> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPIO_READ=y
 CONFIG_CMD_SNTP=y
diff --git a/configs/xilinx_mbv64_defconfig b/configs/xilinx_mbv64_defconfig
index 27d674fc34fb..69ab269619d6 100644
--- a/configs/xilinx_mbv64_defconfig
+++ b/configs/xilinx_mbv64_defconfig
@@ -2,3 +2,4 @@
 
 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
 CONFIG_ARCH_RV64I=y
+CONFIG_SYS_PROMPT="mbv64> "
-- 
2.43.0

[PATCH 09/11] xilinx: mbv: Disable SPL raw image support

[Michal Simek]

From: Padmarao Begari <padmarao.begari@amd.com>

When there is no valid image in SPI flash, SPL falls back to raw
image mode, copies the flash contents to CONFIG_TEXT_BASE, and
jumps there, causing an illegal instruction exception.

Disable raw image support so that a missing SPI image returns an
error and allows SPL to fall back to the next boot device.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 3543ff345f45..2fa464ae9213 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -37,6 +37,7 @@ CONFIG_DISPLAY_BOARDINFO=y
 # CONFIG_BOARD_INIT is not set
 # CONFIG_BOARD_LATE_INIT is not set
 CONFIG_SPL_MAX_SIZE=0xf000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SYS_MALLOC=y
 CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x8C000000
-- 
2.43.0

[PATCH 10/11] xilinx: mbv: Add SPI-related board config

[Michal Simek]

From: Padmarao Begari <padmarao.begari@amd.com>

Add SPI-related configuration to enable SPI flash support for
U-Boot SPL. This allows SPL to boot from SPI flash and load
the FIT image from offset 0x10000.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv_spi.config | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 configs/xilinx_mbv_spi.config

diff --git a/configs/xilinx_mbv_spi.config b/configs/xilinx_mbv_spi.config
new file mode 100644
index 000000000000..34b744e8ac1d
--- /dev/null
+++ b/configs/xilinx_mbv_spi.config
@@ -0,0 +1,14 @@
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPL_SPI=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000
+CONFIG_BOOTDEV_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI=y
+CONFIG_XILINX_SPI=y
-- 
2.43.0

[PATCH 11/11] xilinx: mbv: Enable MTD command by default

[Michal Simek]

Enable MTD command to be able to handle MTD layouts.

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 configs/xilinx_mbv32_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
index 2fa464ae9213..6d5f5b5eafc2 100644
--- a/configs/xilinx_mbv32_defconfig
+++ b/configs/xilinx_mbv32_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPL_REMAKE_ELF=y
 CONFIG_SYS_PROMPT="mbv32> "
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPIO_READ=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_EXCEPTION=y
 CONFIG_CMD_TIMER=y
-- 
2.43.0