Re: [PATCH 4/5] phy: qcom: snps-femto-v2: Move PHY init registers to config tables

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>,
	Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Manivannan Sadhasivam <mani@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Wesley Cheng <quic_wcheng@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] phy: qcom: snps-femto-v2: Move PHY init registers to config tables
Date: Tue, 25 Aug 2026 10:54:58 +0200	[thread overview]
Message-ID: <d3d075ac-598a-4b79-8d59-556657edb23b@oss.qualcomm.com> (raw)
In-Reply-To: <20260824-phy-v1-4-257d68a3210b@oss.qualcomm.com>

On 8/24/26 8:37 AM, Varadarajan Narayanan wrote:
> The driver currently programs the common PHY register sequence directly in
> qcom_snps_hsphy_init(), with the fixed register writes split around the
> override parameter handling. This makes it hard to support SoCs that need a
> different sequence or different values.
> 
> Move the fixed pre- and post-override register programming into per-
> compatible configuration tables, and keep the 7 nm override parameters in
> the same match-data structure. This allows the driver to share the common
> sequence while adding SoC-specific sequences for future platforms such as
> IPQ9650.
> 
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
> ---

[...]

> +	for (tmp = data->pre; tmp->offset != UINT_MAX; tmp++)

"pre"/"post" alone are not descriptive - perhaps pre_tuning/post_tuning?
Or do we maybe know whether the order matters at all?
> +		qcom_snps_hsphy_write_mask(hsphy->base, tmp->offset, tmp->mask, tmp->val);

Custom termination is both error-prone and memory-inefficient, add
another int to size the arrays

Konrad

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