All of lore.kernel.org
 help / color / mirror / Atom feed
From: Baolu Lu <baolu.lu@linux.intel.com>
To: "Camacho Romero, Michal" <michal.camacho.romero@intel.com>
Cc: "iommu@lists.linux.dev" <iommu@lists.linux.dev>,
	"Fedko, Artem" <artem.fedko@intel.com>,
	"Mowka, Mateusz" <mateusz.mowka@intel.com>,
	"Pawlicki, AdamX" <adamx.pawlicki@intel.com>,
	"Michalak, BartlomiejX" <bartlomiejx.michalak@intel.com>
Subject: Re: [PATCH 3/3] iommu: intel: Disable TPRs to allow Kernel for the further DMA usage
Date: Mon, 19 May 2025 10:09:32 +0800	[thread overview]
Message-ID: <d6a25c70-3b4b-4832-97e6-2c1915ffa373@linux.intel.com> (raw)
In-Reply-To: <IA1PR11MB7755B7E81479BC3BC5B11281AF93A@IA1PR11MB7755.namprd11.prod.outlook.com>

On 5/16/25 17:19, Camacho Romero, Michal wrote:
> In order to enable DMA for the Linux Kernel, working on the newest Intel 
> CPUs versions,
> 
> it is necessary to disable TPR memory protection, set earlier by the 
> Intel's SINIT ACM module.

Can you please explain what's the impact if TPR memory protection is not
disabled?

> 
> Disable also the Intel IOMMU enforcement, in the situation, where
> 
> the TPRs have been activated.

Can you please explain the reason why ...?

> 
> This patch depends on the 2 other patches:
> 
> * [PATCH 2/3] tboot: Define DTPR ACPI Table parsing function
> 
> * [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR

I assume that all three patches are in a series. So no need to mention
this in the commit message.

> Signed-off-by: Michal Camacho Romero michal.camacho.romero@intel.com 
> <mailto:michal.camacho.romero@intel.com>
> 
> ---
> 
> drivers/iommu/intel/dmar.c  | 8 ++++++++
> 
> drivers/iommu/intel/iommu.c | 7 ++++++-
> 
> 2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> 
> index e540092d664d..616db46c3a12 100644
> 
> --- a/drivers/iommu/intel/dmar.c
> 
> +++ b/drivers/iommu/intel/dmar.c
> 
> @@ -635,6 +635,7 @@ static int __init
> 
> parse_dmar_table(void)
> 
> {
> 
>             struct acpi_table_dmar *dmar;
> 
> +          struct acpi_table_dtpr *dtpr;
> 
>             int drhd_count = 0;
> 
>             int ret;
> 
>             struct dmar_res_callback cb = {
> 
> @@ -670,6 +671,13 @@ parse_dmar_table(void)
> 
>                         return -EINVAL;
> 
>             }
> 
> +          dtpr = tboot_get_dtpr_table();
> 
> +          if (dtpr) {
> 
> +                      //TPR is enabled
> 
> +                      //This will also tell not to establish IOMMU PMRs
> 
> +                      tboot_parse_dtpr_table();
> 
> +          }

Why do you want to put DPPR ACPI table parsing logic in this helper?

> 
> +
> 
>             pr_info("Host address width %d\n", dmar->width + 1);
> 
>             ret = dmar_walk_dmar_table(dmar, &cb);
> 
>             if (ret == 0 && drhd_count == 0)
> 
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> 
> index cb0b993bebb4..a0250a321b5e 100644
> 
> --- a/drivers/iommu/intel/iommu.c
> 
> +++ b/drivers/iommu/intel/iommu.c
> 
> @@ -3074,6 +3074,11 @@ static __init int tboot_force_iommu(void)
> 
>             if (!tboot_enabled())
> 
>                         return 0;
> 
> +          //If TPR is enabled we don't need to force IOMMU,
> 
> +          //TPR set by SINIT ACM will take care of DMA protection

Please use

	/* xxx */

comment style in this file to keep it with the existing ones.

> 
> +          if (tboot_is_tpr_enabled())
> 
> +                      return 0;
> 
> +
> 
>             if (no_iommu || dmar_disabled)
> 
>                         pr_warn("Forcing Intel-IOMMU to enabled\n");
> 
> @@ -3131,7 +3136,7 @@ int __init intel_iommu_init(void)
> 
>                          * calling SENTER, but the kernel is expected to 
> reset/tear
> 
>                          * down the PMRs.
> 
>                          */
> 
> -                       if (intel_iommu_tboot_noforce) {
> 
> +                      if (intel_iommu_tboot_noforce || 
> tboot_is_tpr_enabled()) {
> 
>                                     for_each_iommu(iommu, drhd)
> 
>                                                 
> iommu_disable_protect_mem_regions(iommu);
> 
>                         }
> 
> -- 
> 
> 2.43.0
> 

Thanks,
baolu

      parent reply	other threads:[~2025-05-19  2:14 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <IA1PR11MB77556710DD26474B9B857408AF93A@IA1PR11MB7755.namprd11.prod.outlook.com>
2025-05-16 20:40 ` [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR Wysocki, Rafael J
2025-05-20  8:44   ` Camacho Romero, Michal
     [not found] ` <IA1PR11MB7755A29CB6DE24B485C71F31AF93A@IA1PR11MB7755.namprd11.prod.outlook.com>
     [not found]   ` <IA1PR11MB7755B7E81479BC3BC5B11281AF93A@IA1PR11MB7755.namprd11.prod.outlook.com>
2025-05-19  2:09     ` Baolu Lu [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=d6a25c70-3b4b-4832-97e6-2c1915ffa373@linux.intel.com \
    --to=baolu.lu@linux.intel.com \
    --cc=adamx.pawlicki@intel.com \
    --cc=artem.fedko@intel.com \
    --cc=bartlomiejx.michalak@intel.com \
    --cc=iommu@lists.linux.dev \
    --cc=mateusz.mowka@intel.com \
    --cc=michal.camacho.romero@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.