Re: [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR

Re: [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR

[Wysocki, Rafael J]

On 5/16/2025 10:28 AM, Camacho Romero, Michal wrote:
>
> Hello @Moore, Robert <mailto:robert.moore@intel.com>, @Wysocki, Rafael 
> J <mailto:rafael.j.wysocki@intel.com>
>
> According to the latest version of the Intel TXT DMA Protection Ranges 
> specification
>
> (Revision 0.73), there were defined a new the ACPI Table, structure 
> and registers, which will be used to handle TPRs:
>
> *    DTPR ACPI Table
>
> *    TPR Base Register
>
> *    TPR Serialize Request Register
>
> *    TPR Limit Register
>
> *    TPR Instance Structure
>
> *    DMAR TXT Protected Reporting Structure
>
> Link: 
> https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Protection_Ranges_rev_0p73.pdf
>
> Signed-off-by: Michal Camacho Romero michal.camacho.romero@intel.com
>
Can you please submit this as a pull request to the upstream ACPICA 
project on GitHub?


> ---
>
> include/acpi/actbl1.h | 86 +++++++++++++++++++++++++++++++++++++++++++
>
> 1 file changed, 86 insertions(+)
>
> diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
>
> index 387fc821703a..14802feb54fd 100644
>
> --- a/include/acpi/actbl1.h
>
> +++ b/include/acpi/actbl1.h
>
> @@ -47,6 +47,7 @@
>
> #define ACPI_SIG_HPET "HPET"           /* High Precision Event Timer 
> table */
>
> #define ACPI_SIG_IBFT           "IBFT"  /* iSCSI Boot Firmware Table */
>
> #define ACPI_SIG_MSCT "MSCT"         /* Maximum System Characteristics 
> Table */
>
> +#define ACPI_SIG_DTPR           "DTPR"  /* TXT DMA Protection Ranges 
> reporting table */
>
>  #define ACPI_SIG_S3PT           "S3PT" /* S3 Performance (sub)Table */
>
> #define ACPI_SIG_PCCS           "PCC" /* PCC Shared Memory Region */
>
> @@ -1953,6 +1954,91 @@ struct acpi_ibft_target {
>
>            u16 reverse_chap_secret_offset;
>
> };
>
> +/*******************************************************************************
>
> + *
>
> + * DTPR - DMA TPR Reporting
>
> + *        Version 1
>
> + *
>
> + * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA 
> Protection
>
> + *              Ranges",
>
> + * Revision 0.73, August 2021
>
> + *
>
> + 
> ******************************************************************************/
>
> +
>
> +struct acpi_table_dtpr {
>
> +          struct acpi_table_header header;
>
> +          u32 flags; // 36
>
> +};
>
> +
>
> +struct acpi_tpr_array {
>
> +          u64 base;
>
> +};
>
> +
>
> +struct acpi_dtpr_instance {
>
> +          u32 flags;
>
> +          u32 tpr_cnt;
>
> +          struct acpi_tpr_array tpr_array[];
>
> +};
>
> +
>
> +/*******************************************************************************
>
> + * TPRn_BASE
>
> + *
>
> + * Specifies the start address of TPRn region. TPR region address and 
> size must
>
> + * be with 1MB resolution. These bits are compared with the result of the
>
> + * TPRn_LIMIT[63:20] * applied to the incoming address, to determine 
> if an
>
> + * access fall within the TPRn defined region.
>
> +*******************************************************************************/
>
> +struct acpi_dtprn_base_reg {
>
> +          u64 reserved0 : 3;
>
> +          u64 rw : 1; // access: 1 == RO, 0 == RW (for TPR must be RW)
>
> +          u64 enable : 1; // 0 == range enabled, 1 == range disabled
>
> +          u64 reserved1 : 15;
>
> +          u64 tpr_base_rw : 44; // Minimal TPRn_Base resolution is 1MB.
>
> +   // Applied to the incoming address, to determine if an
>
> +   // access fall within the TPRn defined region.
>
> +   // Width is determined by a bus width which can be
>
> +   // obtainedvia CPUID function 0x80000008.
>
> +          //u64 unused : 1;
>
> +};
>
> +
>
> +/*******************************************************************************
>
> + * TPRn_LIMIT
>
> + *
>
> + * This register defines an isolated region of memory that can be enabled
>
> + * to prohibit certain system agents from accessing memory. When an agent
>
> + * sends a request upstream, whether snooped or not, a TPR prevents that
>
> + * transaction from changing the state of memory.
>
> +*******************************************************************************/
>
> +
>
> +struct acpi_dtprn_limit_reg {
>
> +          u64 reserved0 : 3;
>
> +          u64 rw : 1; // access: 1 == RO, 0 == RW (for TPR must be RW)
>
> +          u64 enable : 1; // 0 == range enabled, 1 == range disabled
>
> +          u64 reserved1 : 15;
>
> +          u64 tpr_limit_rw : 44; // Minimal TPRn_Limit resolution is 1MB.
>
> +    // These bits define TPR limit address.
>
> +    // Width is determined by a bus width.
>
> +
>
> +          //u64 unused : 1;
>
> +};
>
> +
>
> +/*******************************************************************************
>
> + * SERIALIZE_REQUEST
>
> + *
>
> + * This register is used to request serialization of non-coherent DMA
>
> + * transactions. OS shall  issue it before changing of TPR settings
>
> + * (base / size).
>
> +*******************************************************************************/
>
> +
>
> +struct acpi_tpr_serialize_request {
>
> +          u64 sts : 1; // Status of serialization request (RO)
>
> +                       // 0 == register idle, 1 == serialization in 
> progress
>
> +          u64 ctrl : 1; // Control field to initiate serialization (RW)
>
> +                        // 0 == normal, 1 == initialize serialization
>
> +   // (self-clear to allow multiple serialization requests)
>
> +          u64 unused : 62;
>
> +};
>
> +
>
> /* Reset to default packing */
>
>  #pragma pack()
>
> -- 
>
> 2.43.0
>

RE: [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR

[Camacho Romero, Michal]

Hello @Wysocki, Rafael J, @Moore, Robert,

I've created a new PR on the ACPICA repository from the given Kernel patch: https://github.com/acpica/acpica/pull/1026

Could you please review this PR?

Regards,
Camacho Romero, Michal

-----Original Message-----
From: Wysocki, Rafael J <rafael.j.wysocki@intel.com> 
Sent: Friday, May 16, 2025 10:41 PM
To: Camacho Romero, Michal <michal.camacho.romero@intel.com>
Cc: linux-acpi@vger.kernel.org; Mowka, Mateusz <mateusz.mowka@intel.com>; Fedko, Artem <artem.fedko@intel.com>; Pawlicki, AdamX <adamx.pawlicki@intel.com>; Michalak, BartlomiejX <bartlomiejx.michalak@intel.com>; acpica-devel@lists.linux.dev; Moore, Robert <robert.moore@intel.com>; Dumbre, Saket <saket.dumbre@intel.com>
Subject: Re: [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR

On 5/16/2025 10:28 AM, Camacho Romero, Michal wrote:
>
> Hello @Moore, Robert <mailto:robert.moore@intel.com>, @Wysocki, Rafael 
> J <mailto:rafael.j.wysocki@intel.com>
>
> According to the latest version of the Intel TXT DMA Protection Ranges 
> specification
>
> (Revision 0.73), there were defined a new the ACPI Table, structure 
> and registers, which will be used to handle TPRs:
>
> *    DTPR ACPI Table
>
> *    TPR Base Register
>
> *    TPR Serialize Request Register
>
> *    TPR Limit Register
>
> *    TPR Instance Structure
>
> *    DMAR TXT Protected Reporting Structure
>
> Link: 
> https://uefi.org/sites/default/files/resources/633933_Intel_TXT_DMA_Pr
> otection_Ranges_rev_0p73.pdf
>
> Signed-off-by: Michal Camacho Romero michal.camacho.romero@intel.com
>
Can you please submit this as a pull request to the upstream ACPICA project on GitHub?


> ---
>
> include/acpi/actbl1.h | 86 +++++++++++++++++++++++++++++++++++++++++++
>
> 1 file changed, 86 insertions(+)
>
> diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
>
> index 387fc821703a..14802feb54fd 100644
>
> --- a/include/acpi/actbl1.h
>
> +++ b/include/acpi/actbl1.h
>
> @@ -47,6 +47,7 @@
>
> #define ACPI_SIG_HPET "HPET"           /* High Precision Event Timer 
> table */
>
> #define ACPI_SIG_IBFT           "IBFT"  /* iSCSI Boot Firmware Table */
>
> #define ACPI_SIG_MSCT "MSCT"         /* Maximum System Characteristics 
> Table */
>
> +#define ACPI_SIG_DTPR           "DTPR"  /* TXT DMA Protection Ranges 
> reporting table */
>
>  #define ACPI_SIG_S3PT           "S3PT" /* S3 Performance (sub)Table */
>
> #define ACPI_SIG_PCCS           "PCC" /* PCC Shared Memory Region */
>
> @@ -1953,6 +1954,91 @@ struct acpi_ibft_target {
>
>            u16 reverse_chap_secret_offset;
>
> };
>
> +/*******************************************************************************
>
> + *
>
> + * DTPR - DMA TPR Reporting
>
> + *        Version 1
>
> + *
>
> + * Conforms to "Intel® Trusted Execution Technology (Intel® TXT) DMA 
> Protection
>
> + *              Ranges",
>
> + * Revision 0.73, August 2021
>
> + *
>
> + 
> ******************************************************************************/
>
> +
>
> +struct acpi_table_dtpr {
>
> +          struct acpi_table_header header;
>
> +          u32 flags; // 36
>
> +};
>
> +
>
> +struct acpi_tpr_array {
>
> +          u64 base;
>
> +};
>
> +
>
> +struct acpi_dtpr_instance {
>
> +          u32 flags;
>
> +          u32 tpr_cnt;
>
> +          struct acpi_tpr_array tpr_array[];
>
> +};
>
> +
>
> +/*******************************************************************************
>
> + * TPRn_BASE
>
> + *
>
> + * Specifies the start address of TPRn region. TPR region address and 
> size must
>
> + * be with 1MB resolution. These bits are compared with the result of the
>
> + * TPRn_LIMIT[63:20] * applied to the incoming address, to determine 
> if an
>
> + * access fall within the TPRn defined region.
>
> +*******************************************************************************/
>
> +struct acpi_dtprn_base_reg {
>
> +          u64 reserved0 : 3;
>
> +          u64 rw : 1; // access: 1 == RO, 0 == RW (for TPR must be RW)
>
> +          u64 enable : 1; // 0 == range enabled, 1 == range disabled
>
> +          u64 reserved1 : 15;
>
> +          u64 tpr_base_rw : 44; // Minimal TPRn_Base resolution is 1MB.
>
> +   // Applied to the incoming address, to determine if an
>
> +   // access fall within the TPRn defined region.
>
> +   // Width is determined by a bus width which can be
>
> +   // obtainedvia CPUID function 0x80000008.
>
> +          //u64 unused : 1;
>
> +};
>
> +
>
> +/*******************************************************************************
>
> + * TPRn_LIMIT
>
> + *
>
> + * This register defines an isolated region of memory that can be enabled
>
> + * to prohibit certain system agents from accessing memory. When an agent
>
> + * sends a request upstream, whether snooped or not, a TPR prevents that
>
> + * transaction from changing the state of memory.
>
> +*******************************************************************************/
>
> +
>
> +struct acpi_dtprn_limit_reg {
>
> +          u64 reserved0 : 3;
>
> +          u64 rw : 1; // access: 1 == RO, 0 == RW (for TPR must be RW)
>
> +          u64 enable : 1; // 0 == range enabled, 1 == range disabled
>
> +          u64 reserved1 : 15;
>
> +          u64 tpr_limit_rw : 44; // Minimal TPRn_Limit resolution is 1MB.
>
> +    // These bits define TPR limit address.
>
> +    // Width is determined by a bus width.
>
> +
>
> +          //u64 unused : 1;
>
> +};
>
> +
>
> +/*******************************************************************************
>
> + * SERIALIZE_REQUEST
>
> + *
>
> + * This register is used to request serialization of non-coherent DMA
>
> + * transactions. OS shall  issue it before changing of TPR settings
>
> + * (base / size).
>
> +*******************************************************************************/
>
> +
>
> +struct acpi_tpr_serialize_request {
>
> +          u64 sts : 1; // Status of serialization request (RO)
>
> +                       // 0 == register idle, 1 == serialization in 
> progress
>
> +          u64 ctrl : 1; // Control field to initiate serialization (RW)
>
> +                        // 0 == normal, 1 == initialize serialization
>
> +   // (self-clear to allow multiple serialization requests)
>
> +          u64 unused : 62;
>
> +};
>
> +
>
> /* Reset to default packing */
>
>  #pragma pack()
>
> -- 
>
> 2.43.0
>
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Re: [PATCH 3/3] iommu: intel: Disable TPRs to allow Kernel for the further DMA usage

[Baolu Lu]

On 5/16/25 17:19, Camacho Romero, Michal wrote:
> In order to enable DMA for the Linux Kernel, working on the newest Intel 
> CPUs versions,
> 
> it is necessary to disable TPR memory protection, set earlier by the 
> Intel's SINIT ACM module.

Can you please explain what's the impact if TPR memory protection is not
disabled?

> 
> Disable also the Intel IOMMU enforcement, in the situation, where
> 
> the TPRs have been activated.

Can you please explain the reason why ...?

> 
> This patch depends on the 2 other patches:
> 
> * [PATCH 2/3] tboot: Define DTPR ACPI Table parsing function
> 
> * [PATCH 1/3]: ACPICA: actbl1.h: Add support for the new ACPI Table: DTPR

I assume that all three patches are in a series. So no need to mention
this in the commit message.

> Signed-off-by: Michal Camacho Romero michal.camacho.romero@intel.com 
> <mailto:michal.camacho.romero@intel.com>
> 
> ---
> 
> drivers/iommu/intel/dmar.c  | 8 ++++++++
> 
> drivers/iommu/intel/iommu.c | 7 ++++++-
> 
> 2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c
> 
> index e540092d664d..616db46c3a12 100644
> 
> --- a/drivers/iommu/intel/dmar.c
> 
> +++ b/drivers/iommu/intel/dmar.c
> 
> @@ -635,6 +635,7 @@ static int __init
> 
> parse_dmar_table(void)
> 
> {
> 
>             struct acpi_table_dmar *dmar;
> 
> +          struct acpi_table_dtpr *dtpr;
> 
>             int drhd_count = 0;
> 
>             int ret;
> 
>             struct dmar_res_callback cb = {
> 
> @@ -670,6 +671,13 @@ parse_dmar_table(void)
> 
>                         return -EINVAL;
> 
>             }
> 
> +          dtpr = tboot_get_dtpr_table();
> 
> +          if (dtpr) {
> 
> +                      //TPR is enabled
> 
> +                      //This will also tell not to establish IOMMU PMRs
> 
> +                      tboot_parse_dtpr_table();
> 
> +          }

Why do you want to put DPPR ACPI table parsing logic in this helper?

> 
> +
> 
>             pr_info("Host address width %d\n", dmar->width + 1);
> 
>             ret = dmar_walk_dmar_table(dmar, &cb);
> 
>             if (ret == 0 && drhd_count == 0)
> 
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> 
> index cb0b993bebb4..a0250a321b5e 100644
> 
> --- a/drivers/iommu/intel/iommu.c
> 
> +++ b/drivers/iommu/intel/iommu.c
> 
> @@ -3074,6 +3074,11 @@ static __init int tboot_force_iommu(void)
> 
>             if (!tboot_enabled())
> 
>                         return 0;
> 
> +          //If TPR is enabled we don't need to force IOMMU,
> 
> +          //TPR set by SINIT ACM will take care of DMA protection

Please use

	/* xxx */

comment style in this file to keep it with the existing ones.

> 
> +          if (tboot_is_tpr_enabled())
> 
> +                      return 0;
> 
> +
> 
>             if (no_iommu || dmar_disabled)
> 
>                         pr_warn("Forcing Intel-IOMMU to enabled\n");
> 
> @@ -3131,7 +3136,7 @@ int __init intel_iommu_init(void)
> 
>                          * calling SENTER, but the kernel is expected to 
> reset/tear
> 
>                          * down the PMRs.
> 
>                          */
> 
> -                       if (intel_iommu_tboot_noforce) {
> 
> +                      if (intel_iommu_tboot_noforce || 
> tboot_is_tpr_enabled()) {
> 
>                                     for_each_iommu(iommu, drhd)
> 
>                                                 
> iommu_disable_protect_mem_regions(iommu);
> 
>                         }
> 
> -- 
> 
> 2.43.0
> 

Thanks,
baolu