From: "Timur Kristóf" <timur.kristof@gmail.com>
To: Jesse Zhang <Jesse.Zhang@amd.com>, amd-gfx@lists.freedesktop.org
Cc: Alexander.Deucher@amd.com,
Christian Koenig <christian.koenig@amd.com>,
Lijo.Lazar@amd.com, Mario.Novales@amd.com, Manu.Rastogi@amd.com,
Jiongyu.Zhu@amd.com
Subject: Re: [PATCH v3 02/15] drm/amdgpu: complete the guilty fence at the end of a multi ring reset
Date: Tue, 03 Nov 2026 21:12:12 +0100 [thread overview]
Message-ID: <d744c7dedfc32ba6f1a66731eb9aa196f46af941.camel@gmail.com> (raw)
In-Reply-To: <20261028085736.3808569-2-Jesse.Zhang@amd.com>
On Wed, 2026-10-28 at 16:56 +0800, Jesse Zhang wrote:
> amdgpu_ring_backup_unprocessed_commands() skips the backup of a ring
> and
> clears ring->guilty_fence when it sees the same guilty fence again,
> to
> avoid replay loops. That happens when the IP block soft reset follows
> a
> failed ring reset of the same job.
> amdgpu_multi_ring_reset_helper_end()
> then restored the guilty ring with ring->guilty_fence, NULL by then,
> so
> neither the guilty fence nor the rest of the ring was completed: the
> hung
> job stayed pending until it timed out again.
>
> Pass the guilty fence to the end helper, and use it for the guilty
> ring.
> For the other rings, and when the backup didn't drop it, nothing
> changes.
>
> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 13 ++++++++++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++-
> 3 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c
> index d0b0d3eaffc5..2eea18965fd1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c
> @@ -469,7 +469,8 @@ int amdgpu_device_ip_soft_reset(struct
> amdgpu_ring *guilty_ring,
>
> r = ip_block->version->funcs->soft_reset(ip_block);
>
> - r = amdgpu_multi_ring_reset_helper_end(adev, ring_type_mask,
> guilty_ring, r);
> + r = amdgpu_multi_ring_reset_helper_end(adev, ring_type_mask,
> guilty_ring,
> + guilty_fence, r);
> amdgpu_device_unlock_reset_domain(adev->reset_domain);
>
> if (r) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index edae764eb0c4..7f0f0ae6650a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -1038,6 +1038,7 @@ void
> amdgpu_multi_ring_reset_helper_begin(struct amdgpu_device *adev,
> * @adev: amdgpu device
> * @ring_type_mask: Bitmask of affected ring types
> * @guilty_ring: The ring which is guilty of causing a reset, or
> NULL.
> + * @guilty_fence: The fence which didn't signal on the guilty ring.
> * @ret: Return code from the reset function.
> *
> * After calling amdgpu_multi_ring_reset_helper_begin()
> @@ -1050,7 +1051,8 @@ void
> amdgpu_multi_ring_reset_helper_begin(struct amdgpu_device *adev,
> */
> int amdgpu_multi_ring_reset_helper_end(struct amdgpu_device *adev,
> const u32 ring_type_mask,
> - struct amdgpu_ring
> *guilty_ring, int ret)
> + struct amdgpu_ring
> *guilty_ring,
> + struct amdgpu_fence
> *guilty_fence, int ret)
> {
> struct amdgpu_ring *ring;
> int i, r;
> @@ -1080,8 +1082,13 @@ int amdgpu_multi_ring_reset_helper_end(struct
> amdgpu_device *adev,
> if (!(BIT(ring->funcs->type) & ring_type_mask))
> continue;
>
> - /* Restore contents of the ring */
> - r = amdgpu_ring_reset_helper_end(ring, ring-
> >guilty_fence);
> + /*
> + * Restore contents of the ring. The backup of the
> guilty ring
> + * may have dropped its guilty fence, eg. after a
> failed ring
> + * reset with the same fence: still complete it.
> + */
> + r = amdgpu_ring_reset_helper_end(ring, ring ==
> guilty_ring ?
> + guilty_fence :
> ring->guilty_fence);
Can you help me understand what was wrong with the line before?
I think guilty_fence == ring->guilty_fence when ring == guilty_ring no?
> if (r) {
> dev_err(adev->dev,
> "Failed to recover ring %s after
> soft reset\n",
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 7e6ed43771f2..349c7d503e5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -643,7 +643,8 @@ void amdgpu_multi_ring_reset_helper_begin(struct
> amdgpu_device *adev,
> struct amdgpu_fence
> *guilty_fence);
> int amdgpu_multi_ring_reset_helper_end(struct amdgpu_device *adev,
> const u32 ring_type_mask,
> - struct amdgpu_ring
> *guilty_ring, int ret);
> + struct amdgpu_ring
> *guilty_ring,
> + struct amdgpu_fence
> *guilty_fence, int ret);
> bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,
> u32 reset_type);
> #endif
next prev parent reply other threads:[~2026-11-03 20:12 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-28 8:56 [PATCH v3 01/15] drm/amdgpu: pass the device to the multi ring reset helpers Jesse Zhang
2026-10-28 8:56 ` [PATCH v3 02/15] drm/amdgpu: complete the guilty fence at the end of a multi ring reset Jesse Zhang
2026-11-03 20:12 ` Timur Kristóf [this message]
2026-11-04 2:46 ` Zhang, Jesse(Jie)
2026-11-04 22:46 ` Timur Kristóf
2026-11-05 2:09 ` Zhang, Jesse(Jie)
2026-11-05 8:54 ` Timur Kristóf
2026-10-28 8:56 ` [PATCH v3 03/15] drm/amdgpu: add an engine scope to the IP block soft reset Jesse Zhang
2026-11-03 20:15 ` Timur Kristóf
2026-11-04 3:32 ` Zhang, Jesse(Jie)
2026-11-04 22:49 ` Timur Kristóf
2026-11-05 2:41 ` Zhang, Jesse(Jie)
2026-10-28 8:56 ` [PATCH v3 04/15] drm/amdgpu/gfx: add a reset_engine callback Jesse Zhang
2026-11-03 20:16 ` Timur Kristóf
2026-10-28 8:56 ` [PATCH v3 05/15] drm/amdgpu/gfx12: add a gfx engine reset Jesse Zhang
2026-10-28 8:56 ` [PATCH v3 06/15] drm/amdgpu/gfx11: " Jesse Zhang
2026-11-03 20:22 ` Timur Kristóf
2026-10-28 8:56 ` [PATCH v3 07/15] drm/amdgpu/gfx: add callbacks to read and restore the ring state of a gfx queue Jesse Zhang
2026-11-03 20:29 ` Timur Kristóf
2026-10-28 8:56 ` [PATCH v3 08/15] drm/amdgpu/gfx12: " Jesse Zhang
2026-10-28 8:56 ` [PATCH v3 09/15] drm/amdgpu/gfx11: " Jesse Zhang
2026-10-28 8:56 ` [PATCH v3 10/15] drm/amdgpu/userq: add a helper to signal the fences of a queue up to a point Jesse Zhang
2026-10-28 8:56 ` [PATCH v3 11/15] drm/amdgpu/userq: add helpers to keep the user queues of one engine across a reset Jesse Zhang
2026-11-03 20:37 ` Timur Kristóf
2026-10-28 8:56 ` [PATCH v3 12/15] drm/amdgpu/gfx: add a gfx engine soft reset Jesse Zhang
2026-11-03 20:38 ` Timur Kristóf
2026-10-28 8:56 ` [PATCH v3 13/15] drm/amdgpu/userq: reset the gfx engine when a gfx user queue reset fails Jesse Zhang
2026-10-28 8:56 ` [PATCH v3 14/15] drm/amdgpu/gfx12: enable the gfx engine soft reset Jesse Zhang
2026-10-28 8:56 ` [PATCH v3 15/15] drm/amdgpu/gfx11: " Jesse Zhang
2026-11-03 20:41 ` Timur Kristóf
2026-11-04 5:54 ` Zhang, Jesse(Jie)
2026-11-04 22:51 ` Timur Kristóf
2026-11-02 1:28 ` [PATCH v3 01/15] drm/amdgpu: pass the device to the multi ring reset helpers Zhang, Jesse(Jie)
2026-11-02 16:24 ` Timur Kristóf
2026-11-04 1:45 ` Zhang, Jesse(Jie)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=d744c7dedfc32ba6f1a66731eb9aa196f46af941.camel@gmail.com \
--to=timur.kristof@gmail.com \
--cc=Alexander.Deucher@amd.com \
--cc=Jesse.Zhang@amd.com \
--cc=Jiongyu.Zhu@amd.com \
--cc=Lijo.Lazar@amd.com \
--cc=Manu.Rastogi@amd.com \
--cc=Mario.Novales@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=christian.koenig@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.