All of lore.kernel.org
 help / color / mirror / Atom feed
From: Paul Walmsley <pjw@kernel.org>
To: torvalds@linux-foundation.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [GIT PULL] RISC-V updates for v7.3-rc1
Date: Thu, 20 Aug 2026 11:04:52 -0600 (MDT)	[thread overview]
Message-ID: <d788ab68-c0de-69a3-a36d-b968d6de9b7a@kernel.org> (raw)

[-- Attachment #1: Type: text/plain, Size: 13498 bytes --]

Linus,

Please pull these RISC-V updates for v7.3-rc1.  From a maintenance
point of view, there's a new header file include added into one of the
ACPI driver files.  This doesn't affect existing ACPI-enabled
architectures.

thanks

- Paul


The following changes since commit 994dad686e755477e2b2700cca4e6e1a90a58bdc:

  riscv: hwprobe: Register unaligned probes before usermode (2026-08-07 17:36:22 -0600)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux tags/riscv-for-linus-7.3-mw1

for you to fetch changes up to 8da45c93dfa98f25b148512d92ecfa75d027a5cc:

  RISC-V: hwprobe: Use BIT macro to avoid warnings (2026-08-07 19:24:34 -0600)

----------------------------------------------------------------
RISC-V updates for v7.3

- Add initial definitions and discovery for the Smcsrind, Sscsrind,
  Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse,
  Za64rs, and Ssqosid RISC-V ISA extensions

- Improve the RISC-V update_mmu_cache_range() implementation by using
  flush-by-ASID, enabling performance improvements on
  microarchitectures that support related optimizations; and by taking
  advantage of the Svinval RISC-V ISA extension on microarchitectures
  that support it

- Shrink CFI shadow stack allocation further (to 512MB) to save
  virtual address space (and physical memory on systems with strict
  overcommit policies)

- Add initial CPU context switch support for QoS tagging (Ssqosid)

- Change our vector misaligned access speed test code to be
  synchronous, avoiding a bunch of bugs related to unnecessary
  asynchronicity

- Enable ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V to help with ACPI
  table debugging (similar to ARM64 and x86)

- Extract vDSO section offsets at build time, rather than run time, to
  avoid the boot time overhead

- Use assembler directives to control the use of instructions from the
  RISC-V ISA extensions Zacas and Zabha, rather than compiler -march
  flags that could affect the whole kernel (similar to ARM64)

- Add a kselftest for kprobes support for the c.jal instruction on
  RISC-V

- When UEFI runtime services are available, use them to restart and
  power off

- Fix ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V by adding a missing
  include file to the ACPI code

- Move contiguous DMA memory reservation later in the boot, to ensure
  that the correct global and per-node pools are allocated when
  CONFIG_CMA_SIZE_PERNUMA is enabled

- Disallow probes on breakpoint handlers to avoid recursing
  indefinitely into do_trap_break()

- Patch the compat vDSO during runtime alternatives processing, not
  only the standard vDSO

- Remove some leftover XIP support elements missed by commit
  9b3a2be84803 ("riscv: Remove support for XIP kernel")

- Fix broadcast timer switching in ACPI LPI power states by
  implementing a RISC-V version of arch_get_idle_state_flags()

- Miscellaneous fixes, including: vDSO makefile simplification;
  marking our default_power_off() as __noreturn; error path fixes in
  the PMU SBI perf driver; RISC-V extension capitalization
  consistency; the use of BIT() macros in one of our include files;
  and some documentation fixes

----------------------------------------------------------------
Andrew Jones (1):
      riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe

Atish Patra (10):
      riscv: efi: Power off via EFI runtime services when available
      riscv: Restart via EFI runtime services when available
      RISC-V: perf: fix resource cleanup on driver probe failure
      RISC-V: Add Smcsrind and Sscsrind ISA extension definition and parsing
      dt-bindings: riscv: add Smcsrind and Sscsrind ISA extension descriptions
      RISC-V: Define indirect CSR access helpers
      RISC-V: Add Smcntrpmf extension parsing
      dt-bindings: riscv: add Smcntrpmf ISA extension description
      RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
      dt-bindings: riscv: add Counter delegation ISA extensions description

Charlie Jenkins (1):
      riscv: Standardize extension capitalization

Drew Fustini (3):
      dt-bindings: riscv: Add Ssqosid extension description
      riscv: Detect the Ssqosid extension
      riscv: Add support for srmcfg CSR from Ssqosid extension

Eder Zulian (1):
      riscv: mm: Move dma_contiguous_reserve() after NUMA initialization

Guodong Xu (1):
      riscv: cpufeature: Clarify ISA spec version for canonical order

Jesse Taube (2):
      riscv: Add Zicclsm to cpufeature and hwprobe
      RISC-V: hwprobe: Use BIT macro to avoid warnings

Jisheng Zhang (1):
      riscv: further remove XIP

Kaiwen Xue (2):
      RISC-V: Add Smcsrind and Sscsrind ISA extension CSR definitions
      RISC-V: Add Ssccfg extension CSR definition

Nam Cao (3):
      riscv: kprobes: add test case for c.jal instruction simulation
      riscv: unaligned: stop using kthread for check_vector_unaligned_access()
      Revert "riscv: hwprobe: Fix stale vDSO data for late-initialized keys at boot"

Peixin Xie (1):
      riscv: acpi: Handle LPI architectural context loss flags

Rui Qi (1):
      riscv: kprobes: Prevent probes in breakpoint handlers

Thomas Weißschuh (4):
      riscv: vdso: Simplify cflags remove logic
      riscv: vdso: Add symbols for the alternative section boundaries
      riscv: alternative: Use the statically extracted vDSO section offsets
      riscv: alternative: Also patch the compat vDSO

Thorsten Blum (1):
      riscv: Mark default_power_off() as __noreturn

Vivian Wang (3):
      ACPI: tables: Add missing #include <asm/fixmap.h>
      riscv: acpi: Enable ARCH_HAS_ACPI_TABLE_UPGRADE
      riscv: cmpxchg: Use .option arch for Zacas and Zabha

Xiaofeng Yuan (1):
      riscv: probes: simulate c.jal instruction

Xu Lu (2):
      riscv: mm: Use ASID in update_mmu_cache()
      riscv: mm: Apply Svinval in update_mmu_cache()

Zong Li (1):
      riscv: cfi: reduce shadow stack size limit from 2GB to 512MB

 Documentation/arch/riscv/hwprobe.rst               |  20 +++
 .../devicetree/bindings/riscv/extensions.yaml      |  69 ++++++++++
 MAINTAINERS                                        |   8 ++
 arch/riscv/Kconfig                                 |  19 +++
 arch/riscv/Makefile                                |  10 +-
 arch/riscv/boot/.gitignore                         |   1 -
 arch/riscv/boot/Makefile                           |   3 +-
 arch/riscv/include/asm/acpi.h                      |  21 +++
 arch/riscv/include/asm/cmpxchg.h                   |  14 +-
 arch/riscv/include/asm/csr.h                       |  53 +++++++
 arch/riscv/include/asm/csr_indirect.h              |  50 +++++++
 arch/riscv/include/asm/hwcap.h                     |  30 ++--
 arch/riscv/include/asm/hwprobe.h                   |   7 -
 arch/riscv/include/asm/pgtable.h                   |  12 +-
 arch/riscv/include/asm/processor.h                 |   3 +
 arch/riscv/include/asm/qos.h                       |  74 ++++++++++
 arch/riscv/include/asm/switch_to.h                 |   7 +-
 arch/riscv/include/asm/tlbflush.h                  |  23 ++++
 arch/riscv/include/asm/vdso.h                      |   6 +
 arch/riscv/include/asm/vdso/arch_data.h            |   6 -
 arch/riscv/include/uapi/asm/hwprobe.h              | 152 +++++++++++----------
 arch/riscv/kernel/Makefile                         |   2 +
 arch/riscv/kernel/acpi.c                           |   5 +
 arch/riscv/kernel/alternative.c                    |  33 +++--
 arch/riscv/kernel/cpufeature.c                     |  80 +++++++----
 arch/riscv/kernel/efi.c                            |   5 +
 arch/riscv/kernel/probes/decode-insn.c             |   2 +-
 arch/riscv/kernel/probes/simulate-insn.c           |   7 +
 arch/riscv/kernel/probes/simulate-insn.h           |   1 +
 arch/riscv/kernel/qos.c                            | 101 ++++++++++++++
 arch/riscv/kernel/reset.c                          |   9 +-
 arch/riscv/kernel/setup.c                          |   2 +
 arch/riscv/kernel/sys_hwprobe.c                    |  79 +++--------
 arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S |  24 ++++
 arch/riscv/kernel/traps.c                          |   3 +
 arch/riscv/kernel/unaligned_access_speed.c         |  19 +--
 arch/riscv/kernel/usercfi.c                        |   4 +-
 arch/riscv/kernel/vdso/Makefile                    |   7 +-
 arch/riscv/kernel/vdso/hwprobe.c                   |   2 +-
 arch/riscv/kernel/vdso/vdso.lds.S                  |   2 +
 arch/riscv/kernel/vmlinux-xip.lds.S                | 143 -------------------
 arch/riscv/kvm/isa.c                               |  16 +--
 arch/riscv/kvm/main.c                              |   2 +-
 arch/riscv/kvm/vcpu_fp.c                           |  20 +--
 arch/riscv/kvm/vcpu_onereg.c                       |   6 +-
 arch/riscv/kvm/vcpu_vector.c                       |  10 +-
 arch/riscv/mm/init.c                               |   3 +-
 arch/riscv/mm/tlbflush.c                           |  23 ----
 drivers/acpi/tables.c                              |   1 +
 drivers/perf/riscv_pmu_sbi.c                       |  33 ++++-
 50 files changed, 794 insertions(+), 438 deletions(-)
 create mode 100644 arch/riscv/include/asm/csr_indirect.h
 create mode 100644 arch/riscv/include/asm/qos.h
 create mode 100644 arch/riscv/kernel/qos.c
 delete mode 100644 arch/riscv/kernel/vmlinux-xip.lds.S

vmlinux size differences in bytes (from 994dad686e75):
  text   data   bss     dec    hex  filename                             
 +2916  +3652   +24   +6592  +19c0  vmlinux.defconfig.gcc-16             
 +6980  +3660   +24  +10664  +29a8  vmlinux.nosmp_defconfig.gcc-16       
 +1956     +8     .   +1964   +7ac  vmlinux.rv32_defconfig.gcc-16        
 +1784    -16     .   +1768   +6e8  vmlinux.rv32_nosmp_defconfig.gcc-16  
  +652   +432     .   +1084   +43c  vmlinux.nommu_virt_defconfig.gcc-16  
 +4336  +3560     .   +7896  +1ed8  vmlinux.defconfig.clang-20           
 +4408  +3560     .   +7968  +1f20  vmlinux.nosmp_defconfig.clang-20     
 +1704    -40     .   +1664   +680  vmlinux.rv32_defconfig.clang-20      
 +1804  +2328     .   +4132  +1024  vmlinux.rv32_nosmp_defconfig.clang-20
  +676  -3664     .   -2988   -bac  vmlinux.nommu_virt_defconfig.clang-20
 +2936  +3684   +24   +6644  +19f4  vmlinux.defconfig.gcc-15             
 +2804  +3660   +24   +6488  +1958  vmlinux.nosmp_defconfig.gcc-15       
 +1660    +96     .   +1756   +6dc  vmlinux.rv32_defconfig.gcc-15        
 +1268    +80     .   +1348   +544  vmlinux.rv32_nosmp_defconfig.gcc-15  
  +652   +432     .   +1084   +43c  vmlinux.nommu_virt_defconfig.gcc-15  
 +2788  +3620   +24   +6432  +1920  vmlinux.defconfig.gcc-14             
 +2820  +3620   +24   +6464  +1940  vmlinux.nosmp_defconfig.gcc-14       
 +1660     +8     .   +1668   +684  vmlinux.rv32_defconfig.gcc-14        
 +1644     +8     .   +1652   +674  vmlinux.rv32_nosmp_defconfig.gcc-14  
  +652   +496     .   +1148   +47c  vmlinux.nommu_virt_defconfig.gcc-14  
 +4552  +3592   +24   +8168  +1fe8  vmlinux.defconfig.clang-19           
 +4608  +3048   +24   +7680  +1e00  vmlinux.nosmp_defconfig.clang-19     
 +1932   -548     .   +1384   +568  vmlinux.rv32_defconfig.clang-19      
 +1872  +2324     .   +4196  +1064  vmlinux.rv32_nosmp_defconfig.clang-19
  +660  -3664     .   -3004   -bbc  vmlinux.nommu_virt_defconfig.clang-19
 +2932  +3620   +24   +6576  +19b0  vmlinux.defconfig.gcc-13             
 +2968  +3564   +24   +6556  +199c  vmlinux.nosmp_defconfig.gcc-13       
 +1584      .     .   +1584   +630  vmlinux.rv32_defconfig.gcc-13        
 +1644    -16     .   +1628   +65c  vmlinux.rv32_nosmp_defconfig.gcc-13  
  +640   +496     .   +1136   +470  vmlinux.nommu_virt_defconfig.gcc-13  
 +4512  +3592   +24   +8128  +1fc0  vmlinux.defconfig.clang-18           
 +4588  +3560   +24   +8172  +1fec  vmlinux.nosmp_defconfig.clang-18     
 +1664    -68     .   +1596   +63c  vmlinux.rv32_defconfig.clang-18      
 +1896  +2356     .   +4252  +109c  vmlinux.rv32_nosmp_defconfig.clang-18
  +660   +496     .   +1156   +484  vmlinux.nommu_virt_defconfig.clang-18
 +2996  +7588   +24  +10608  +2970  vmlinux.defconfig.gcc-12             
 +3004  +3588   +24   +6616  +19d8  vmlinux.nosmp_defconfig.gcc-12       
 +1144    +32     .   +1176   +498  vmlinux.rv32_defconfig.gcc-12        
 +1572    +40     .   +1612   +64c  vmlinux.rv32_nosmp_defconfig.gcc-12  
  +644  -3664     .   -3020   -bcc  vmlinux.nommu_virt_defconfig.gcc-12  
 +4908  +3592   +24   +8524  +214c  vmlinux.defconfig.clang-17           
 +4960  +3592   +24   +8576  +2180  vmlinux.nosmp_defconfig.clang-17     
 +2172   -516     .   +1656   +678  vmlinux.rv32_defconfig.clang-17      
 +2268    -12     .   +2256   +8d0  vmlinux.rv32_nosmp_defconfig.clang-17
  +668   +432     .   +1100   +44c  vmlinux.nommu_virt_defconfig.clang-17
 +2844  +3524   +24   +6392  +18f8  vmlinux.defconfig.gcc-11             
 +3008  +3556   +24   +6588  +19bc  vmlinux.nosmp_defconfig.gcc-11       
 +1020    +40     .   +1060   +424  vmlinux.rv32_defconfig.gcc-11        
 +1640    +40     .   +1680   +690  vmlinux.rv32_nosmp_defconfig.gcc-11  
  +652  -3664     .   -3012   -bc4  vmlinux.nommu_virt_defconfig.gcc-11  
  +838    +48     .    +886   +376  vmlinux.allnoconfig.gcc-15           
+57248  +4612  -128  +61732  +f124  vmlinux.allmodconfig.gcc-15          
  +346  -4036     .   -3690   -e6a  vmlinux.allnoconfig.clang-19         
+30136  +8116  +120  +38372  +95e4  vmlinux.allmodconfig.clang-19        

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <pjw@kernel.org>
To: torvalds@linux-foundation.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [GIT PULL] RISC-V updates for v7.3-rc1
Date: Thu, 20 Aug 2026 11:04:52 -0600 (MDT)	[thread overview]
Message-ID: <d788ab68-c0de-69a3-a36d-b968d6de9b7a@kernel.org> (raw)

[-- Attachment #1: Type: text/plain, Size: 13498 bytes --]

Linus,

Please pull these RISC-V updates for v7.3-rc1.  From a maintenance
point of view, there's a new header file include added into one of the
ACPI driver files.  This doesn't affect existing ACPI-enabled
architectures.

thanks

- Paul


The following changes since commit 994dad686e755477e2b2700cca4e6e1a90a58bdc:

  riscv: hwprobe: Register unaligned probes before usermode (2026-08-07 17:36:22 -0600)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux tags/riscv-for-linus-7.3-mw1

for you to fetch changes up to 8da45c93dfa98f25b148512d92ecfa75d027a5cc:

  RISC-V: hwprobe: Use BIT macro to avoid warnings (2026-08-07 19:24:34 -0600)

----------------------------------------------------------------
RISC-V updates for v7.3

- Add initial definitions and discovery for the Smcsrind, Sscsrind,
  Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse,
  Za64rs, and Ssqosid RISC-V ISA extensions

- Improve the RISC-V update_mmu_cache_range() implementation by using
  flush-by-ASID, enabling performance improvements on
  microarchitectures that support related optimizations; and by taking
  advantage of the Svinval RISC-V ISA extension on microarchitectures
  that support it

- Shrink CFI shadow stack allocation further (to 512MB) to save
  virtual address space (and physical memory on systems with strict
  overcommit policies)

- Add initial CPU context switch support for QoS tagging (Ssqosid)

- Change our vector misaligned access speed test code to be
  synchronous, avoiding a bunch of bugs related to unnecessary
  asynchronicity

- Enable ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V to help with ACPI
  table debugging (similar to ARM64 and x86)

- Extract vDSO section offsets at build time, rather than run time, to
  avoid the boot time overhead

- Use assembler directives to control the use of instructions from the
  RISC-V ISA extensions Zacas and Zabha, rather than compiler -march
  flags that could affect the whole kernel (similar to ARM64)

- Add a kselftest for kprobes support for the c.jal instruction on
  RISC-V

- When UEFI runtime services are available, use them to restart and
  power off

- Fix ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V by adding a missing
  include file to the ACPI code

- Move contiguous DMA memory reservation later in the boot, to ensure
  that the correct global and per-node pools are allocated when
  CONFIG_CMA_SIZE_PERNUMA is enabled

- Disallow probes on breakpoint handlers to avoid recursing
  indefinitely into do_trap_break()

- Patch the compat vDSO during runtime alternatives processing, not
  only the standard vDSO

- Remove some leftover XIP support elements missed by commit
  9b3a2be84803 ("riscv: Remove support for XIP kernel")

- Fix broadcast timer switching in ACPI LPI power states by
  implementing a RISC-V version of arch_get_idle_state_flags()

- Miscellaneous fixes, including: vDSO makefile simplification;
  marking our default_power_off() as __noreturn; error path fixes in
  the PMU SBI perf driver; RISC-V extension capitalization
  consistency; the use of BIT() macros in one of our include files;
  and some documentation fixes

----------------------------------------------------------------
Andrew Jones (1):
      riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe

Atish Patra (10):
      riscv: efi: Power off via EFI runtime services when available
      riscv: Restart via EFI runtime services when available
      RISC-V: perf: fix resource cleanup on driver probe failure
      RISC-V: Add Smcsrind and Sscsrind ISA extension definition and parsing
      dt-bindings: riscv: add Smcsrind and Sscsrind ISA extension descriptions
      RISC-V: Define indirect CSR access helpers
      RISC-V: Add Smcntrpmf extension parsing
      dt-bindings: riscv: add Smcntrpmf ISA extension description
      RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
      dt-bindings: riscv: add Counter delegation ISA extensions description

Charlie Jenkins (1):
      riscv: Standardize extension capitalization

Drew Fustini (3):
      dt-bindings: riscv: Add Ssqosid extension description
      riscv: Detect the Ssqosid extension
      riscv: Add support for srmcfg CSR from Ssqosid extension

Eder Zulian (1):
      riscv: mm: Move dma_contiguous_reserve() after NUMA initialization

Guodong Xu (1):
      riscv: cpufeature: Clarify ISA spec version for canonical order

Jesse Taube (2):
      riscv: Add Zicclsm to cpufeature and hwprobe
      RISC-V: hwprobe: Use BIT macro to avoid warnings

Jisheng Zhang (1):
      riscv: further remove XIP

Kaiwen Xue (2):
      RISC-V: Add Smcsrind and Sscsrind ISA extension CSR definitions
      RISC-V: Add Ssccfg extension CSR definition

Nam Cao (3):
      riscv: kprobes: add test case for c.jal instruction simulation
      riscv: unaligned: stop using kthread for check_vector_unaligned_access()
      Revert "riscv: hwprobe: Fix stale vDSO data for late-initialized keys at boot"

Peixin Xie (1):
      riscv: acpi: Handle LPI architectural context loss flags

Rui Qi (1):
      riscv: kprobes: Prevent probes in breakpoint handlers

Thomas Weißschuh (4):
      riscv: vdso: Simplify cflags remove logic
      riscv: vdso: Add symbols for the alternative section boundaries
      riscv: alternative: Use the statically extracted vDSO section offsets
      riscv: alternative: Also patch the compat vDSO

Thorsten Blum (1):
      riscv: Mark default_power_off() as __noreturn

Vivian Wang (3):
      ACPI: tables: Add missing #include <asm/fixmap.h>
      riscv: acpi: Enable ARCH_HAS_ACPI_TABLE_UPGRADE
      riscv: cmpxchg: Use .option arch for Zacas and Zabha

Xiaofeng Yuan (1):
      riscv: probes: simulate c.jal instruction

Xu Lu (2):
      riscv: mm: Use ASID in update_mmu_cache()
      riscv: mm: Apply Svinval in update_mmu_cache()

Zong Li (1):
      riscv: cfi: reduce shadow stack size limit from 2GB to 512MB

 Documentation/arch/riscv/hwprobe.rst               |  20 +++
 .../devicetree/bindings/riscv/extensions.yaml      |  69 ++++++++++
 MAINTAINERS                                        |   8 ++
 arch/riscv/Kconfig                                 |  19 +++
 arch/riscv/Makefile                                |  10 +-
 arch/riscv/boot/.gitignore                         |   1 -
 arch/riscv/boot/Makefile                           |   3 +-
 arch/riscv/include/asm/acpi.h                      |  21 +++
 arch/riscv/include/asm/cmpxchg.h                   |  14 +-
 arch/riscv/include/asm/csr.h                       |  53 +++++++
 arch/riscv/include/asm/csr_indirect.h              |  50 +++++++
 arch/riscv/include/asm/hwcap.h                     |  30 ++--
 arch/riscv/include/asm/hwprobe.h                   |   7 -
 arch/riscv/include/asm/pgtable.h                   |  12 +-
 arch/riscv/include/asm/processor.h                 |   3 +
 arch/riscv/include/asm/qos.h                       |  74 ++++++++++
 arch/riscv/include/asm/switch_to.h                 |   7 +-
 arch/riscv/include/asm/tlbflush.h                  |  23 ++++
 arch/riscv/include/asm/vdso.h                      |   6 +
 arch/riscv/include/asm/vdso/arch_data.h            |   6 -
 arch/riscv/include/uapi/asm/hwprobe.h              | 152 +++++++++++----------
 arch/riscv/kernel/Makefile                         |   2 +
 arch/riscv/kernel/acpi.c                           |   5 +
 arch/riscv/kernel/alternative.c                    |  33 +++--
 arch/riscv/kernel/cpufeature.c                     |  80 +++++++----
 arch/riscv/kernel/efi.c                            |   5 +
 arch/riscv/kernel/probes/decode-insn.c             |   2 +-
 arch/riscv/kernel/probes/simulate-insn.c           |   7 +
 arch/riscv/kernel/probes/simulate-insn.h           |   1 +
 arch/riscv/kernel/qos.c                            | 101 ++++++++++++++
 arch/riscv/kernel/reset.c                          |   9 +-
 arch/riscv/kernel/setup.c                          |   2 +
 arch/riscv/kernel/sys_hwprobe.c                    |  79 +++--------
 arch/riscv/kernel/tests/kprobes/test-kprobes-asm.S |  24 ++++
 arch/riscv/kernel/traps.c                          |   3 +
 arch/riscv/kernel/unaligned_access_speed.c         |  19 +--
 arch/riscv/kernel/usercfi.c                        |   4 +-
 arch/riscv/kernel/vdso/Makefile                    |   7 +-
 arch/riscv/kernel/vdso/hwprobe.c                   |   2 +-
 arch/riscv/kernel/vdso/vdso.lds.S                  |   2 +
 arch/riscv/kernel/vmlinux-xip.lds.S                | 143 -------------------
 arch/riscv/kvm/isa.c                               |  16 +--
 arch/riscv/kvm/main.c                              |   2 +-
 arch/riscv/kvm/vcpu_fp.c                           |  20 +--
 arch/riscv/kvm/vcpu_onereg.c                       |   6 +-
 arch/riscv/kvm/vcpu_vector.c                       |  10 +-
 arch/riscv/mm/init.c                               |   3 +-
 arch/riscv/mm/tlbflush.c                           |  23 ----
 drivers/acpi/tables.c                              |   1 +
 drivers/perf/riscv_pmu_sbi.c                       |  33 ++++-
 50 files changed, 794 insertions(+), 438 deletions(-)
 create mode 100644 arch/riscv/include/asm/csr_indirect.h
 create mode 100644 arch/riscv/include/asm/qos.h
 create mode 100644 arch/riscv/kernel/qos.c
 delete mode 100644 arch/riscv/kernel/vmlinux-xip.lds.S

vmlinux size differences in bytes (from 994dad686e75):
  text   data   bss     dec    hex  filename                             
 +2916  +3652   +24   +6592  +19c0  vmlinux.defconfig.gcc-16             
 +6980  +3660   +24  +10664  +29a8  vmlinux.nosmp_defconfig.gcc-16       
 +1956     +8     .   +1964   +7ac  vmlinux.rv32_defconfig.gcc-16        
 +1784    -16     .   +1768   +6e8  vmlinux.rv32_nosmp_defconfig.gcc-16  
  +652   +432     .   +1084   +43c  vmlinux.nommu_virt_defconfig.gcc-16  
 +4336  +3560     .   +7896  +1ed8  vmlinux.defconfig.clang-20           
 +4408  +3560     .   +7968  +1f20  vmlinux.nosmp_defconfig.clang-20     
 +1704    -40     .   +1664   +680  vmlinux.rv32_defconfig.clang-20      
 +1804  +2328     .   +4132  +1024  vmlinux.rv32_nosmp_defconfig.clang-20
  +676  -3664     .   -2988   -bac  vmlinux.nommu_virt_defconfig.clang-20
 +2936  +3684   +24   +6644  +19f4  vmlinux.defconfig.gcc-15             
 +2804  +3660   +24   +6488  +1958  vmlinux.nosmp_defconfig.gcc-15       
 +1660    +96     .   +1756   +6dc  vmlinux.rv32_defconfig.gcc-15        
 +1268    +80     .   +1348   +544  vmlinux.rv32_nosmp_defconfig.gcc-15  
  +652   +432     .   +1084   +43c  vmlinux.nommu_virt_defconfig.gcc-15  
 +2788  +3620   +24   +6432  +1920  vmlinux.defconfig.gcc-14             
 +2820  +3620   +24   +6464  +1940  vmlinux.nosmp_defconfig.gcc-14       
 +1660     +8     .   +1668   +684  vmlinux.rv32_defconfig.gcc-14        
 +1644     +8     .   +1652   +674  vmlinux.rv32_nosmp_defconfig.gcc-14  
  +652   +496     .   +1148   +47c  vmlinux.nommu_virt_defconfig.gcc-14  
 +4552  +3592   +24   +8168  +1fe8  vmlinux.defconfig.clang-19           
 +4608  +3048   +24   +7680  +1e00  vmlinux.nosmp_defconfig.clang-19     
 +1932   -548     .   +1384   +568  vmlinux.rv32_defconfig.clang-19      
 +1872  +2324     .   +4196  +1064  vmlinux.rv32_nosmp_defconfig.clang-19
  +660  -3664     .   -3004   -bbc  vmlinux.nommu_virt_defconfig.clang-19
 +2932  +3620   +24   +6576  +19b0  vmlinux.defconfig.gcc-13             
 +2968  +3564   +24   +6556  +199c  vmlinux.nosmp_defconfig.gcc-13       
 +1584      .     .   +1584   +630  vmlinux.rv32_defconfig.gcc-13        
 +1644    -16     .   +1628   +65c  vmlinux.rv32_nosmp_defconfig.gcc-13  
  +640   +496     .   +1136   +470  vmlinux.nommu_virt_defconfig.gcc-13  
 +4512  +3592   +24   +8128  +1fc0  vmlinux.defconfig.clang-18           
 +4588  +3560   +24   +8172  +1fec  vmlinux.nosmp_defconfig.clang-18     
 +1664    -68     .   +1596   +63c  vmlinux.rv32_defconfig.clang-18      
 +1896  +2356     .   +4252  +109c  vmlinux.rv32_nosmp_defconfig.clang-18
  +660   +496     .   +1156   +484  vmlinux.nommu_virt_defconfig.clang-18
 +2996  +7588   +24  +10608  +2970  vmlinux.defconfig.gcc-12             
 +3004  +3588   +24   +6616  +19d8  vmlinux.nosmp_defconfig.gcc-12       
 +1144    +32     .   +1176   +498  vmlinux.rv32_defconfig.gcc-12        
 +1572    +40     .   +1612   +64c  vmlinux.rv32_nosmp_defconfig.gcc-12  
  +644  -3664     .   -3020   -bcc  vmlinux.nommu_virt_defconfig.gcc-12  
 +4908  +3592   +24   +8524  +214c  vmlinux.defconfig.clang-17           
 +4960  +3592   +24   +8576  +2180  vmlinux.nosmp_defconfig.clang-17     
 +2172   -516     .   +1656   +678  vmlinux.rv32_defconfig.clang-17      
 +2268    -12     .   +2256   +8d0  vmlinux.rv32_nosmp_defconfig.clang-17
  +668   +432     .   +1100   +44c  vmlinux.nommu_virt_defconfig.clang-17
 +2844  +3524   +24   +6392  +18f8  vmlinux.defconfig.gcc-11             
 +3008  +3556   +24   +6588  +19bc  vmlinux.nosmp_defconfig.gcc-11       
 +1020    +40     .   +1060   +424  vmlinux.rv32_defconfig.gcc-11        
 +1640    +40     .   +1680   +690  vmlinux.rv32_nosmp_defconfig.gcc-11  
  +652  -3664     .   -3012   -bc4  vmlinux.nommu_virt_defconfig.gcc-11  
  +838    +48     .    +886   +376  vmlinux.allnoconfig.gcc-15           
+57248  +4612  -128  +61732  +f124  vmlinux.allmodconfig.gcc-15          
  +346  -4036     .   -3690   -e6a  vmlinux.allnoconfig.clang-19         
+30136  +8116  +120  +38372  +95e4  vmlinux.allmodconfig.clang-19        

             reply	other threads:[~2026-08-20 17:05 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-20 17:04 Paul Walmsley [this message]
2026-08-20 17:04 ` [GIT PULL] RISC-V updates for v7.3-rc1 Paul Walmsley
2026-08-20 21:57 ` pr-tracker-bot
2026-08-20 21:57   ` pr-tracker-bot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=d788ab68-c0de-69a3-a36d-b968d6de9b7a@kernel.org \
    --to=pjw@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=torvalds@linux-foundation.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.