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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Lee Jones <lee@kernel.org>
Cc: Xu Yilun <yilun.xu@intel.com>, Wu Hao <hao.wu@intel.com>,
	Tom Rix <trix@redhat.com>, Moritz Fischer <mdf@kernel.org>,
	linux-fpga@vger.kernel.org, Jean Delvare <jdelvare@suse.com>,
	Guenter Roeck <linux@roeck-us.net>,
	Russ Weight <russell.h.weight@intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	linux-hwmon@vger.kernel.org
Subject: Re: [PATCH v3 4/4] mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers
Date: Wed, 10 May 2023 14:51:07 +0300 (EEST)	[thread overview]
Message-ID: <dc53f4a2-b91f-e114-6da8-72cac82d508d@linux.intel.com> (raw)
In-Reply-To: <20230427150712.GV50521@google.com>

[-- Attachment #1: Type: text/plain, Size: 1557 bytes --]

On Thu, 27 Apr 2023, Lee Jones wrote:
> On Mon, 17 Apr 2023, Ilpo Järvinen wrote:
> > On some MAX 10 cards, the BMC firmware is not available to service
> > handshake registers during secure update erase and write phases at
> > normal speeds. This problem affects at least hwmon driver. When the MAX
> > 10 hwmon driver tries to read the sensor values during a secure update,
> > the reads are slowed down (e.g., reading all D5005 sensors takes ~24s
> > which is magnitudes worse than the normal <0.02s).
> > 
> > Manage access to the handshake registers using a rw semaphore and a FW
> > state variable to prevent accesses during those secure update phases
> > and return -EBUSY instead.
> > 
> > If handshake_sys_reg_nranges == 0, don't update bwcfw_state as it is not
> > used. This avoids the locking cost.
> > 
> > Co-developed-by: Russ Weight <russell.h.weight@intel.com>
> > Signed-off-by: Russ Weight <russell.h.weight@intel.com>
> > Co-developed-by: Xu Yilun <yilun.xu@intel.com>
> > Signed-off-by: Xu Yilun <yilun.xu@intel.com>
> > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > ---
> >  drivers/fpga/intel-m10-bmc-sec-update.c | 17 +++++--
> >  drivers/mfd/intel-m10-bmc-core.c        | 67 ++++++++++++++++++++++++-
> >  drivers/mfd/intel-m10-bmc-spi.c         | 14 ++++++
> >  include/linux/mfd/intel-m10-bmc.h       | 28 +++++++++++
> >  4 files changed, 121 insertions(+), 5 deletions(-)
> 
> Applied, thanks

Did these end up falling throught the cracks as I've not been able to 
locate where they were applied?


-- 
 i.

  reply	other threads:[~2023-05-10 11:52 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-17  9:26 [PATCH v3 0/4] intel-m10-bmc: Manage register access to control delay during sec update Ilpo Järvinen
2023-04-17  9:26 ` [PATCH v3 1/4] mfd: intel-m10-bmc: Move core symbols to own namespace Ilpo Järvinen
2023-04-20 16:08   ` Xu Yilun
2023-04-27 15:05   ` Lee Jones
2023-04-17  9:26 ` [PATCH v3 2/4] mfd: intel-m10-bmc: Create m10bmc_sys_update_bits() Ilpo Järvinen
2023-04-20 16:09   ` Xu Yilun
2023-04-21  9:52   ` Xu Yilun
2023-04-27 15:05   ` Lee Jones
2023-04-17  9:26 ` [PATCH v3 3/4] mfd: intel-m10-bmc: Move m10bmc_sys_read() away from header Ilpo Järvinen
2023-04-20 16:10   ` Xu Yilun
2023-04-27 15:06   ` Lee Jones
2023-04-17  9:26 ` [PATCH v3 4/4] mfd: intel-m10-bmc: Manage access to MAX 10 fw handshake registers Ilpo Järvinen
2023-04-20 16:07   ` Xu Yilun
2023-04-20 11:13     ` Lee Jones
2023-04-21  9:52       ` Xu Yilun
2023-04-27 15:07   ` Lee Jones
2023-05-10 11:51     ` Ilpo Järvinen [this message]
2023-05-15 10:06       ` Lee Jones

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