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From: matthew.gerlach@linux.intel.com
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: lpieralisi@kernel.org, kw@linux.com,
	manivannan.sadhasivam@linaro.org,  robh@kernel.org,
	bhelgaas@google.com, krzk+dt@kernel.org,  conor+dt@kernel.org,
	dinguyen@kernel.org, joyce.ooi@intel.com,
	 linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, matthew.gerlach@altera.com,
	 peter.colberg@altera.com
Subject: Re: [PATCH v7 2/7] dt-bindings: intel: document Agilex PCIe Root Port
Date: Mon, 17 Feb 2025 07:47:48 -0800 (PST)	[thread overview]
Message-ID: <dcd28035-6ba8-5d67-daa3-26812c4fc99d@linux.intel.com> (raw)
In-Reply-To: <20250216-ubiquitous-agile-spoonbill-cf12ab@krzk-bin>



On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:

> On Sat, Feb 15, 2025 at 09:53:54AM -0600, Matthew Gerlach wrote:
>> The Agilex7f devkit can support PCIe End Points with the appropriate
>> daughter card.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v7:
>>  - New patch to series.
>> ---
>>  Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> index 2ee0c740eb56..0da5810c9510 100644
>> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
>> @@ -20,6 +20,7 @@ properties:
>>                - intel,n5x-socdk
>>                - intel,socfpga-agilex-n6000
>>                - intel,socfpga-agilex-socdk
>> +              - intel,socfpga-agilex7f-socdk-pcie-root-port
>
> Compatible should represent the board, so what is here exactly the
> board? 7f? Agilex7f? socdk? Or is it standard agilex-socdk but with some
> things attached?

The board is the Agilex 7 FPGA F-Series Transceiver-Soc Development Kit:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agf014.html

There is not a single, standard agilex-socdk board. There are currently 
three variants. In addition to the F-Series socdk, there are I-Series and 
M-Series devkits:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agi027.html
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html

>
> But then, are they attached or you just creat the same board with
> different configuration?
The PCIe Root Port does involve a different FPGA configuration, but 
depending on the board, daughter cards and possibly cables are also 
involved.

>
> Best regards,
> Krzysztof
>
>
Thanks for the feedback,
Matthew Gerlach

  reply	other threads:[~2025-02-17 15:47 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-15 15:53 [PATCH v7 0/7] Add PCIe Root Port support for Agilex family of chips Matthew Gerlach
2025-02-15 15:53 ` [PATCH v7 1/7] dt-bindings: PCI: altera: Add binding for Agilex Matthew Gerlach
2025-02-15 15:53 ` [PATCH v7 2/7] dt-bindings: intel: document Agilex PCIe Root Port Matthew Gerlach
2025-02-16 11:56   ` Krzysztof Kozlowski
2025-02-17 15:47     ` matthew.gerlach [this message]
2025-02-18  7:25       ` Krzysztof Kozlowski
2025-02-18 22:51         ` matthew.gerlach
2025-02-15 15:53 ` [PATCH v7 3/7] arm64: dts: agilex: Fix fixed-clock schema warnings Matthew Gerlach
2025-02-16 11:58   ` Krzysztof Kozlowski
2025-02-18 21:44     ` matthew.gerlach
2025-02-19 23:53       ` matthew.gerlach
2025-02-15 15:53 ` [PATCH v7 4/7] arm64: dts: agilex: move bus@80000000 to socfpga_agilex.dtsi Matthew Gerlach
2025-02-15 15:53 ` [PATCH v7 5/7] arm64: dts: agilex: add dtsi for PCIe Root Port Matthew Gerlach
2025-02-15 15:53 ` [PATCH v7 6/7] arm64: dts: agilex: add dts enabling " Matthew Gerlach
2025-02-16 12:00   ` Krzysztof Kozlowski
2025-02-18 22:40     ` matthew.gerlach
2025-02-15 15:53 ` [PATCH v7 7/7] PCI: altera: Add Agilex support Matthew Gerlach

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