Re: [PATCH v7 6/7] arm64: dts: agilex: add dts enabling PCIe Root Port

[matthew.gerlach@linux.intel.com]

On Sun, 16 Feb 2025, Krzysztof Kozlowski wrote:

> On Sat, Feb 15, 2025 at 09:53:58AM -0600, Matthew Gerlach wrote:
>> Add a device tree enabling PCIe Root Port support on an Agilex F-series
>> Development Kit which has the P-tile variant of the PCIe IP.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v7:
>>  - Create and use appropriate board compatibility and use of model.
>>
>> v6:
>>  - Fix SPDX header.
>>  - Make compatible property first.
>>  - Fix comment line wrapping.
>>  - Don't include .dts.
>>
>> v3:
>>  - Remove accepted patches from patch set.
>> ---
>>  arch/arm64/boot/dts/intel/Makefile            |   1 +
>>  .../socfpga_agilex7f_socdk_pcie_root_port.dts | 147 ++++++++++++++++++
>>  2 files changed, 148 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>>
>> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
>> index d39cfb723f5b..737e81c3c3f7 100644
>> --- a/arch/arm64/boot/dts/intel/Makefile
>> +++ b/arch/arm64/boot/dts/intel/Makefile
>> @@ -2,6 +2,7 @@
>>  dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>>  				socfpga_agilex_socdk.dtb \
>>  				socfpga_agilex_socdk_nand.dtb \
>> +				socfpga_agilex7f_socdk_pcie_root_port.dtb \
>>  				socfpga_agilex5_socdk.dtb \
>>  				socfpga_n5x_socdk.dtb
>>  dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>> new file mode 100644
>> index 000000000000..19b14f88e32d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
>> @@ -0,0 +1,147 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2024, Intel Corporation
>> + */
>> +#include "socfpga_agilex.dtsi"
>> +#include "socfpga_agilex_pcie_root_port.dtsi"
>> +
>> +/ {
>> +	model = "SoCFPGA Agilex SoCDK";
>> +	compatible = "intel,socfpga-agilex7f-socdk-pcie-root-port", "intel,socfpga-agilex";
>
> So that's different SoC (Agilex F series)? Why isn't this expressed in
What was formally known as Agilex is now more precisely referred Agilex 7 
F series, Agilex 7 I series, or Agilex 7 M series. Yes, this should me 
reflected in the compatibles.

> compatibles? Is it different or the same board? If different, why
> "root-port" in board name? Is this how the product is named?

"root-port" refers to a particular board combined with a specific FPGA 
image and possibly a daughter card and cables. I am not sure that FPGA 
image specific DTS or DTSI should be in the kernel tree.

>
> Best regards,
> Krzysztof
>
>

Thanks for the feedback,
Matthew Gerlach