From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Linu Cherian <linu.cherian@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Ryan Roberts <ryan.roberts@arm.com>,
Kevin Brodsky <kevin.brodsky@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/6] arm64: cputype: Add C1-Nano definitions
Date: Fri, 10 Jul 2026 12:07:36 +0530 [thread overview]
Message-ID: <ddb34ff6-e9eb-43ae-86f0-bf49a355e5cf@arm.com> (raw)
In-Reply-To: <20260708144331.679816-3-linu.cherian@arm.com>
On 08/07/26 8:13 PM, Linu Cherian wrote:
> Add cputype definitions for C1-Nano.
>
> The definition can be found in C1-Nano TRM,
> https://developer.arm.com/documentation/107753/0002
> as part of MIDR_EL1 bit descriptions.
>
> This is going to be used in the bbml3 support list.
>
> Signed-off-by: Linu Cherian <linu.cherian@arm.com>
> ---
> arch/arm64/include/asm/cputype.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index e41fae46426b..1fa29616e586 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -100,6 +100,7 @@
> #define ARM_CPU_PART_CORTEX_A720AE 0xD89
> #define ARM_CPU_PART_C1_ULTRA 0xD8C
> #define ARM_CPU_PART_NEOVERSE_N3 0xD8E
> +#define ARM_CPU_PART_C1_NANO 0xD8A
> #define ARM_CPU_PART_C1_PRO 0xD8B
> #define ARM_CPU_PART_C1_PREMIUM 0xD90
>
> @@ -195,6 +196,7 @@
> #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE)
> #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA)
> #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3)
> +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO)
> #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
> #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
> #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
next prev parent reply other threads:[~2026-07-10 6:37 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 14:43 [PATCH v2 0/6] Add BBML3 cpu feature Linu Cherian
2026-07-08 14:43 ` [PATCH v2 1/6] arm64: cputype: Add Cortex-A520AE definitions Linu Cherian
2026-07-10 6:37 ` Anshuman Khandual
2026-07-08 14:43 ` [PATCH v2 2/6] arm64: cputype: Add C1-Nano definitions Linu Cherian
2026-07-10 6:37 ` Anshuman Khandual [this message]
2026-07-08 14:43 ` [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list Linu Cherian
2026-07-08 14:53 ` Suzuki K Poulose
2026-07-10 6:24 ` Anshuman Khandual
2026-07-14 13:43 ` Linu Cherian
2026-07-08 14:43 ` [PATCH v2 4/6] arm64: sysreg: Add BBM_3 Linu Cherian
2026-07-10 6:46 ` Anshuman Khandual
2026-07-08 14:43 ` [PATCH v2 5/6] arm64: cpufeature: Add BBML3 Linu Cherian
2026-07-10 7:00 ` Anshuman Khandual
2026-07-14 13:59 ` Linu Cherian
2026-07-08 14:43 ` [PATCH v2 6/6] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Linu Cherian
2026-07-10 7:11 ` Anshuman Khandual
2026-07-14 14:01 ` Linu Cherian
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