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From: Linu Cherian <linu.cherian@arm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Ryan Roberts <ryan.roberts@arm.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list
Date: Tue, 14 Jul 2026 19:13:05 +0530	[thread overview]
Message-ID: <alY86WOa-O2aguT7@a079125.arm.com> (raw)
In-Reply-To: <eab6908e-d897-4fd0-9626-ef2e0b553cc2@arm.com>

On Wed, Jul 08, 2026 at 03:53:59PM +0100, Suzuki K Poulose wrote:
> On 08/07/2026 15:43, Linu Cherian wrote:
> > Add below cpus to the midr list, which supports
> > BBML2_NOABORT.
> > 
> > Cortex A520(AE)
> > Cortex A715
> > Cortex A720(AE)
> > Cortex A725
> > Neoverse N3
> > C1-Nano
> > C1-Pro
> > C1-Ultra
> > C1-Premium
> > 
> > C1-Ultra and C1-Premium both suffer from erratum 3683289,
> > where Break-Before-Make must be followed to avoid a livelock.
> > For both CPUs, the erratum is fixed from r1p1.
> > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0.
> 
> Please could you also update the list of errata here :
> 
> Documentation/arch/arm64/silicon-errata.rst

Ack.

> 
> > 
> > The relevant SDENs are:
> > * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/
> > * C1-Premium: https://developer.arm.com/documentation/111078/9-00/
> > 
> > Signed-off-by: Linu Cherian <linu.cherian@arm.com>
> > ---
> >   arch/arm64/kernel/cpufeature.c | 9 +++++++++
> >   1 file changed, 9 insertions(+)
> > 
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 9a22df0c5120..adcabea80fcb 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void)
> >   		MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
> >   		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
> >   		MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> > +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
> > +		MIDR_ALL_VERSIONS(MIDR_C1_NANO),
> > +		MIDR_ALL_VERSIONS(MIDR_C1_PRO),
> 
> And mention it here, so that it is evident from the code alone ?
> 
Ack.

> > +		MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf),
> > +		MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf),
> 
> 
> Suzuki
> 
> 
> >   		{}
> >   	};
> 

  parent reply	other threads:[~2026-07-14 13:43 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08 14:43 [PATCH v2 0/6] Add BBML3 cpu feature Linu Cherian
2026-07-08 14:43 ` [PATCH v2 1/6] arm64: cputype: Add Cortex-A520AE definitions Linu Cherian
2026-07-10  6:37   ` Anshuman Khandual
2026-07-08 14:43 ` [PATCH v2 2/6] arm64: cputype: Add C1-Nano definitions Linu Cherian
2026-07-10  6:37   ` Anshuman Khandual
2026-07-08 14:43 ` [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list Linu Cherian
2026-07-08 14:53   ` Suzuki K Poulose
2026-07-10  6:24     ` Anshuman Khandual
2026-07-14 13:43     ` Linu Cherian [this message]
2026-07-08 14:43 ` [PATCH v2 4/6] arm64: sysreg: Add BBM_3 Linu Cherian
2026-07-10  6:46   ` Anshuman Khandual
2026-07-08 14:43 ` [PATCH v2 5/6] arm64: cpufeature: Add BBML3 Linu Cherian
2026-07-10  7:00   ` Anshuman Khandual
2026-07-14 13:59     ` Linu Cherian
2026-07-08 14:43 ` [PATCH v2 6/6] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Linu Cherian
2026-07-10  7:11   ` Anshuman Khandual
2026-07-14 14:01     ` Linu Cherian

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