From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v2 05/31] drm/xe: Long running job update
Date: Tue, 9 May 2023 17:21:39 +0200 [thread overview]
Message-ID: <df98676a-039b-d159-72c8-559c6ece606a@linux.intel.com> (raw)
In-Reply-To: <ZFpfM0cvsd76A+tY@DUT025-TGLU.fm.intel.com>
On 5/9/23 16:56, Matthew Brost wrote:
> On Mon, May 08, 2023 at 03:14:10PM +0200, Thomas Hellström wrote:
>> Hi, Matthew
>>
>> In addition to Rodrigo's comments:
>>
>> On 5/2/23 02:17, Matthew Brost wrote:
>>> Flow control + write ring in exec, return NULL in run_job, siganl
>>> xe_hw_fence immediately, and override TDR for LR jobs.
>>>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/xe_engine.c | 32 ++++++++
>>> drivers/gpu/drm/xe/xe_engine.h | 4 +
>>> drivers/gpu/drm/xe/xe_exec.c | 8 ++
>>> drivers/gpu/drm/xe/xe_guc_engine_types.h | 2 +
>>> drivers/gpu/drm/xe/xe_guc_submit.c | 95 +++++++++++++++++++++---
>>> drivers/gpu/drm/xe/xe_trace.h | 5 ++
>>> 6 files changed, 137 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_engine.c b/drivers/gpu/drm/xe/xe_engine.c
>>> index 094ec17d3004..d1e84d7adbd4 100644
>>> --- a/drivers/gpu/drm/xe/xe_engine.c
>>> +++ b/drivers/gpu/drm/xe/xe_engine.c
>>> @@ -18,6 +18,7 @@
>>> #include "xe_macros.h"
>>> #include "xe_migrate.h"
>>> #include "xe_pm.h"
>>> +#include "xe_ring_ops_types.h"
>>> #include "xe_trace.h"
>>> #include "xe_vm.h"
>>> @@ -673,6 +674,37 @@ static void engine_kill_compute(struct xe_engine *e)
>>> up_write(&e->vm->lock);
>>> }
>>> +/**
>>> + * xe_engine_is_lr() - Whether an engine is long-running
>>> + * @e: The engine
>>> + *
>>> + * Return: True if the engine is long-running, false otherwise.
>>> + */
>>> +bool xe_engine_is_lr(struct xe_engine *e)
>>> +{
>>> + return e->vm && xe_vm_no_dma_fences(e->vm) &&
>>> + !(e->flags & ENGINE_FLAG_VM);
>>> +}
>>> +
>>> +static s32 xe_engine_num_job_inflight(struct xe_engine *e)
>>> +{
>>> + return e->lrc->fence_ctx.next_seqno - xe_lrc_seqno(e->lrc) - 1;
>>> +}
>>> +
>>> +/**
>>> + * xe_engine_ring_full() - Whether an engine's ring is full
>>> + * @e: The engine
>>> + *
>>> + * Return: True if the engine's ring is full, false otherwise.
>>> + */
>>> +bool xe_engine_ring_full(struct xe_engine *e)
>>> +{
>>> + struct xe_lrc *lrc = e->lrc;
>>> + s32 max_job = lrc->ring.size / MAX_JOB_SIZE_BYTES;
>>> +
>>> + return xe_engine_num_job_inflight(e) >= max_job;
>>> +}
>>> +
>>> /**
>>> * xe_engine_is_idle() - Whether an engine is idle.
>>> * @engine: The engine
>>> diff --git a/drivers/gpu/drm/xe/xe_engine.h b/drivers/gpu/drm/xe/xe_engine.h
>>> index a49cf2ab405e..2e60f6d90226 100644
>>> --- a/drivers/gpu/drm/xe/xe_engine.h
>>> +++ b/drivers/gpu/drm/xe/xe_engine.h
>>> @@ -42,6 +42,10 @@ static inline bool xe_engine_is_parallel(struct xe_engine *engine)
>>> return engine->width > 1;
>>> }
>>> +bool xe_engine_is_lr(struct xe_engine *e);
>>> +
>>> +bool xe_engine_ring_full(struct xe_engine *e);
>>> +
>>> bool xe_engine_is_idle(struct xe_engine *engine);
>>> void xe_engine_kill(struct xe_engine *e);
>>> diff --git a/drivers/gpu/drm/xe/xe_exec.c b/drivers/gpu/drm/xe/xe_exec.c
>>> index ea869f2452ef..44ea9bcd0066 100644
>>> --- a/drivers/gpu/drm/xe/xe_exec.c
>>> +++ b/drivers/gpu/drm/xe/xe_exec.c
>>> @@ -13,6 +13,7 @@
>>> #include "xe_device.h"
>>> #include "xe_engine.h"
>>> #include "xe_macros.h"
>>> +#include "xe_ring_ops_types.h"
>>> #include "xe_sched_job.h"
>>> #include "xe_sync.h"
>>> #include "xe_vm.h"
>>> @@ -277,6 +278,11 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
>>> goto err_engine_end;
>>> }
>>> + if (xe_engine_is_lr(engine) && xe_engine_ring_full(engine)) {
>>> + err = -EWOULDBLOCK;
>>> + goto err_engine_end;
>>> + }
>>> +
>>> job = xe_sched_job_create(engine, xe_engine_is_parallel(engine) ?
>>> addresses : &args->address);
>>> if (IS_ERR(job)) {
>>> @@ -363,6 +369,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
>>> xe_sync_entry_signal(&syncs[i], job,
>>> &job->drm.s_fence->finished);
>>> + if (xe_engine_is_lr(engine))
>>> + engine->ring_ops->emit_job(job);
>>> xe_sched_job_push(job);
>>> xe_vm_reactivate_rebind(vm);
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_types.h b/drivers/gpu/drm/xe/xe_guc_engine_types.h
>>> index cbfb13026ec1..5d83132034a6 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_engine_types.h
>>> +++ b/drivers/gpu/drm/xe/xe_guc_engine_types.h
>>> @@ -31,6 +31,8 @@ struct xe_guc_engine {
>>> */
>>> #define MAX_STATIC_MSG_TYPE 3
>>> struct drm_sched_msg static_msgs[MAX_STATIC_MSG_TYPE];
>>> + /** @lr_tdr: long running TDR worker */
>>> + struct work_struct lr_tdr;
>>> /** @fini_async: do final fini async from this worker */
>>> struct work_struct fini_async;
>>> /** @resume_time: time of last resume */
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
>>> index 68d09e7a4cc0..0a41f5d04f6d 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
>>> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
>>> @@ -500,6 +500,14 @@ static void register_engine(struct xe_engine *e)
>>> parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE);
>>> }
>>> + /*
>>> + * We must keep a reference for LR engines if engine is registered with
>>> + * the GuC as jobs signal immediately and can't destroy an engine if the
>>> + * GuC has a reference to it.
>>> + */
>>> + if (xe_engine_is_lr(e))
>>> + xe_engine_get(e);
>>> +
>>> set_engine_registered(e);
>>> trace_xe_engine_register(e);
>>> if (xe_engine_is_parallel(e))
>>> @@ -662,6 +670,7 @@ guc_engine_run_job(struct drm_sched_job *drm_job)
>>> {
>>> struct xe_sched_job *job = to_xe_sched_job(drm_job);
>>> struct xe_engine *e = job->engine;
>>> + bool lr = xe_engine_is_lr(e);
>>> XE_BUG_ON((engine_destroyed(e) || engine_pending_disable(e)) &&
>>> !engine_banned(e) && !engine_suspended(e));
>>> @@ -671,14 +680,19 @@ guc_engine_run_job(struct drm_sched_job *drm_job)
>>> if (!engine_killed_or_banned(e) && !xe_sched_job_is_error(job)) {
>>> if (!engine_registered(e))
>>> register_engine(e);
>>> - e->ring_ops->emit_job(job);
>>> + if (!lr) /* Written in IOCTL */
>> Hmm? What does "Written in IOCTL mean?" Could you rephrase to something more
>> descriptive?
>>
> "LR jos are emitted in the IOCTL"
Ah, I read it as "the lr variable was written in IOCTL."
Perhaps LR jobs are already emitted at execbuf time?
/Thomas
>
> Does that work?
>
> Matt
>
>>> + e->ring_ops->emit_job(job);
>>> submit_engine(e);
>>> }
>>> - if (test_and_set_bit(JOB_FLAG_SUBMIT, &job->fence->flags))
>>> + if (lr) {
>>> + xe_sched_job_set_error(job, -ENOTSUPP);
>>> + return NULL;
>>> + } else if (test_and_set_bit(JOB_FLAG_SUBMIT, &job->fence->flags)) {
>>> return job->fence;
>>> - else
>>> + } else {
>>> return dma_fence_get(job->fence);
>>> + }
>>> }
>>> static void guc_engine_free_job(struct drm_sched_job *drm_job)
>>> @@ -782,6 +796,57 @@ static void simple_error_capture(struct xe_engine *e)
>>> }
>>> #endif
>>> +static void xe_guc_engine_trigger_cleanup(struct xe_engine *e)
>>> +{
>>> + struct xe_guc *guc = engine_to_guc(e);
>>> +
>>> + if (xe_engine_is_lr(e))
>>> + queue_work(guc_to_gt(guc)->ordered_wq, &e->guc->lr_tdr);
>>> + else
>>> + drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT);
>>> +}
>>> +
>>> +static void xe_guc_engine_lr_cleanup(struct work_struct *w)
>>> +{
>>> + struct xe_guc_engine *ge =
>>> + container_of(w, struct xe_guc_engine, lr_tdr);
>>> + struct xe_engine *e = ge->engine;
>>> + struct drm_gpu_scheduler *sched = &ge->sched;
>>> +
>>> + XE_BUG_ON(!xe_engine_is_lr(e));
>>> + trace_xe_engine_lr_cleanup(e);
>>> +
>>> + /* Kill the run_job / process_msg entry points */
>>> + drm_sched_run_wq_stop(sched);
>>> +
>>> + /* Engine state now stable, disable scheduling / deregister if needed */
>>> + if (engine_registered(e)) {
>>> + struct xe_guc *guc = engine_to_guc(e);
>>> + int ret;
>>> +
>>> + set_engine_banned(e);
>>> + xe_engine_get(e);
>>> + disable_scheduling_deregister(guc, e);
>>> +
>>> + /*
>>> + * Must wait for scheduling to be disabled before signalling
>>> + * any fences, if GT broken the GT reset code should signal us.
>>> + */
>>> + smp_rmb();
>> wait_event() paired with wake_up() family of functions typically set the
>> necessary barriers to make sure anything written prior to wake_up() is seen
>> in wait_event(). So that smp_rmb() is most likely not needed. If it still
>> is, its pairing smp_wmb() should be documented and pointed to as well. See
>> documentation of set_current_state() vs __set_current_state().
>>
>>> + ret = wait_event_timeout(guc->ct.wq,
>>> + !engine_pending_disable(e) ||
>>> + guc_read_stopped(guc), HZ * 5);
>>> + if (!ret) {
>>> + XE_WARN_ON("Schedule disable failed to respond");
>>> + drm_sched_run_wq_start(sched);
>>> + xe_gt_reset_async(e->gt);
>>> + return;
>>> + }
>>> + }
>>> +
>>> + drm_sched_run_wq_start(sched);
>>> +}
>>> +
>>> static enum drm_gpu_sched_stat
>>> guc_engine_timedout_job(struct drm_sched_job *drm_job)
>>> {
>>> @@ -832,7 +897,7 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job)
>>> err = -EIO;
>>> set_engine_banned(e);
>>> xe_engine_get(e);
>>> - disable_scheduling_deregister(engine_to_guc(e), e);
>>> + disable_scheduling_deregister(guc, e);
>>> /*
>>> * Must wait for scheduling to be disabled before signalling
>>> @@ -865,7 +930,7 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job)
>>> */
>>> list_add(&drm_job->list, &sched->pending_list);
>>> drm_sched_run_wq_start(sched);
>>> - drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT);
>>> + xe_guc_engine_trigger_cleanup(e);
>>> /* Mark all outstanding jobs as bad, thus completing them */
>>> spin_lock(&sched->job_list_lock);
>>> @@ -889,6 +954,8 @@ static void __guc_engine_fini_async(struct work_struct *w)
>>> trace_xe_engine_destroy(e);
>>> + if (xe_engine_is_lr(e))
>>> + cancel_work_sync(&ge->lr_tdr);
>>> if (e->flags & ENGINE_FLAG_PERSISTENT)
>>> xe_device_remove_persistent_engines(gt_to_xe(e->gt), e);
>>> release_guc_id(guc, e);
>>> @@ -906,7 +973,7 @@ static void guc_engine_fini_async(struct xe_engine *e)
>>> bool kernel = e->flags & ENGINE_FLAG_KERNEL;
>>> INIT_WORK(&e->guc->fini_async, __guc_engine_fini_async);
>>> - queue_work(system_unbound_wq, &e->guc->fini_async);
>>> + queue_work(system_wq, &e->guc->fini_async);
>>> /* We must block on kernel engines so slabs are empty on driver unload */
>>> if (kernel) {
>>> @@ -1089,12 +1156,16 @@ static int guc_engine_init(struct xe_engine *e)
>>> if (err)
>>> goto err_free;
>>> +
>> Unrelated whitespace?
>>
>>
>>> sched = &ge->sched;
>>> err = drm_sched_entity_init(&ge->entity, DRM_SCHED_PRIORITY_NORMAL,
>>> &sched, 1, NULL);
>>> if (err)
>>> goto err_sched;
>>> + if (xe_engine_is_lr(e))
>>> + INIT_WORK(&e->guc->lr_tdr, xe_guc_engine_lr_cleanup);
>>> +
>>> mutex_lock(&guc->submission_state.lock);
>>> err = alloc_guc_id(guc, e);
>>> @@ -1146,7 +1217,7 @@ static void guc_engine_kill(struct xe_engine *e)
>>> {
>>> trace_xe_engine_kill(e);
>>> set_engine_killed(e);
>>> - drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT);
>>> + xe_guc_engine_trigger_cleanup(e);
>>> }
>>> static void guc_engine_add_msg(struct xe_engine *e, struct drm_sched_msg *msg,
>>> @@ -1296,6 +1367,9 @@ static void guc_engine_stop(struct xe_guc *guc, struct xe_engine *e)
>>> /* Stop scheduling + flush any DRM scheduler operations */
>>> drm_sched_run_wq_stop(sched);
>>> + if (engine_registered(e) && xe_engine_is_lr(e))
>>> + xe_engine_put(e);
>>> +
>>> /* Clean up lost G2H + reset engine state */
>>> if (engine_destroyed(e) && engine_registered(e)) {
>>> if (engine_banned(e))
>>> @@ -1520,6 +1594,9 @@ int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
>>> trace_xe_engine_deregister_done(e);
>>> clear_engine_registered(e);
>>> + if (xe_engine_is_lr(e))
>>> + xe_engine_put(e);
>>> +
>>> if (engine_banned(e))
>>> xe_engine_put(e);
>>> else
>>> @@ -1557,7 +1634,7 @@ int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len)
>>> */
>>> set_engine_reset(e);
>>> if (!engine_banned(e))
>>> - drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT);
>>> + xe_guc_engine_trigger_cleanup(e);
>>> return 0;
>>> }
>>> @@ -1584,7 +1661,7 @@ int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,
>>> /* Treat the same as engine reset */
>>> set_engine_reset(e);
>>> if (!engine_banned(e))
>>> - drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT);
>>> + xe_guc_engine_trigger_cleanup(e);
>>> return 0;
>>> }
>>> diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
>>> index 2f8eb7ebe9a7..02861c26e145 100644
>>> --- a/drivers/gpu/drm/xe/xe_trace.h
>>> +++ b/drivers/gpu/drm/xe/xe_trace.h
>>> @@ -219,6 +219,11 @@ DEFINE_EVENT(xe_engine, xe_engine_resubmit,
>>> TP_ARGS(e)
>>> );
>>> +DEFINE_EVENT(xe_engine, xe_engine_lr_cleanup,
>>> + TP_PROTO(struct xe_engine *e),
>>> + TP_ARGS(e)
>>> +);
>>> +
>>> DECLARE_EVENT_CLASS(xe_sched_job,
>>> TP_PROTO(struct xe_sched_job *job),
>>> TP_ARGS(job),
next prev parent reply other threads:[~2023-05-09 15:21 UTC|newest]
Thread overview: 126+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-02 0:16 [Intel-xe] [PATCH v2 00/31] Upstreaming prep / all of mbrosts patches Matthew Brost
2023-05-02 0:16 ` [Intel-xe] [PATCH v2 01/31] drm/sched: Add run_wq argument to drm_sched_init Matthew Brost
2023-05-03 12:03 ` Thomas Hellström
2023-05-03 15:06 ` Matthew Brost
2023-05-05 18:24 ` Rodrigo Vivi
2023-05-02 0:16 ` [Intel-xe] [PATCH v2 02/31] drm/sched: Move schedule policy to scheduler Matthew Brost
2023-05-03 12:13 ` Thomas Hellström
2023-05-03 15:11 ` Matthew Brost
2023-05-02 0:16 ` [Intel-xe] [PATCH v2 03/31] drm/sched: Add DRM_SCHED_POLICY_SINGLE_ENTITY scheduling policy Matthew Brost
2023-05-08 12:40 ` Thomas Hellström
2023-05-22 1:16 ` Matthew Brost
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 04/31] drm/xe: Use DRM_SCHED_POLICY_SINGLE_ENTITY mode Matthew Brost
2023-05-08 12:41 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 05/31] drm/xe: Long running job update Matthew Brost
2023-05-05 18:36 ` Rodrigo Vivi
2023-05-08 1:14 ` Matthew Brost
2023-05-08 13:14 ` Thomas Hellström
2023-05-09 14:56 ` Matthew Brost
2023-05-09 15:21 ` Thomas Hellström [this message]
2023-05-09 22:16 ` Matthew Brost
2023-05-10 8:15 ` Thomas Hellström
2023-05-09 22:21 ` Matthew Brost
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 06/31] drm/xe: Ensure LR engines are not persistent Matthew Brost
2023-05-05 18:38 ` Rodrigo Vivi
2023-05-08 1:03 ` Matthew Brost
2023-05-09 12:21 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 07/31] drm/xe: Only try to lock external BOs in VM bind Matthew Brost
2023-05-05 18:40 ` Rodrigo Vivi
2023-05-08 1:08 ` Matthew Brost
2023-05-08 1:15 ` Christopher Snowhill
2023-05-08 21:34 ` Rodrigo Vivi
2023-05-09 12:29 ` Thomas Hellström
2023-05-10 23:25 ` Matthew Brost
2023-05-11 7:43 ` Thomas Hellström
2023-05-08 1:17 ` Christopher Snowhill
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 08/31] drm/xe: VM LRU bulk move Matthew Brost
2023-05-08 21:39 ` Rodrigo Vivi
2023-05-09 22:09 ` Matthew Brost
2023-05-10 1:37 ` Rodrigo Vivi
2023-05-09 12:47 ` Thomas Hellström
2023-05-09 22:05 ` Matthew Brost
2023-05-10 8:14 ` Thomas Hellström
2023-05-10 18:40 ` Matthew Brost
2023-05-11 7:24 ` Thomas Hellström
2023-05-11 14:11 ` Matthew Brost
2023-05-12 9:03 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 09/31] drm/xe/guc: Read HXG fields from DW1 of G2H response Matthew Brost
2023-05-05 18:50 ` Rodrigo Vivi
2023-05-09 12:49 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 10/31] drm/xe/guc: Return the lower part of blocking H2G message Matthew Brost
2023-05-05 18:52 ` Rodrigo Vivi
2023-05-08 1:10 ` Matthew Brost
2023-05-08 9:20 ` Michal Wajdeczko
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 11/31] drm/xe/guc: Use doorbells for submission if possible Matthew Brost
2023-05-08 21:42 ` Rodrigo Vivi
2023-05-10 0:49 ` Matthew Brost
2023-05-09 13:00 ` Thomas Hellström
2023-05-10 0:51 ` Matthew Brost
2023-05-21 12:32 ` Oded Gabbay
2023-06-08 19:30 ` Matthew Brost
2023-06-12 13:01 ` Oded Gabbay
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 12/31] drm/xe/guc: Print doorbell ID in GuC engine debugfs entry Matthew Brost
2023-05-05 18:55 ` Rodrigo Vivi
2023-05-09 13:01 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 13/31] maple_tree: split up MA_STATE() macro Matthew Brost
2023-05-09 13:21 ` Thomas Hellström
2023-05-10 0:29 ` Matthew Brost
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 14/31] maple_tree: Export mas_preallocate Matthew Brost
2023-05-09 13:33 ` Thomas Hellström
2023-05-10 0:31 ` Matthew Brost
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 15/31] drm: manager to keep track of GPUs VA mappings Matthew Brost
2023-05-09 13:49 ` Thomas Hellström
2023-05-10 0:55 ` Matthew Brost
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 16/31] drm/xe: Port Xe to GPUVA Matthew Brost
2023-05-09 13:52 ` Thomas Hellström
2023-05-11 2:41 ` Matthew Brost
2023-05-11 7:39 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 17/31] drm/xe: NULL binding implementation Matthew Brost
2023-05-09 14:34 ` Rodrigo Vivi
2023-05-11 2:52 ` Matthew Brost
2023-05-09 15:17 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 18/31] drm/xe: Avoid doing rebinds Matthew Brost
2023-05-09 14:48 ` Rodrigo Vivi
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 19/31] drm/xe: Reduce the number list links in xe_vma Matthew Brost
2023-05-08 21:43 ` Rodrigo Vivi
2023-05-11 8:38 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 20/31] drm/xe: Optimize size of xe_vma allocation Matthew Brost
2023-05-05 19:37 ` Rodrigo Vivi
2023-05-08 1:21 ` Matthew Brost
2023-05-11 9:05 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 21/31] drm/gpuva: Add drm device to GPUVA manager Matthew Brost
2023-05-05 19:39 ` Rodrigo Vivi
2023-05-11 9:06 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 22/31] drm/gpuva: Move dma-resv " Matthew Brost
2023-05-11 9:10 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 23/31] drm/gpuva: Add support for extobj Matthew Brost
2023-05-11 9:35 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 24/31] drm/xe: Userptr refactor Matthew Brost
2023-05-05 19:41 ` Rodrigo Vivi
2023-05-11 9:46 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 25/31] drm: execution context for GEM buffers v3 Matthew Brost
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 26/31] drm/exec: Always compile drm_exec Matthew Brost
2023-05-09 14:45 ` Rodrigo Vivi
2023-05-10 0:37 ` Matthew Brost
2023-05-10 0:38 ` Matthew Brost
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 27/31] drm/xe: Use drm_exec for locking rather than TTM exec helpers Matthew Brost
2023-05-05 19:42 ` Rodrigo Vivi
2023-05-11 10:01 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 28/31] drm/xe: Allow dma-fences as in-syncs for compute / faulting VM Matthew Brost
2023-05-05 19:43 ` Rodrigo Vivi
2023-05-08 1:19 ` Matthew Brost
2023-05-08 21:29 ` Rodrigo Vivi
2023-05-11 10:03 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 29/31] drm/xe: Allow compute VMs to output dma-fences on binds Matthew Brost
2023-05-09 14:50 ` Rodrigo Vivi
2023-05-11 10:04 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 30/31] drm/xe: remove async worker, sync binds, new error handling Matthew Brost
2023-05-17 16:53 ` Thomas Hellström
2023-05-02 0:17 ` [Intel-xe] [PATCH v2 31/31] drm/xe/uapi: Add some VM bind kernel doc Matthew Brost
2023-05-05 19:45 ` Rodrigo Vivi
2023-05-11 10:14 ` Thomas Hellström
2023-05-02 0:20 ` [Intel-xe] ✗ CI.Patch_applied: failure for Upstreaming prep / all of mbrosts patches (rev2) Patchwork
2023-05-02 1:54 ` Christopher Snowhill (kode54)
2023-05-02 1:59 ` Christopher Snowhill (kode54)
2023-05-03 12:37 ` [Intel-xe] [PATCH v2 00/31] Upstreaming prep / all of mbrosts patches Thomas Hellström
2023-05-03 15:27 ` Matthew Brost
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=df98676a-039b-d159-72c8-559c6ece606a@linux.intel.com \
--to=thomas.hellstrom@linux.intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=matthew.brost@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.