From: "Wachowski, Karol" <karol.wachowski@linux.intel.com>
To: Jeff Hugo <jeff.hugo@oss.qualcomm.com>,
Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>,
dri-devel@lists.freedesktop.org
Cc: oded.gabbay@gmail.com, karol.wachowski@linux.intel.com,
lizhi.hou@amd.com, dawid.osuchowski@linux.intel.com
Subject: Re: [PATCH] accel/ivpu: Drop MTL interrupt clear-with-zero workaround
Date: Mon, 5 Oct 2026 09:08:16 +0200 [thread overview]
Message-ID: <e0f70d42-cc26-43af-b2cc-8044a7ec36e3@linux.intel.com> (raw)
In-Reply-To: <eaa7b598-24be-45c5-9ab4-27bc87085d10@oss.qualcomm.com>
On 02-Oct-26 17:22, Jeff Hugo wrote:
> On 9/30/2026 10:03 AM, Andrzej Kacprowski wrote:
>> Early MTL steppings needed a runtime check for BTRS interrupt status
>> registers that cleared by writing 0 instead of the usual write-1-to-clear
>> flow.
>>
>> Those pre-production steppings are no longer supported. Remove the
>> workaround flag, probe helper, and conditional IRQ clear path, and always
>> clear handled MTL BTRS interrupt status bits by writing the interrupt
>> status value.
>>
>> Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
>
> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
Applied to drm-misc-next.
prev parent reply other threads:[~2026-10-05 7:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 16:03 [PATCH] accel/ivpu: Drop MTL interrupt clear-with-zero workaround Andrzej Kacprowski
2026-10-01 7:44 ` Wachowski, Karol
2026-10-02 15:22 ` Jeff Hugo
2026-10-05 7:08 ` Wachowski, Karol [this message]
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