[PATCH 0/5] dts: update imx95 Libra devicetree for the newest hardware version

[PATCH 0/5] dts: update imx95 Libra devicetree for the newest hardware version

[Benjamin Hahn]

The Libra RDK and i.MX95 FPSC SoM have been updated with new hardware
revisions 1618.2 and 1620.3. With these new hardware revisions they also
got renamed slightly, as they have been integrated in the phyFLEX
series. The baseboard is now named phyFLEX Libra RDK and the SoM is now
named phyFLEX-i.MX 95 FPSC Gamma. Add the new devicetrees and bindings
and remove the old versions. The old versions of the baseboard (1618.0)
and SoM (1620.1) were only ALPHA hardware and are not longer supported
or manufactured, as they were based on the i.MX95 silicon revision A1,
which is no longer available.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
---
Benjamin Hahn (5):
      bindings: Add devicetree bindings for new phyFLEX-i.MX 95 Libra RDK
      dts: imx95-phyflex-libra-rdk: Add dts for phyFLEX-i.MX 95 Libra RDK
      dts: imx95-phyflex-libra-rdk: Add overlays
      dts: imx95-libra-rdk-fpsc: remove devicetree for old Libra
      bindings: remove unused binding from old Libra version

 Documentation/devicetree/bindings/arm/fsl.yaml     |   6 +-
 arch/arm64/boot/dts/freescale/Makefile             |  12 +-
 .../boot/dts/freescale/imx95-libra-rdk-fpsc.dts    | 318 ------------
 .../imx95-phyflex-fpsc-g-som-temperature.dtso      |  23 +
 ...ore-fpsc.dtsi => imx95-phyflex-fpsc-g-som.dtsi} | 204 +++++---
 .../imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso |  24 +
 .../boot/dts/freescale/imx95-phyflex-libra-rdk.dts | 558 +++++++++++++++++++++
 7 files changed, 761 insertions(+), 384 deletions(-)
---
base-commit: df2908090cda368b01ff43709f51890076c56157
change-id: 20260911-wip-bhahn-imx95_upstreaming-99947bb5aea0

Best regards,
--  
Benjamin Hahn <B.Hahn@phytec.de>

[PATCH 1/5] bindings: Add devicetree bindings for new phyFLEX-i.MX 95 Libra RDK

[Benjamin Hahn]

Add devicetree bindings for new phyFLEX-i.MX 95 Libra RDK and
phyFLEX-i.MX 95 FPSC Gamma SoM.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 656f2596e1d5..f917ae7202e9 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1551,6 +1551,13 @@ properties:
           - const: phytec,imx95-phycore-fpsc  # phyCORE-i.MX 95 FPSC
           - const: fsl,imx95
 
+      - description: PHYTEC phyFLEX-i.MX95 FPSC-Gamma SoM based boards
+        items:
+          - enum:
+            - phytec,imx95-phyflex-libra-rdk    # i.MX 95 phyFLEX Libra RDK
+          - const: phytec,imx95-phyflex-fpsc-g  # phyFLEX-i.MX 95 FPSC-Gamma
+          - const: fsl,imx95
+
       - description: Toradex Boards with Aquila iMX95 Modules
         items:
           - enum:

-- 
2.53.0

Re: [PATCH 1/5] bindings: Add devicetree bindings for new phyFLEX-i.MX 95 Libra RDK

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: arm: fsl: wrong enum sequence indentation breaks yamllint
--

commit 46ee5c7fdee02b781beb27b96a47fddb125b6299
Author: Benjamin Hahn <B.Hahn@phytec.de>

bindings: Add devicetree bindings for new phyFLEX-i.MX 95 Libra RDK

This commit adds devicetree bindings for the phyFLEX-i.MX 95 Libra RDK board
and the phyFLEX-i.MX 95 FPSC Gamma SoM to fsl.yaml.

> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 656f2596e1d53..f917ae7202e96 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1551,6 +1551,13 @@ properties:
>            - const: phytec,imx95-phycore-fpsc  # phyCORE-i.MX 95 FPSC
>            - const: fsl,imx95
>  
> +      - description: PHYTEC phyFLEX-i.MX95 FPSC-Gamma SoM based boards
> +        items:
> +          - enum:
> +            - phytec,imx95-phyflex-libra-rdk    # i.MX 95 phyFLEX Libra RDK

[Severity: Low]
In Documentation/devicetree/bindings/arm/fsl.yaml under
properties.compatible, the sequence entry phytec,imx95-phyflex-libra-rdk
under enum is indented with 12 spaces instead of 14 spaces.

Because Documentation/devicetree/bindings/.yamllint configures the
indentation rule with:

  indentation:
    spaces: 2
    indent-sequences: true

does this cause yamllint and make dt_binding_check to fail with an
indentation error?

Should it be indented by two more spaces to match the surrounding compatible
entries:

          - enum:
              - phytec,imx95-phyflex-libra-rdk    # i.MX 95 phyFLEX Libra RDK

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-wip-bhahn-imx95_upstreaming-v1-0-1c1cebb5be99@phytec.de?part=1

Re: [PATCH 1/5] bindings: Add devicetree bindings for new phyFLEX-i.MX 95 Libra RDK

[Krzysztof Kozlowski]

On 30/10/2026 14:32, Benjamin Hahn wrote:
> Add devicetree bindings for new phyFLEX-i.MX 95 Libra RDK and
> phyFLEX-i.MX 95 FPSC Gamma SoM.
> 
> Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>

You hit some combos for subject...


Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters


A nit, subject: drop second/last, redundant "devicetree bindings for".
The "dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst#L23

> ---
>  Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 656f2596e1d5..f917ae7202e9 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1551,6 +1551,13 @@ properties:
>            - const: phytec,imx95-phycore-fpsc  # phyCORE-i.MX 95 FPSC
>            - const: fsl,imx95
>  
> +      - description: PHYTEC phyFLEX-i.MX95 FPSC-Gamma SoM based boards
> +        items:
> +          - enum:
> +            - phytec,imx95-phyflex-libra-rdk    # i.MX 95 phyFLEX Libra RDK

Never tested :/


Best regards,
Krzysztof

[PATCH 2/5] dts: imx95-phyflex-libra-rdk: Add dts for phyFLEX-i.MX 95 Libra RDK

[Benjamin Hahn]

The Libra RDK and i.MX95 FPSC SoM have been updated with new hardware
revisions 1618.2 and 1620.3. With these new hardware revisions they also
got renamed slightly, as they have been integrated in the phyFLEX
series. The baseboard is now named phyFLEX Libra RDK and the SoM is now
named phyFLEX-i.MX 95 FPSC Gamma.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
---
 arch/arm64/boot/dts/freescale/Makefile             |   2 +
 .../dts/freescale/imx95-phyflex-fpsc-g-som.dtsi    | 736 +++++++++++++++++++++
 .../boot/dts/freescale/imx95-phyflex-libra-rdk.dts | 558 ++++++++++++++++
 3 files changed, 1296 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 95ae85ab4adf..4eb7508193e7 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -739,6 +739,8 @@ imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo
 dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb
 
+dtb-$(CONFIG_ARCH_MXC) += imx95-phyflex-libra-rdk.dtb
+
 dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-verdin-evk.dtb
 
 dtb-$(CONFIG_ARCH_MXC) += imx952-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som.dtsi b/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som.dtsi
new file mode 100644
index 000000000000..4b37d76cced1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som.dtsi
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 PHYTEC Messtechnik GmbH
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "imx95.dtsi"
+
+/ {
+	model = "PHYTEC phyFLEX-i.MX95 FPSC";
+	compatible = "phytec,imx95-phyflex-fpsc-g", "fsl,imx95";
+
+	aliases {
+		/* FPSC alias definitions */
+		ethernet1 = &enetc_port1;
+		ethernet2 = &enetc_port0;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		i2c1 = &lpi2c2;
+		i2c2 = &lpi2c5;
+		i2c3 = &lpi2c3;
+		i2c4 = &lpi2c4;
+		i2c5 = &lpi2c1;
+		pcie1 = &pcie0;
+		pcie2 = &pcie1;
+		pwm1 = &tpm3;
+		pwm2 = &tpm5;
+		sai1 = &sai5;
+		serial1 = &lpuart8;
+		serial2 = &lpuart5;
+		serial3 = &lpuart7;
+		spi1 = &lpspi7;
+		spi2 = &lpspi3;
+		spi3 = &lpspi4;
+		usb1 = &usb3;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0x00000002 0x00000000>;
+	};
+
+	reg_nvcc_aon: regulator-nvcc-aon {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "VDD_IO";
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		off-on-delay-us = <12000>;
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		pinctrl-names = "default";
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VDDSW_SD2";
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		bootph-pre-ram;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x00000000 0x90200000 0x00000000 0x6fe00000>;
+			reusable;
+			size = <0x00000000 0x3c000000>;
+			linux,cma-default;
+		};
+	};
+};
+
+&enetc_port0 { /* FPSC RGMII2 */
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&pinctrl_enetc0>;
+	pinctrl-names = "default";
+};
+
+&enetc_port1 {
+	phy-handle = <&ethphy1>;
+	phy-mode = "rgmii-id";
+	pinctrl-0 = <&pinctrl_enetc1>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&flexcan1 { /* FPSC CAN1 */
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	pinctrl-names = "default";
+};
+
+&flexcan2 { /* FPSC CAN2 */
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	pinctrl-names = "default";
+};
+
+&flexspi1 { /* FPSC QSPI */
+	pinctrl-0 = <&pinctrl_flexspi>;
+	pinctrl-names = "default";
+};
+
+&gpio1 { /* FPSC GPIO */
+	gpio-line-names = "", "", "", "",
+			  "GPIO2", "GPIO1", "", "",
+			  "", "", "PCIE1_nPERST", "USB1_PWR_EN",
+			  "GPIO3", "USB2_PWR_EN", "PCIE2_nPERST";
+	pinctrl-0 = <&pinctrl_gpio1>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio2 { /* FPSC GPIO */
+	gpio-line-names = "", "", "", "", "",
+			  "", "", "", "", "",
+			  "", "", "", "", "",
+			  "", "RGMII2_nINT", "GPIO4";
+	pinctrl-0 = <&pinctrl_gpio2>;
+	pinctrl-names = "default";
+};
+
+&gpio3 {
+	gpio-line-names = "", "", "", "", "",
+			  "", "", "SD2_RESET_B";
+};
+
+&gpio4 {
+	gpio-line-names = "ENET2_nINT";
+};
+
+&gpio5 {
+	gpio-line-names = "", "", "", "", "",
+			  "", "", "", "", "",
+			  "", "", "", "USB1_OC", "USB2_OC";
+};
+
+&lpi2c1 { /* FPSC I2C5 */
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	pinctrl-names = "default";
+	bootph-all;
+	status = "okay";
+
+	dram_sense: temperature-sensor@48 {
+		compatible = "ti,tmp102";
+		reg = <0x48>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
+	emmc_sense: temperature-sensor@49 {
+		compatible = "ti,tmp102";
+		reg = <0x49>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
+	ethphy_sense: temperature-sensor@4a {
+		compatible = "ti,tmp102";
+		reg = <0x4a>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
+	pmic_sense: temperature-sensor@4b {
+		compatible = "ti,tmp102";
+		reg = <0x4b>;
+		#thermal-sensor-cells = <1>;
+		status = "disabled";
+	};
+
+	/* User EEPROM */
+	eeprom@50 {
+		compatible = "atmel,24c32";
+		reg = <0x50>;
+		pagesize = <32>;
+		vcc-supply = <&reg_nvcc_aon>;
+	};
+
+	/* Factory EEPROM */
+	eeprom@51 {
+		compatible = "atmel,24c32";
+		reg = <0x51>;
+		pagesize = <32>;
+		read-only;
+		vcc-supply = <&reg_nvcc_aon>;
+	};
+
+	rv3028: rtc@52 {
+		compatible = "microcrystal,rv3028";
+		reg = <0x52>;
+		#clock-cells = <0>;
+		trickle-resistor-ohms = <3000>;
+	};
+
+	/* User EEPROM ID page */
+	eeprom@58 {
+		compatible = "atmel,24c32";
+		reg = <0x58>;
+		pagesize = <32>;
+		vcc-supply = <&reg_nvcc_aon>;
+	};
+};
+
+&lpi2c2 { /* FPSC I2C1 */
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	pinctrl-names = "default";
+};
+
+&lpi2c3 { /* FPSC I2C3 */
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-names = "default";
+};
+
+&lpi2c4 { /* FPSC I2C4 */
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c4>;
+	pinctrl-names = "default";
+};
+
+&lpi2c5 { /* FPSC I2C2 */
+	clock-frequency = <400000>;
+	pinctrl-0 = <&pinctrl_lpi2c5>;
+	pinctrl-names = "default";
+};
+
+&lpspi3 { /* FPSC SPI2 */
+	pinctrl-0 = <&pinctrl_lpspi3>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
+
+&lpspi4 { /* FPSC SPI3 */
+	pinctrl-0 = <&pinctrl_lpspi4>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
+};
+
+&lpspi7 { /* FPSC SPI1 */
+	pinctrl-0 = <&pinctrl_lpspi7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+};
+
+&lpuart5 { /* FPSC UART2 */
+	pinctrl-0 = <&pinctrl_lpuart5>;
+	pinctrl-names = "default";
+};
+
+&lpuart7 { /* FPSC UART3 */
+	pinctrl-0 = <&pinctrl_lpuart7>;
+	pinctrl-names = "default";
+	bootph-all;
+};
+
+&lpuart8 { /* FPSC UART1 */
+	pinctrl-0 = <&pinctrl_lpuart8>;
+	pinctrl-names = "default";
+};
+
+&netc_blk_ctrl {
+	status = "okay";
+};
+
+&netc_emdio { /* FPSC RGMII2 */
+	pinctrl-0 = <&pinctrl_emdio>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ethphy1: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+		enet-phy-lane-no-swap;
+		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+	};
+};
+
+&netcmix_blk_ctrl {
+	status = "okay";
+};
+
+&pcie0 { /* FPSC PCIE1 */
+	pinctrl-0 = <&pinctrl_pcie0>;
+	pinctrl-names = "default";
+};
+
+&pcie1 { /* FPSC PCIE2 */
+	pinctrl-0 = <&pinctrl_pcie1>;
+	pinctrl-names = "default";
+};
+
+&sai5 { /* FPSC SAI1 */
+	pinctrl-0 = <&pinctrl_sai5>;
+	pinctrl-names = "default";
+};
+
+&scmi_iomuxc {
+	pinctrl_emdio: emdiogrp {
+		fsl,pins = <
+			IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO	0x97e	/* RGMII2_MDIO */
+			IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC	0x502	/* RGMII2_MDC */
+		>;
+	};
+
+	pinctrl_enetc0: enetc0grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16			0x31e	/* RGMII2_nINT */
+			IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2	0x31e	/* RGMII2_EVENT_IN */
+			IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2	0x31e	/* RGMII2_EVENT_OUT */
+
+			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x51e	/* RGMII2_TX_3 */
+			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x51e	/* RGMII2_TX_2 */
+			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x51e	/* RGMII2_TX_1 */
+			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x51e	/* RGMII2_TX_0 */
+			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x51e	/* RGMII2_TX_CTL */
+			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e	/* RGMII2_TXC */
+			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e	/* RGMII2_RX_3 */
+			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e	/* RGMII2_RX_2 */
+			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e	/* RGMII2_RX_1 */
+			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e	/* RGMII2_RX_0 */
+			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e	/* RGMII2_RX_CTL */
+			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e	/* RGMII2_RXC */
+		>;
+	};
+
+	pinctrl_enetc1: enetc1grp {
+		fsl,pins = <
+			IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0			0x31e
+			IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x57e
+			IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x57e
+			IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x51e
+			IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x51e
+			IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e
+			IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK	0x58e
+			IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e
+			IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e
+			IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e
+			IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e
+			IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e
+			IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK	0x58e
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX		0x51e	/* CAN1_TX */
+			IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX	0x51e	/* CAN1_RX */
+		>;
+	};
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO25__CAN2_TX	0x51e	/* CAN2_TX */
+			IMX95_PAD_GPIO_IO27__CAN2_RX	0x51e	/* CAN2_RX */
+		>;
+	};
+
+	pinctrl_flexspi: flexspigrp {
+		fsl,pins = <
+			IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B		0x39e	/* QSPI_CE */
+			IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK		0x39e	/* QSPI_CLK */
+			IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0	0x39e	/* QSPI_DATA_0 */
+			IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1	0x39e	/* QSPI_DATA_1 */
+			IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2	0x39e	/* QSPI_DATA_2 */
+			IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3	0x39e	/* QSPI_DATA_3 */
+		>;
+	};
+
+	pinctrl_gpio1: gpio1grp {
+		fsl,pins = <
+			IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5	0x31e	/* GPIO1 */
+			IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4	0x31e	/* GPIO2 */
+			IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12	0x31e	/* GPIO3 */
+		>;
+	};
+
+	pinctrl_gpio2: gpio2grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17	0x31e	/* GPIO4 */
+		>;
+	};
+
+	pinctrl_lpi2c1: lpi2c1grp {
+		fsl,pins = <
+			IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL	0x40000b9e	/* I2C5_SCL */
+			IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA	0x40000b9e	/* I2C5_SDA */
+		>;
+		bootph-all;
+	};
+
+	pinctrl_lpi2c2: lpi2c2grp {
+		fsl,pins = <
+			IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA	0x40000b9e	/* I2C1_SDA_DNU */
+			IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL	0x40000b9e	/* I2C1_SCL_DNU */
+		>;
+	};
+
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e	/* I2C3_SDA */
+			IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e	/* I2C3_SCL */
+		>;
+	};
+
+	pinctrl_lpi2c4: lpi2c4grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e	/* I2C4_SDA */
+			IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e	/* I2C4_SDL */
+		>;
+	};
+
+	pinctrl_lpi2c5: lpi2c5grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO22__LPI2C5_SDA	0x40000b9e	/* I2C2_SDA */
+			IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e	/* I2C2_SCL */
+		>;
+	};
+
+	/* lpspi driver only works with cs-gpios currently, thus mux
+	 * to gpio instead of native controller cs signal. To compensate,
+	 * cs-gpios is defined as active low in this file.
+	 */
+	pinctrl_lpspi3: lpspi3grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO11__LPSPI3_SCK		0x3fe	/* SPI2_SCLK */
+			IMX95_PAD_GPIO_IO10__LPSPI3_SOUT	0x3fe	/* SPI2_MOSI */
+			IMX95_PAD_GPIO_IO09__LPSPI3_SIN		0x3fe	/* SPI2_MISO */
+			IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8	0x3fe	/* SPI2_CS */
+		>;
+	};
+
+	pinctrl_lpspi4: lpspi4grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO21__LPSPI4_SCK		0x3fe	/* SPI3_SCLK */
+			IMX95_PAD_GPIO_IO20__LPSPI4_SOUT	0x3fe	/* SPI3_MOSI */
+			IMX95_PAD_GPIO_IO19__LPSPI4_SIN		0x3fe	/* SPI3_MISO */
+			IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18	0x3fe	/* SPI3_CS */
+		>;
+	};
+
+	pinctrl_lpspi7: lpspi7grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO07__LPSPI7_SCK		0x3fe	/* SPI1_SCLK */
+			IMX95_PAD_GPIO_IO06__LPSPI7_SOUT	0x3fe	/* SPI1_MOSI */
+			IMX95_PAD_GPIO_IO05__LPSPI7_SIN		0x3fe	/* SPI1_MISO */
+			IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4	0x3fe	/* SPI1_CS */
+		>;
+	};
+
+	pinctrl_lpuart5: lpuart5grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO01__LPUART5_RX		0x51e	/* UART2_RXD */
+			IMX95_PAD_GPIO_IO00__LPUART5_TX		0x51e	/* UART2_TXD */
+			IMX95_PAD_GPIO_IO03__LPUART5_RTS_B	0x51e	/* UART2_RTS */
+			IMX95_PAD_GPIO_IO02__LPUART5_CTS_B	0x51e	/* UART2_CTS */
+		>;
+	};
+
+	pinctrl_lpuart7: lpuart7grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO37__LPUART7_RX	0x31e	/* UART3_RXD */
+			IMX95_PAD_GPIO_IO36__LPUART7_TX	0x31e	/* UART3_TXD */
+		>;
+		bootph-all;
+	};
+
+	pinctrl_lpuart8: lpuart8grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO13__LPUART8_RX		0x51e	/* UART1_RXD */
+			IMX95_PAD_GPIO_IO12__LPUART8_TX		0x51e	/* UART1_TXD */
+			IMX95_PAD_GPIO_IO15__LPUART8_RTS_B	0x51e	/* UART1_RTS */
+			IMX95_PAD_GPIO_IO14__LPUART8_CTS_B	0x51e	/* UART1_CTS */
+		>;
+	};
+
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B		0x31e	/* PCIE1_nCLKREQ */
+			IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10	0x31e	/* PCIE1_nPERST */
+		>;
+	};
+
+	pinctrl_pcie1: pcie1grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x31e	/* PCIE2_nCLKREQ */
+			IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14	0x31e	/* PCIE2_nPERST */
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7	0x31e
+		>;
+		bootph-all;
+	};
+
+	pinctrl_sai5: sai5grp {
+		fsl,pins = <
+			IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC		0x51e	/* SAI1_RX_SYNC */
+			IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK		0x51e	/* SAI1_RX_BCLK */
+			IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0	0x51e	/* SAI1_RX_DATA */
+			IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC		0x51e	/* SAI1_TX_SYNC */
+			IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK		0x51e	/* SAI1_TX_BCLK */
+			IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0	0x51e	/* SAI1_TX_DATA */
+		>;
+	};
+
+	pinctrl_tpm3: tpm3grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO24__TPM3_CH3	0x51e	/* PWM1 */
+		>;
+	};
+
+	pinctrl_tpm5: tpm5grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO26__TPM5_CH3	0x51e	/* PWM2 */
+		>;
+	};
+
+	pinctrl_usbc: usbcgrp {
+		fsl,pins = <
+			IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11	0x51e	/* USB1_PWR_EN */
+			IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13		0x51e	/* USB1_OC */
+		>;
+	};
+
+	pinctrl_usb2: usb2grp {
+		fsl,pins = <
+			IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13	0x51e	/* USB2_PWR_EN */
+			IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14		0x51e	/* USB2_OC */
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e
+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e
+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e
+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e
+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e
+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e
+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e
+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e
+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e
+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e
+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e
+		>;
+		bootph-pre-ram;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e
+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e
+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e
+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e
+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e
+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e
+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e
+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e
+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e
+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e
+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e
+		>;
+		bootph-pre-ram;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x13fe
+			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x13fe
+			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x13fe
+			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x13fe
+			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x13fe
+			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x13fe
+			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x13fe
+			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x13fe
+			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe
+			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe
+			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x15fe
+		>;
+		bootph-pre-ram;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */
+			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */
+			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */
+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */
+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */
+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */
+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */
+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+
+		>;
+		bootph-all;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */
+			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */
+			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */
+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */
+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */
+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */
+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */
+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+		bootph-all;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */
+			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */
+			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */
+			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */
+			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */
+			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */
+			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */
+			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
+		>;
+		bootph-all;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x159e	/* SDIO_CLK */
+			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x139e	/* SDIO_CMD */
+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x139e	/* SDIO_DATA0 */
+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x139e	/* SDIO_DATA1 */
+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x139e	/* SDIO_DATA2 */
+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x139e	/* SDIO_DATA3 */
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x159e	/* SDIO_CLK */
+			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x139e	/* SDIO_CMD */
+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x139e	/* SDIO_DATA0 */
+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x139e	/* SDIO_DATA1 */
+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x139e	/* SDIO_DATA2 */
+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x139e	/* SDIO_DATA3 */
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x159e	/* SDIO_CLK */
+			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x139e	/* SDIO_CMD */
+			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x139e	/* SDIO_DATA0 */
+			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x139e	/* SDIO_DATA1 */
+			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x139e	/* SDIO_DATA2 */
+			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x139e	/* SDIO_DATA3 */
+		>;
+	};
+};
+
+&tpm3 { /* FPSC PWM1 */
+	pinctrl-0 = <&pinctrl_tpm3>;
+	pinctrl-names = "default";
+};
+
+&tpm5 { /* FPSC PWM2 */
+	pinctrl-0 = <&pinctrl_tpm5>;
+	pinctrl-names = "default";
+};
+
+&usb3 { /* FPSC USB1 */
+	pinctrl-0 = <&pinctrl_usbc>;
+	pinctrl-names = "default";
+};
+
+&usdhc1 {
+	bus-width = <8>;
+	mmc-hs400-1_8v;
+	non-removable;
+	no-sd;
+	no-sdio;
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc1>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	bootph-pre-ram;
+	status = "okay";
+};
+
+&usdhc2 { /* FPSC SDCARD */
+	bus-width = <4>;
+	disable-wp;
+	no-mmc-hs400;
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc2>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	sd-uhs-sdr104;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bootph-pre-ram;
+};
+
+&usdhc3 { /* FPSC SDIO */
+	bus-width = <4>;
+	no-mmc-hs400;
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc3>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+};
+
+&wdog3 {
+	fsl,ext-reset-output;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk.dts b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk.dts
new file mode 100644
index 000000000000..55d49f810956
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk.dts
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 PHYTEC Messtechnik GmbH
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+
+#include "imx95-phyflex-fpsc-g-som.dtsi"
+
+/ {
+	compatible = "phytec,imx95-phyflex-libra-rdk",
+		     "phytec,imx95-phyflex-fpsc-g", "fsl,imx95";
+	model = "PHYTEC Libra phyFLEX-i.MX95 FPSC";
+
+	aliases {
+		ethernet3 = &enetc_port2;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		rtc0 = &rv3028;
+		rtc1 = &scmi_bbm;
+	};
+
+	chosen {
+		stdout-path = &lpuart7;
+	};
+
+	can_transceiver1: can-phy1 {
+		compatible = "ti,tcan1043";
+		#phy-cells = <0>;
+		max-bitrate = <8000000>;
+		standby-gpios = <&gpio_expander2 0 GPIO_ACTIVE_HIGH>;
+	};
+
+	can_transceiver2: can-phy2 {
+		compatible = "ti,tcan1043";
+		#phy-cells = <0>;
+		max-bitrate = <8000000>;
+		standby-gpios = <&gpio_expander2 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	connector {
+		compatible = "usb-c-connector";
+		label = "USB-C";
+		data-role = "dual";
+		pd-disable;
+		self-powered;
+		typec-power-opmode = "1.5A";
+		vbus-supply = <&reg_vdd_vbus>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				hs_ep: endpoint {
+					remote-endpoint = <&usb3_hs_ep>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+
+				ss_ep: endpoint {
+					remote-endpoint = <&hd3ss3220_in_ep>;
+				};
+			};
+		};
+	};
+
+	m2-key-m-connector {
+		compatible = "pcie-m2-m-connector";
+		clocks = <&rv3028>;
+		i2c-parent = <&lpi2c5>;
+		vpcie3v3-supply = <&reg_vdd_3v3>;
+	};
+
+	m2-key-e-connector {
+		compatible = "pcie-m2-e-connector";
+		clocks = <&rv3028>;
+		i2c-parent = <&lpi2c3>;
+		sdio-reset-gpios = <&gpio_expander2 6 GPIO_ACTIVE_LOW>;
+		sdio-wake-gpios = <&gpio_expander2 5 GPIO_ACTIVE_LOW>;
+		uart-wake-gpios = <&gpio_expander1 13 GPIO_ACTIVE_LOW>;
+		vpcie3v3-supply = <&reg_vdd_3v3>;
+		w-disable1-gpios = <&gpio_expander1 9 GPIO_ACTIVE_LOW>;
+		w-disable2-gpios = <&gpio_expander1 10 GPIO_ACTIVE_LOW>;
+	};
+
+
+	osc_mclk: oscillator-mclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <19200000>;
+		status = "disabled";
+	};
+
+	osc_mclk_gated: oscillator-mclk-gated {
+		compatible = "gpio-gate-clock";
+		#clock-cells = <0>;
+		clocks = <&osc_mclk>;
+		enable-gpios = <&gpio_expander1 8 GPIO_ACTIVE_HIGH>;
+		status = "disabled";
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		interrupt-parent = <&gpio1>;
+		interrupts = <4 IRQ_TYPE_EDGE_RISING>;
+		#cooling-cells = <2>;
+		/* startup 35%, duty cycle 30%-100%;
+		 * polarity inversion does not appear to work
+		 */
+		cooling-levels = <255 166 96 0>;
+		/* fan-supply = <&reg_vdd_5v0>;  probe fails with this set */
+		pwms = <&tpm5 3 86958 0>;
+		pulses-per-revolution = <2>;
+	};
+
+	reg_vdd_12v0: regulator-vdd-12v0 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <12000000>;
+		regulator-min-microvolt = <12000000>;
+		regulator-name = "VDD_12V0";
+	};
+
+	reg_vdd_1v8: regulator-vdd-1v8 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "VDD_1V8";
+	};
+
+	reg_vdd_3v3: regulator-vdd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "VDD_3V3";
+	};
+
+	reg_vdd_5v0: regulator-vdd-5v0 {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "VDD_5V0";
+	};
+
+	reg_vdd_5v0_ref: regulator-vdd-5v0-ref {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-max-microvolt = <5000000>;
+		regulator-min-microvolt = <5000000>;
+		regulator-name = "VDD_5V0_REF";
+	};
+
+	reg_vdd_vbus: regulator-vdd-vbus {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "VDD_VBUS_C";
+	};
+
+	reg_usb3_phy: regulator-usb-vbus {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "usb3-phy-dummy";
+	};
+};
+
+&enetc_port0 {
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+/* CAN FD */
+&flexcan1 {
+	phys = <&can_transceiver1>;
+	status = "okay";
+};
+
+&flexcan2 {
+	phys = <&can_transceiver2>;
+	status = "okay";
+};
+
+/* SPI-NOR */
+&flexspi1 {
+	pinctrl-0 = <&pinctrl_flexspi>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	spi_nor: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <166000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		vcc-supply = <&reg_vdd_1v8>;
+	};
+};
+
+&gpio2 {
+	gpio-line-names = "", "", "", "", "",
+			  "", "", "", "", "",
+			  "", "", "", "", "",
+			  "", "RGMII2_nINT", "GPIO4", "RTC_INT", "",
+			  "LVDS1_BL_EN";
+};
+
+&lpi2c1 {
+	temperature-sensor@4f {
+		compatible = "nxp,p3t1755";
+		reg = <0x4f>;
+		vs-supply = <&reg_vdd_1v8>;
+	};
+};
+
+&lpi2c3 {
+	status = "okay";
+
+	gpio_expander2: gpio@21 {
+		compatible = "ti,tcal6416";
+		reg = <0x21>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+		#interrupt-cells = <2>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "CAN1_STBY", "CAN2_STBY", "NC",
+				  "KEY-E_nALERT", "KEY-M_nALERT",
+				  "SDIO_nWAKE", "SDIO_nRESET", "HDMI_EN",
+				  "RTC_nINT", "LVDS1_BL_EN", "SFP_TX_FAULT",
+				  "SFP_TX_DISABLE", "SFP_MOD_ABS", "SFP_RS0",
+				  "SFP_RX_LOSS", "SFP_RS1";
+		interrupt-controller;
+		vcc-supply = <&reg_vdd_1v8>;
+	};
+
+	led-controller@62 {
+		compatible = "nxp,pca9633";
+		reg = <0x62>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		led@0 {
+			reg = <0>;
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led@1 {
+			reg = <1>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+		};
+
+		led@2 {
+			reg = <2>;
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+		};
+	};
+
+	usb-typec@47 {
+		compatible = "ti,hd3ss3220";
+		reg = <0x47>;
+		interrupt-parent = <&gpio_expander1>;
+		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				hd3ss3220_in_ep: endpoint {
+					remote-endpoint = <&ss_ep>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				hd3ss3220_out_ep: endpoint {
+					remote-endpoint = <&usb3_role_switch>;
+				};
+			};
+		};
+	};
+};
+
+&lpi2c5 {
+	status = "okay";
+
+	gpio_expander1: gpio@21 {
+		compatible = "ti,tcal6416";
+		reg = <0x21>;
+		interrupt-controller;
+		interrupt-parent = <&gpio1>;
+		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+		#interrupt-cells = <2>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-line-names = "VCONN_nFAULT", "CSI1_CTRL1", "CSI1_CTRL3",
+				  "CSI1_CTRL4", "USB-C_nINT/AUDIO_AC",
+				  "CSI2_CTRL1", "CSI2_CTRL3", "CSI2_CTRL4",
+				  "CLK_EN_AV", "W_nDISABLE1", "W_nDISABLE2",
+				  "PCIE1_nWAKE", "PCIE2_nWAKE", "UART1_nWAKE",
+				  "UART1_BT_RS_SEL", "UART1_RS232_485_SEL";
+
+		vcc-supply = <&reg_vdd_1v8>;
+	};
+
+	/* Factory EEPROM */
+	eeprom@51 {
+		compatible = "atmel,24c02";
+		reg = <0x51>;
+		pagesize = <16>;
+		vcc-supply = <&reg_vdd_1v8>;
+	};
+
+	/* User EEPROM */
+	eeprom@52 {
+		compatible = "atmel,24c02";
+		reg = <0x52>;
+		pagesize = <16>;
+		vcc-supply = <&reg_vdd_1v8>;
+	};
+};
+
+&lpspi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	num-cs = <1>;
+	assigned-clocks = <&scmi_clk IMX95_CLK_LPSPI3>;
+	assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD0_DIV2>;
+	assigned-clock-rates = <50000000>;
+	status = "okay";
+
+	tpm: tpm@0 {
+		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+		reg = <0>;
+		spi-max-frequency = <22500000>;
+	};
+};
+
+&lpspi7 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	num-cs = <1>;
+	status = "okay";
+
+	adc@0 {
+		compatible = "microchip,mcp3208";
+		reg = <0>;
+		spi-max-frequency = <2000000>;
+		vref-supply = <&reg_vdd_5v0_ref>;
+		#io-channel-cells = <1>;
+	};
+};
+
+/* Used for M33 debug */
+&lpuart2 {
+	pinctrl-0 = <&pinctrl_lpuart2>;
+	pinctrl-names = "default";
+	status = "reserved";
+};
+
+/* A-55 debug UART */
+&lpuart7 {
+	status = "okay";
+};
+
+/* RS232/RS485/BT */
+&lpuart8 {
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&netc_emdio { /* RGMII2 */
+	ethphy0: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+		enet-phy-lane-no-swap;
+		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+	};
+};
+
+/* M.2 Key-E PCIe */
+&pcie0 {
+	external-facing;
+	supports-clkreq;
+	wake-gpios = <&gpio_expander1 11 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie0_port0 {
+	reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+	vpcie3v3-supply = <&reg_vdd_3v3>;
+};
+
+/* M.2 Key-M PCIe */
+&pcie1 {
+	external-facing;
+	supports-clkreq;
+	wake-gpios = <&gpio_expander1 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pcie1_port0 {
+	reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+	vpcie3v3-supply = <&reg_vdd_3v3>;
+};
+
+&rv3028 {
+	interrupt-parent = <&gpio_expander2>;
+	interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+	aux-voltage-chargeable = <1>;
+	wakeup-source;
+};
+
+&scmi_bbm {
+	linux,code = <KEY_POWER>;
+};
+
+&scmi_iomuxc {
+	pinctrl_lpuart2: lpuart2grp { /* FPSC proprietary */
+		fsl,pins = <
+			IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX	0x31e
+			IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX	0x31e
+		>;
+	};
+};
+
+&thermal_zones {
+	a55-thermal {
+		trips {
+			atrip2: trip2 {
+				temperature = <55000>;
+				hysteresis = <2000>;
+				type = "active";
+			};
+
+			atrip3: trip3 {
+				temperature = <65000>;
+				hysteresis = <2000>;
+				type = "active";
+			};
+
+			atrip4: trip4 {
+				temperature = <75000>;
+				hysteresis = <2000>;
+				type = "active";
+			};
+		};
+
+		cooling-maps {
+			map1 {
+				trip = <&atrip2>;
+				cooling-device = <&fan 0 1>;
+			};
+
+			map2 {
+				trip = <&atrip3>;
+				cooling-device = <&fan 1 2>;
+			};
+
+			map3 {
+				trip = <&atrip4>;
+				cooling-device = <&fan 2 3>;
+			};
+		};
+	};
+};
+
+&tpm5 {
+	status = "okay";
+};
+
+&usb2 {
+	disable-over-current;
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+&usb3_dwc3 {
+	adp-disable;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	usb-role-switch;
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			usb3_hs_ep: endpoint {
+				remote-endpoint = <&hs_ep>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			usb3_role_switch: endpoint {
+				remote-endpoint = <&hd3ss3220_out_ep>;
+			};
+		};
+	};
+};
+
+&usb3_phy {
+	status = "okay";
+	vbus-supply = <&reg_usb3_phy>;
+};
+
+&usbphynop {
+	vbus-supply = <&reg_vdd_5v0>;
+};
+
+/* uSD Card */
+&usdhc2 {
+	status = "okay";
+};
+
+/* SDIO used on pcie m.2 key-E */
+&usdhc3 {
+	broken-cd;
+	disable-wp;
+	status = "okay";
+};

-- 
2.53.0

Re: [PATCH 2/5] dts: imx95-phyflex-libra-rdk: Add dts for phyFLEX-i.MX 95 Libra RDK

[Krzysztof Kozlowski]

On 30/10/2026 14:32, Benjamin Hahn wrote:
> The Libra RDK and i.MX95 FPSC SoM have been updated with new hardware
> revisions 1618.2 and 1620.3. With these new hardware revisions they also
> got renamed slightly, as they have been integrated in the phyFLEX
> series. The baseboard is now named phyFLEX Libra RDK and the SoM is now
> named phyFLEX-i.MX 95 FPSC Gamma.
> 
> Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
> ---

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters

Best regards,
Krzysztof

Re: [PATCH 2/5] dts: imx95-phyflex-libra-rdk: Add dts for phyFLEX-i.MX 95 Libra RDK

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] arm64: dts: freescale: duplicate usdhc2-200mhzgrp node overwrites usdhc2 pins
- [High] arm64: dts: freescale: missing OF graph ports on M.2 connectors disables radios
- [High] arm64: dts: freescale: descending cooling-levels ending in 0 breaks pwm-fan
- [Medium] arm64: dts: freescale: misplaced external-facing and wake-gpios on pcie0/pcie1
- [Medium] arm64: dts: freescale: stale gpio2 gpio-line-names collide with gpio_expander2
--

commit 01cb871eca78a3c506a85dce8f3e949939c4a0cb
Author: Benjamin Hahn <B.Hahn@phytec.de>

dts: imx95-phyflex-libra-rdk: Add dts for phyFLEX-i.MX 95 Libra RDK

This commit adds the device tree source files for the PHYTEC phyFLEX Libra
RDK baseboard (revision 1618.2) and phyFLEX-i.MX 95 FPSC Gamma SoM (revision
1620.3).

> diff --git a/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som.dtsi b/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som.dtsi
> new file mode 100644
> index 0000000000000..4b37d76cced1b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som.dtsi
> @@ -0,0 +1,736 @@

[ ... ]

> +&scmi_iomuxc {

[ ... ]

> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> +		fsl,pins = <
> +			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */
> +			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */
> +			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */
> +			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */
> +			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */
> +			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */
> +			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */
> +			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
> +		>;
> +		bootph-all;
> +	};
> +
> +	pinctrl_usdhc3: usdhc3grp {
> +		fsl,pins = <
> +			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x159e	/* SDIO_CLK */
> +			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x139e	/* SDIO_CMD */
> +			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x139e	/* SDIO_DATA0 */
> +			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x139e	/* SDIO_DATA1 */
> +			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x139e	/* SDIO_DATA2 */
> +			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x139e	/* SDIO_DATA3 */
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> +		fsl,pins = <
> +			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x159e	/* SDIO_CLK */
> +			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x139e	/* SDIO_CMD */
> +			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x139e	/* SDIO_DATA0 */
> +			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x139e	/* SDIO_DATA1 */
> +			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x139e	/* SDIO_DATA2 */
> +			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x139e	/* SDIO_DATA3 */
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_200mhz: usdhc2-200mhzgrp {
> +		fsl,pins = <
> +			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x159e	/* SDIO_CLK */
> +			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x139e	/* SDIO_CMD */
> +			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x139e	/* SDIO_DATA0 */
> +			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x139e	/* SDIO_DATA1 */
> +			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x139e	/* SDIO_DATA2 */
> +			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x139e	/* SDIO_DATA3 */
> +		>;
> +	};

[Severity: High]
Should pinctrl_usdhc3_200mhz be named usdhc3-200mhzgrp instead of
usdhc2-200mhzgrp?

Because both pinctrl_usdhc2_200mhz and pinctrl_usdhc3_200mhz use the node
name usdhc2-200mhzgrp under &scmi_iomuxc, dtc merges them into a single
node and overwrites the SD2 fsl,pins array in pinctrl_usdhc2_200mhz with
the SD3 pins from pinctrl_usdhc3_200mhz.

When usdhc2 (which has sd-uhs-sdr104 enabled) switches to its state_200mhz
pinctrl state, it will attempt to claim the SD3 pads instead of configuring
the SD2 pads, breaking 200MHz SD card operation and conflicting with usdhc3.

Also, both pinctrl_usdhc2_200mhz and pinctrl_usdhc3_200mhz appear to use
100MHz pad settings (0x158e/0x138e and 0x159e/0x139e) rather than 200MHz
slew rate settings (such as 0x15fe/0x13fe used in pinctrl_usdhc1_200mhz).

> diff --git a/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk.dts b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk.dts
> new file mode 100644
> index 0000000000000..55d49f8109567
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk.dts
> @@ -0,0 +1,558 @@

[ ... ]

> +	m2-key-m-connector {
> +		compatible = "pcie-m2-m-connector";
> +		clocks = <&rv3028>;
> +		i2c-parent = <&lpi2c5>;
> +		vpcie3v3-supply = <&reg_vdd_3v3>;
> +	};
> +
> +	m2-key-e-connector {
> +		compatible = "pcie-m2-e-connector";
> +		clocks = <&rv3028>;
> +		i2c-parent = <&lpi2c3>;
> +		sdio-reset-gpios = <&gpio_expander2 6 GPIO_ACTIVE_LOW>;
> +		sdio-wake-gpios = <&gpio_expander2 5 GPIO_ACTIVE_LOW>;
> +		uart-wake-gpios = <&gpio_expander1 13 GPIO_ACTIVE_LOW>;
> +		vpcie3v3-supply = <&reg_vdd_3v3>;
> +		w-disable1-gpios = <&gpio_expander1 9 GPIO_ACTIVE_LOW>;
> +		w-disable2-gpios = <&gpio_expander1 10 GPIO_ACTIVE_LOW>;
> +	};

[Severity: High]
Are the OF graph ports missing from m2-key-m-connector and
m2-key-e-connector?

When pwrseq_pcie_m2_probe() in drivers/power/sequencing/pwrseq-pcie-m2.c
probes m2-key-e-connector, it requests w-disable1-gpios and w-disable2-gpios
with GPIOD_OUT_HIGH, asserting the active-low W_DISABLE1# and W_DISABLE2#
lines and disabling the M.2 module's Wi-Fi and Bluetooth radios:

drivers/power/sequencing/pwrseq-pcie-m2.c:pwrseq_pcie_m2_probe() {
	...
	ctx->w_disable1_gpio = devm_gpiod_get_optional(dev, "w-disable1",
						       GPIOD_OUT_HIGH);
	...
	ctx->w_disable2_gpio = devm_gpiod_get_optional(dev, "w-disable2",
						       GPIOD_OUT_HIGH);
}

Those lines are only deasserted when a consumer matches via
pwrseq_pcie_m2_match(), which walks the connector's OF graph endpoints via
for_each_endpoint_of_node(ctx->of_node, endpoint). Without the ports nodes
linking m2-key-e-connector and m2-key-m-connector to the PCIe Root Ports,
UART, and SDIO controller (which are also required by
pcie-m2-e-connector.yaml and pcie-m2-m-connector.yaml), no consumer can
match and the radios remain permanently disabled.

> +	osc_mclk: oscillator-mclk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <19200000>;
> +		status = "disabled";
> +	};
> +
> +	osc_mclk_gated: oscillator-mclk-gated {
> +		compatible = "gpio-gate-clock";
> +		#clock-cells = <0>;
> +		clocks = <&osc_mclk>;
> +		enable-gpios = <&gpio_expander1 8 GPIO_ACTIVE_HIGH>;
> +		status = "disabled";
> +	};
> +
> +	fan: pwm-fan {
> +		compatible = "pwm-fan";
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <4 IRQ_TYPE_EDGE_RISING>;
> +		#cooling-cells = <2>;
> +		/* startup 35%, duty cycle 30%-100%;
> +		 * polarity inversion does not appear to work
> +		 */
> +		cooling-levels = <255 166 96 0>;
> +		/* fan-supply = <&reg_vdd_5v0>;  probe fails with this set */
> +		pwms = <&tpm5 3 86958 0>;
> +		pulses-per-revolution = <2>;
> +	};

[Severity: High]
Will cooling-levels = <255 166 96 0> turn the fan off when the thermal zone
reaches its highest temperature trip point (trip4 at 75C)?

In drivers/hwmon/pwm-fan.c, __set_pwm() treats a PWM value of 0 as fan
power-off rather than driving a 0% duty cycle:

drivers/hwmon/pwm-fan.c:__set_pwm() {
	...
	if (pwm > 0) {
		...
		state->duty_cycle = DIV_ROUND_UP(pwm * (period - 1), MAX_PWM);
		ret = pwm_apply_might_sleep(ctx->pwm, state);
		if (ret)
			return ret;
		ret = pwm_fan_power_on(ctx);
	} else {
		ret = pwm_fan_power_off(ctx, false);
	}
	...
}

When cooling state 3 selects cooling-levels[3] == 0, pwm_fan_power_off() sets
state->enabled = false. In drivers/pwm/pwm-imx-tpm.c, pwm_imx_tpm_apply_hw()
disables the TPM5_CH3 output driver when state->enabled is false, allowing the
pad pull-up on IMX95_PAD_GPIO_IO26__TPM5_CH3 (0x51e) to pull the inverted PWM
line high and stop the fan at 75C.

Additionally, pwm_fan_probe() sets the initial state to
cooling_levels[pwm_fan_max_state] (0), so the PWM channel is not enabled at
boot, and pwm_fan_update_state() expects cooling-levels to be ordered in
ascending order. Using a non-zero minimum value (such as 1) or configuring
active-high/inverted PWM handling would avoid disabling the channel at state 3.

[ ... ]

> +&gpio2 {
> +	gpio-line-names = "", "", "", "", "",
> +			  "", "", "", "", "",
> +			  "", "", "", "", "",
> +			  "", "RGMII2_nINT", "GPIO4", "RTC_INT", "",
> +			  "LVDS1_BL_EN";
> +};
> +
> +&lpi2c1 {
> +	temperature-sensor@4f {
> +		compatible = "nxp,p3t1755";
> +		reg = <0x4f>;
> +		vs-supply = <&reg_vdd_1v8>;
> +	};
> +};
> +
> +&lpi2c3 {
> +	status = "okay";
> +
> +	gpio_expander2: gpio@21 {
> +		compatible = "ti,tcal6416";
> +		reg = <0x21>;
> +		interrupt-parent = <&gpio2>;
> +		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
> +		#interrupt-cells = <2>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		gpio-line-names = "CAN1_STBY", "CAN2_STBY", "NC",
> +				  "KEY-E_nALERT", "KEY-M_nALERT",
> +				  "SDIO_nWAKE", "SDIO_nRESET", "HDMI_EN",
> +				  "RTC_nINT", "LVDS1_BL_EN", "SFP_TX_FAULT",
> +				  "SFP_TX_DISABLE", "SFP_MOD_ABS", "SFP_RS0",
> +				  "SFP_RX_LOSS", "SFP_RS1";

[Severity: Medium]
Should the &gpio2 gpio-line-names override in imx95-phyflex-libra-rdk.dts be
dropped?

On the SoM (imx95-phyflex-fpsc-g-som.dtsi), GPIO2 lines 18 and 20 are muxed to
SPI3_CS and SPI3_MOSI for lpspi4, while on the baseboard RTC_nINT and
LVDS1_BL_EN are on gpio_expander2 lines 8 and 9. Keeping "RTC_INT" and
"LVDS1_BL_EN" on &gpio2 duplicates the "LVDS1_BL_EN" line name and causes
userspace lookups by name to match gpio2 line 20 instead of gpio_expander2
line 9.

[ ... ]

> +/* M.2 Key-E PCIe */
> +&pcie0 {
> +	external-facing;
> +	supports-clkreq;
> +	wake-gpios = <&gpio_expander1 11 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +};
> +
> +&pcie0_port0 {
> +	reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> +	vpcie3v3-supply = <&reg_vdd_3v3>;
> +};
> +
> +/* M.2 Key-M PCIe */
> +&pcie1 {
> +	external-facing;
> +	supports-clkreq;
> +	wake-gpios = <&gpio_expander1 12 GPIO_ACTIVE_LOW>;
> +	status = "okay";
> +};
> +
> +&pcie1_port0 {
> +	reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
> +	vpcie3v3-supply = <&reg_vdd_3v3>;
> +};

[Severity: Medium]
Should external-facing and wake-gpios be placed on &pcie0_port0 and
&pcie1_port0 rather than on &pcie0 and &pcie1?

In drivers/pci/of.c, pci_set_bus_of_node() only checks external-facing when
bus->self is non-NULL (reading from the Root Port node rather than the host
bridge node), and pci_configure_of_wake_gpio() requests wake-gpios from the
enumerated pci_dev's OF node (&pcie0_port0 and &pcie1_port0). The
fsl,imx6q-pcie.yaml binding also only allows pci-pci-bridge.yaml properties
like external-facing and wake-gpios on the Root Port child node.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-wip-bhahn-imx95_upstreaming-v1-0-1c1cebb5be99@phytec.de?part=2

[PATCH 3/5] dts: imx95-phyflex-libra-rdk: Add overlays

[Benjamin Hahn]

Add overlays for SoM temperature sensors and M.2 Key-E WIFI/BT cards
that need the nxp,88w8987-bt compatible in devicetree (tested on
IW611/IW612).

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
---
 arch/arm64/boot/dts/freescale/Makefile             |  9 ++++++++
 .../imx95-phyflex-fpsc-g-som-temperature.dtso      | 23 +++++++++++++++++++++
 .../imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso | 24 ++++++++++++++++++++++
 3 files changed, 56 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 4eb7508193e7..17b357f4886a 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -739,7 +739,16 @@ imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo
 dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb
 
+imx95-phyflex-fpsc-g-som-temperature-dtbs := \
+			  imx95-phyflex-libra-rdk.dtb \
+			  imx95-phyflex-fpsc-g-som-temperature.dtbo
+imx95-phyflex-libra-rdk-bluetooth-88w8987-dtbs := \
+			  imx95-phyflex-libra-rdk.dtb \
+			  imx95-phyflex-libra-rdk-bluetooth-88w8987.dtbo
+
 dtb-$(CONFIG_ARCH_MXC) += imx95-phyflex-libra-rdk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-phyflex-fpsc-g-som-temperature.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-phyflex-libra-rdk-bluetooth-88w8987.dtb
 
 dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-verdin-evk.dtb
 
diff --git a/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som-temperature.dtso b/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som-temperature.dtso
new file mode 100644
index 000000000000..84afe1ff9f06
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-phyflex-fpsc-g-som-temperature.dtso
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ */
+
+/dts-v1/;
+/plugin/;
+
+&dram_sense {
+	status = "okay";
+};
+
+&emmc_sense {
+	status = "okay";
+};
+
+&ethphy_sense {
+	status = "okay";
+};
+
+&pmic_sense {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso
new file mode 100644
index 000000000000..1601e04b3940
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2026 PHYTEC Messtechnik GmbH
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&lpuart8 {
+	bluetooth {
+		compatible = "nxp,88w8987-bt";
+		fw-init-baudrate = <115200>;
+	};
+};
+
+&gpio_expander1 {
+	uart1_bt_rs_sel: bt-rs-hog {
+		gpios = <14 GPIO_ACTIVE_HIGH>;
+		gpio-hog;
+		line-name = "UART1_BT_RS_SEL";
+		output-high;
+	};
+};

-- 
2.53.0

Re: [PATCH 3/5] dts: imx95-phyflex-libra-rdk: Add overlays

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: imx95-phyflex-libra-rdk: missing OF graph link for M.2 BT pwrseq
--

commit 214248ffcd9454f4e28fccad2971f5e7db77d114
Author: Benjamin Hahn <B.Hahn@phytec.de>

dts: imx95-phyflex-libra-rdk: Add overlays

This commit adds devicetree overlays for the SoM temperature sensors and
for M.2 Key-E Wi-Fi/Bluetooth cards using the nxp,88w8987-bt compatible on
imx95-phyflex-libra-rdk.

> diff --git a/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso
> new file mode 100644
> index 0000000000000..1601e04b3940f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk-bluetooth-88w8987.dtso
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
> +/*
> + * Copyright (C) 2026 PHYTEC Messtechnik GmbH
> + */
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +&lpuart8 {
> +	bluetooth {
> +		compatible = "nxp,88w8987-bt";
> +		fw-init-baudrate = <115200>;
> +	};
> +};

[Severity: Medium]
Does lpuart8 also need an OF graph link to the m2-key-e-connector node so
that the M.2 Key-E Bluetooth power sequencer can deassert w-disable2-gpios?

In arch/arm64/boot/dts/freescale/imx95-phyflex-libra-rdk.dts, the base
board defines the M.2 connector without OF graph ports:

	m2-key-e-connector {
		compatible = "pcie-m2-e-connector";
		...
		w-disable1-gpios = <&gpio_expander1 9 GPIO_ACTIVE_LOW>;
		w-disable2-gpios = <&gpio_expander1 10 GPIO_ACTIVE_LOW>;
	};

When CONFIG_POWER_SEQUENCING_PCIE_M2 is enabled, pwrseq_pcie_m2_probe() in
drivers/power/sequencing/pwrseq-pcie-m2.c requests w-disable2-gpios with
GPIOD_OUT_HIGH, asserting the active-low W_nDISABLE2 signal:

	ctx->w_disable2_gpio = devm_gpiod_get_optional(dev, "w-disable2",
						       GPIOD_OUT_HIGH);

When nxp_serdev_probe() in drivers/bluetooth/btnxpuart.c probes the
bluetooth child node under lpuart8, it checks for the M.2 connector via OF
graph endpoints before acquiring and enabling the uart power sequencer
target:

	if (nxp_m2_connector_is_available(&serdev->ctrl->dev)) {
		struct pwrseq_desc *pwrseq;

		pwrseq = pwrseq_get(&serdev->ctrl->dev, "uart");

Without OF graph endpoints connecting lpuart8 and port@3 of
m2-key-e-connector, nxp_m2_connector_is_available() returns false, the uart
pwrseq target is never enabled, and w-disable2-gpios remains asserted.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-wip-bhahn-imx95_upstreaming-v1-0-1c1cebb5be99@phytec.de?part=3

[PATCH 4/5] dts: imx95-libra-rdk-fpsc: remove devicetree for old Libra

[Benjamin Hahn]

The old versions of the baseboard (1618.0) and SoM (1620.1) were only
ALPHA hardware and are not longer supported or built, as they were based
on the i.MX95 silicon revision A1, which is no longer available.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
---
 arch/arm64/boot/dts/freescale/Makefile             |   1 -
 .../boot/dts/freescale/imx95-libra-rdk-fpsc.dts    | 318 ----------
 .../boot/dts/freescale/imx95-phycore-fpsc.dtsi     | 656 ---------------------
 3 files changed, 975 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 17b357f4886a..acf3f6c06f98 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -737,7 +737,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
 imx95-19x19-evk-pcie0-ep-dtbs += imx95-19x19-evk.dtb imx-pcie0-ep.dtbo
 imx95-19x19-evk-pcie1-ep-dtbs += imx95-19x19-evk.dtb imx-pcie1-ep.dtbo
 dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb
 
 imx95-phyflex-fpsc-g-som-temperature-dtbs := \
 			  imx95-phyflex-libra-rdk.dtb \
diff --git a/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts
deleted file mode 100644
index 26c2df9b1b60..000000000000
--- a/arch/arm64/boot/dts/freescale/imx95-libra-rdk-fpsc.dts
+++ /dev/null
@@ -1,318 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2025 PHYTEC Messtechnik GmbH
- */
-
-/dts-v1/;
-
-#include <dt-bindings/leds/leds-pca9532.h>
-#include <dt-bindings/pwm/pwm.h>
-
-#include "imx95-phycore-fpsc.dtsi"
-
-/ {
-	compatible = "phytec,imx95-libra-rdk-fpsc",
-		"phytec,imx95-phycore-fpsc", "fsl,imx95";
-	model = "PHYTEC Libra i.MX95 RDK FPSC";
-
-	aliases {
-		can1 = &flexcan2;
-		can2 = &flexcan1;
-		ethernet0 = &enetc_port0;
-		serial0 = &lpuart7;
-		serial1 = &lpuart8;
-	};
-
-	chosen {
-		stdout-path = &lpuart7;
-	};
-
-	backlight_lvds0: backlight0 {
-		compatible = "pwm-backlight";
-		pinctrl-0 = <&pinctrl_lvds0>;
-		power-supply = <&reg_vdd_12v0>;
-		status = "disabled";
-	};
-
-	transceiver1: can-phy {
-		compatible = "ti,tcan1043";
-		#phy-cells = <0>;
-		max-bitrate = <8000000>;
-		enable-gpios = <&gpio_expander 10 GPIO_ACTIVE_LOW>;
-	};
-
-	transceiver2: can-phy {
-		compatible = "ti,tcan1043";
-		#phy-cells = <0>;
-		max-bitrate = <8000000>;
-		enable-gpios = <&gpio_expander 9 GPIO_ACTIVE_LOW>;
-	};
-
-	panel0_lvds: panel-lvds0 {
-		backlight = <&backlight_lvds0>;
-		power-supply = <&reg_vdd_3v3>;
-		status = "disabled";
-	};
-
-	reg_vdd_12v0: regulator-vdd-12v0 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-max-microvolt = <12000000>;
-		regulator-min-microvolt = <12000000>;
-		regulator-name = "VDD_12V0";
-	};
-
-	reg_vdd_1v8: regulator-vdd-1v8 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-max-microvolt = <1800000>;
-		regulator-min-microvolt = <1800000>;
-		regulator-name = "VDD_1V8";
-	};
-
-	reg_vdd_3v3: regulator-vdd-3v3 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-max-microvolt = <3300000>;
-		regulator-min-microvolt = <3300000>;
-		regulator-name = "VDD_3V3";
-	};
-
-	reg_vdd_5v0: regulator-vdd-5v0 {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-max-microvolt = <5000000>;
-		regulator-min-microvolt = <5000000>;
-		regulator-name = "VDD_5V0";
-	};
-};
-
-&enetc_port0 {
-	phy-handle = <&ethphy0>;
-	status = "okay";
-};
-
-&enetc_port2 {
-	managed = "in-band-status";
-	phy-handle = <&ethphy2>;
-	phy-mode = "10gbase-r";
-};
-
-/* CAN FD */
-&flexcan1 {
-	phys = <&transceiver1>;
-	status = "okay";
-};
-
-&flexcan2 {
-	phys = <&transceiver2>;
-	status = "okay";
-};
-
-/* SPI-NOR */
-&flexspi1 {
-	pinctrl-0 = <&pinctrl_flexspi>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	spi_nor: flash@0 {
-		compatible = "jedec,spi-nor";
-		reg = <0>;
-		spi-max-frequency = <166000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
-		vcc-supply = <&reg_vdd_1v8>;
-	};
-};
-
-&gpio2 {
-	gpio-line-names = "", "", "", "", "",
-			  "", "", "", "", "",
-			  "", "", "", "", "",
-			  "", "RGMII2_nINT", "GPIO4", "RTC_INT", "",
-			  "LVDS1_BL_EN";
-};
-
-&lpi2c1 {
-	temperature-sensor@4f {
-		compatible = "nxp,p3t1755";
-		reg = <0x4f>;
-		vs-supply = <&reg_vdd_1v8>;
-	};
-};
-
-&lpi2c3 {
-	status = "okay";
-
-	leds@62 {
-		compatible = "nxp,pca9533";
-		reg = <0x62>;
-
-		led-1 {
-			type = <PCA9532_TYPE_LED>;
-		};
-
-		led-2 {
-			type = <PCA9532_TYPE_LED>;
-		};
-
-		led-3 {
-			type = <PCA9532_TYPE_LED>;
-		};
-	};
-};
-
-&lpi2c4 {
-	status = "okay";
-
-	gpio_expander: gpio@20 {
-		compatible = "ti,tca6416";
-		reg = <0x20>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
-		#gpio-cells = <2>;
-		gpio-controller;
-		gpio-line-names = "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3",
-				  "CSI1_CTRL4", "CSI2_CTRL1", "CSI2_CTRL2",
-				  "CSI2_CTRL3", "CSI2_CTRL4", "CLK_EN_AV",
-				  "nCAN2_EN", "nCAN1_EN", "PCIE1_nWAKE",
-				  "PCIE2_nWAKE", "PCIE2_nALERT_3V3",
-				  "UART1_BT_RS_SEL", "UART1_RS232_485_SEL";
-		vcc-supply = <&reg_vdd_1v8>;
-
-		uart1_bt_rs_sel: bt-rs-hog {
-			gpios = <14 GPIO_ACTIVE_HIGH>;
-			gpio-hog;
-			line-name = "UART1_BT_RS_SEL";
-			output-low;
-		};
-	};
-};
-
-&lpi2c5 {
-	status = "okay";
-
-	eeprom@51 {
-		compatible = "atmel,24c02";
-		reg = <0x51>;
-		pagesize = <16>;
-		vcc-supply = <&reg_vdd_1v8>;
-	};
-};
-
-/* Used for M33 debug */
-&lpuart2 {
-	pinctrl-0 = <&pinctrl_lpuart2>;
-	pinctrl-names = "default";
-};
-
-/* A-55 debug UART */
-&lpuart7 {
-	status = "okay";
-};
-
-/* RS232/RS485/BT */
-&lpuart8 {
-	uart-has-rtscts;
-	status = "okay";
-};
-
-&netc_emdio { /* RGMII2 */
-	ethphy0: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x1>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
-		enet-phy-lane-no-swap;
-		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
-		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-	};
-
-	ethphy2: ethernet-phy@8 {
-		compatible = "ethernet-phy-ieee802.3-c45";
-		reg = <0x8>;
-		max-speed = <10000>; /* 10Gbit/s */
-		status = "disabled";
-	};
-};
-
-&pcie0 {
-	reset-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
-	vpcie-supply = <&reg_vdd_3v3>;
-	status = "okay";
-};
-
-&pcie1 {
-	reset-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
-	vpcie-supply = <&reg_vdd_3v3>;
-	status = "okay";
-};
-
-&rv3028 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_rtc>;
-	interrupt-parent = <&gpio2>;
-	interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
-	aux-voltage-chargeable = <1>;
-	wakeup-source;
-	trickle-resistor-ohms = <3000>;
-};
-
-&scmi_iomuxc {
-	pinctrl_lpuart2: lpuart2grp { /* FPSC proprietary */
-		fsl,pins = <
-			IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX	0x31e
-			IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX	0x31e
-		>;
-	};
-
-	pinctrl_lvds0: lvds0grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20	0x31e
-		>;
-	};
-
-	pinctrl_rtc: rtcgrp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18	0x31e
-		>;
-	};
-
-	pinctrl_tpm4: tpm4grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO21__TPM4_CH1	0x51e
-		>;
-	};
-};
-
-&tpm4 {
-	pinctrl-0 = <&pinctrl_tpm4>;
-	pinctrl-names = "default";
-};
-
-&usb3 {
-	fsl,over-current-active-low;
-	fsl,power-active-low;
-	status = "okay";
-};
-
-&usb3_dwc3 {
-	dr_mode = "peripheral";
-	status = "okay";
-};
-
-&usb3_phy {
-	vbus-supply = <&reg_vdd_5v0>;
-	status = "okay";
-};
-
-/* uSD Card */
-&usdhc2 {
-	status = "okay";
-};
diff --git a/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi b/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi
deleted file mode 100644
index 7519d5bd06ba..000000000000
--- a/arch/arm64/boot/dts/freescale/imx95-phycore-fpsc.dtsi
+++ /dev/null
@@ -1,656 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2025 PHYTEC Messtechnik GmbH
- */
-
-#include <dt-bindings/net/ti-dp83867.h>
-#include "imx95.dtsi"
-
-/ {
-	model = "PHYTEC phyCORE-i.MX95 FPSC";
-	compatible = "phytec,imx95-phycore-fpsc", "fsl,imx95";
-
-	aliases {
-		ethernet1 = &enetc_port1;
-		i2c1 = &lpi2c2;
-		i2c2 = &lpi2c5;
-		i2c3 = &lpi2c3;
-		i2c4 = &lpi2c4;
-		i2c5 = &lpi2c1;
-		rtc0 = &rv3028;
-		rtc1 = &scmi_bbm;
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000 0x00000001 0x00000000>;
-	};
-
-	reg_nvcc_aon: regulator-nvcc-aon {
-		compatible = "regulator-fixed";
-		regulator-always-on;
-		regulator-boot-on;
-		regulator-max-microvolt = <1800000>;
-		regulator-min-microvolt = <1800000>;
-		regulator-name = "VDD_IO";
-	};
-
-	reg_usdhc2_vmmc: regulator-usdhc2 {
-		compatible = "regulator-fixed";
-		off-on-delay-us = <12000>;
-		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-		pinctrl-names = "default";
-		regulator-max-microvolt = <3300000>;
-		regulator-min-microvolt = <3300000>;
-		regulator-name = "VDDSW_SD2";
-		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reserved-memory {
-		ranges;
-		#address-cells = <2>;
-		#size-cells = <2>;
-
-		linux,cma {
-			compatible = "shared-dma-pool";
-			alloc-ranges = <0 0x80000000 0 0x7f000000>;
-			reusable;
-			size = <0 0x3c000000>;
-			linux,cma-default;
-		};
-	};
-};
-
-&enetc_port0 { /* FPSC RGMII2 */
-	phy-mode = "rgmii-id";
-	pinctrl-0 = <&pinctrl_enetc0>;
-	pinctrl-names = "default";
-};
-
-&enetc_port1 {
-	phy-handle = <&ethphy1>;
-	phy-mode = "rgmii-id";
-	pinctrl-0 = <&pinctrl_enetc1>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&flexcan1 { /* FPSC CAN1 */
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	pinctrl-names = "default";
-};
-
-&flexcan2 { /* FPSC CAN2 */
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	pinctrl-names = "default";
-};
-
-&flexspi1 { /* FPSC QSPI */
-	pinctrl-0 = <&pinctrl_flexspi>;
-	pinctrl-names = "default";
-};
-
-&gpio1 { /* FPSC GPIO */
-	gpio-line-names = "", "", "", "", "GPIO2",
-			  "GPIO1", "", "", "", "",
-			  "PCIE1_nPERST", "USB1_PWR_EN", "GPIO3", "USB2_PWR_EN", "PCIE2_nPERST";
-	pinctrl-0 = <&pinctrl_gpio1>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&gpio2 { /* FPSC GPIO */
-	gpio-line-names = "", "", "", "", "",
-			  "", "", "", "", "",
-			  "", "", "", "", "",
-			  "", "RGMII2_nINT", "GPIO4";
-	pinctrl-0 = <&pinctrl_gpio2>;
-	pinctrl-names = "default";
-};
-
-&gpio3 {
-	gpio-line-names = "", "", "", "", "",
-			  "", "", "SD2_RESET_B";
-};
-
-&gpio4 {
-	gpio-line-names = "ENET2_nINT";
-};
-
-&gpio5 {
-	gpio-line-names = "", "", "", "", "",
-			  "", "", "", "", "",
-			  "", "", "", "USB1_OC", "USB2_OC";
-};
-
-&lpi2c1 { /* FPSC I2C5 */
-	clock-frequency = <400000>;
-	pinctrl-0 = <&pinctrl_lpi2c1>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	dram_sense: temperature-sensor@48 {
-		compatible = "ti,tmp102";
-		reg = <0x48>;
-		#thermal-sensor-cells = <1>;
-	};
-
-	emmc_sense: temperature-sensor@49 {
-		compatible = "ti,tmp102";
-		reg = <0x49>;
-		#thermal-sensor-cells = <1>;
-	};
-
-	ethphy_sense: temperature-sensor@4a {
-		compatible = "ti,tmp102";
-		reg = <0x4a>;
-		#thermal-sensor-cells = <1>;
-	};
-
-	pmic_sense: temperature-sensor@4b {
-		compatible = "ti,tmp102";
-		reg = <0x4b>;
-		#thermal-sensor-cells = <1>;
-	};
-
-	/* User EEPROM */
-	eeprom@50 {
-		compatible = "st,24c32", "atmel,24c32";
-		reg = <0x50>;
-		pagesize = <32>;
-		vcc-supply = <&reg_nvcc_aon>;
-	};
-
-	/* Factory EEPROM */
-	eeprom@51 {
-		compatible = "st,24c32", "atmel,24c32";
-		reg = <0x51>;
-		pagesize = <32>;
-		vcc-supply = <&reg_nvcc_aon>;
-	};
-
-	rv3028: rtc@52 {
-		compatible = "microcrystal,rv3028";
-		reg = <0x52>;
-	};
-
-	/* User EEPROM ID page */
-	eeprom@58 {
-		compatible = "st,24c32", "atmel,24c32";
-		reg = <0x58>;
-		pagesize = <32>;
-		vcc-supply = <&reg_nvcc_aon>;
-	};
-};
-
-&lpi2c2 { /* FPSC I2C1 */
-	clock-frequency = <400000>;
-	pinctrl-0 = <&pinctrl_lpi2c2>;
-	pinctrl-names = "default";
-};
-
-&lpi2c3 { /* FPSC I2C3 */
-	clock-frequency = <400000>;
-	pinctrl-0 = <&pinctrl_lpi2c3>;
-	pinctrl-names = "default";
-};
-
-&lpi2c4 { /* FPSC I2C4 */
-	clock-frequency = <400000>;
-	pinctrl-0 = <&pinctrl_lpi2c4>;
-	pinctrl-names = "default";
-};
-
-&lpi2c5 { /* FPSC I2C2 */
-	clock-frequency = <400000>;
-	pinctrl-0 = <&pinctrl_lpi2c5>;
-	pinctrl-names = "default";
-};
-
-&lpspi3 { /* FPSC SPI2 */
-	pinctrl-0 = <&pinctrl_lpspi3>;
-	pinctrl-names = "default";
-};
-
-&lpspi4 { /* FPSC SPI3 */
-	pinctrl-0 = <&pinctrl_lpspi4>;
-	pinctrl-names = "default";
-};
-
-&lpspi7 { /* FPSC SPI1 */
-	pinctrl-0 = <&pinctrl_lpspi7>;
-	pinctrl-names = "default";
-};
-
-&lpuart5 { /* FPSC UART2 */
-	pinctrl-0 = <&pinctrl_lpuart5>;
-	pinctrl-names = "default";
-};
-
-&lpuart7 { /* FPSC UART3 */
-	pinctrl-0 = <&pinctrl_lpuart7>;
-	pinctrl-names = "default";
-};
-
-&lpuart8 { /* FPSC UART1 */
-	pinctrl-0 = <&pinctrl_lpuart8>;
-	pinctrl-names = "default";
-};
-
-&netc_blk_ctrl {
-	status = "okay";
-};
-
-&netc_emdio { /* FPSC RGMII2 */
-	pinctrl-0 = <&pinctrl_emdio>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	ethphy1: ethernet-phy@0 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <0x0>;
-		interrupt-parent = <&gpio4>;
-		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-		enet-phy-lane-no-swap;
-		ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
-		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-	};
-};
-
-&netcmix_blk_ctrl {
-	status = "okay";
-};
-
-&pcie0 { /* FPSC PCIE1 */
-	pinctrl-0 = <&pinctrl_pcie0>;
-	pinctrl-names = "default";
-};
-
-&pcie1 { /* FPSC PCIE2 */
-	pinctrl-0 = <&pinctrl_pcie1>;
-	pinctrl-names = "default";
-};
-
-&sai5 {	/* FPSC SAI1 */
-	pinctrl-0 = <&pinctrl_sai5>;
-	pintrc-names = "default";
-};
-
-&scmi_iomuxc {
-	pinctrl_emdio: emdiogrp {
-		fsl,pins = <
-			IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO	0x97e	/* RGMII2_MDIO */
-			IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC	0x502	/* RGMII2_MDC */
-		>;
-	};
-
-	pinctrl_enetc0: enetc0grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16			0x31e	/* RGMII2_nINT */
-			IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2	0x31e	/* RGMII2_EVENT_IN */
-			IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2	0x31e	/* RGMII2_EVENT_OUT */
-
-			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x57e	/* RGMII2_TX_3 */
-			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x57e	/* RGMII2_TX_2 */
-			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x57e	/* RGMII2_TX_1 */
-			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x57e	/* RGMII2_TX_0 */
-			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e	/* RGMII2_TX_CTL */
-			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e	/* RGMII2_TXC */
-			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e	/* RGMII2_RX_3 */
-			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e	/* RGMII2_RX_2 */
-			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e	/* RGMII2_RX_1 */
-			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e	/* RGMII2_RX_0 */
-			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e	/* RGMII2_RX_CTL */
-			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e	/* RGMII2_RXC */
-		>;
-	};
-
-	pinctrl_enetc1: enetc1grp {
-		fsl,pins = <
-			IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0			0x31e
-			IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x57e
-			IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x57e
-			IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x57e
-			IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x57e
-			IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e
-			IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK	0x58e
-			IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e
-			IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e
-			IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e
-			IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e
-			IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e
-			IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK	0x58e
-		>;
-	};
-
-	pinctrl_flexcan1: flexcan1grp {
-		fsl,pins = <
-			IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX		0x51e	/* CAN1_TX */
-			IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX	0x51e	/* CAN1_RX */
-		>;
-	};
-
-	pinctrl_flexcan2: flexcan2grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO25__CAN2_TX	0x51e	/* CAN2_TX */
-			IMX95_PAD_GPIO_IO27__CAN2_RX	0x51e	/* CAN2_RX */
-		>;
-	};
-
-	pinctrl_flexspi: flexspigrp {
-		fsl,pins = <
-			IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B		0x3fe	/* QSPI_CE */
-			IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK		0x3fe	/* QSPI_CLK */
-			IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0	0x3fe	/* QSPI_DATA_0 */
-			IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1	0x3fe	/* QSPI_DATA_1 */
-			IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2	0x3fe	/* QSPI_DATA_2 */
-			IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3	0x3fe	/* QSPI_DATA_3 */
-			IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS		0x3fe	/* QSPI_DQS */
-		>;
-	};
-
-	pinctrl_gpio1: gpio1grp {
-		fsl,pins = <
-			IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5	0x31e	/* GPIO1 */
-			IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4	0x31e	/* GPIO2 */
-			IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12	0x31e	/* GPIO3 */
-		>;
-	};
-
-	pinctrl_gpio2: gpio2grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17	0x31e	/* GPIO4 */
-		>;
-	};
-
-	pinctrl_lpi2c1: lpi2c1grp {
-		fsl,pins = <
-			IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL	0x40000b9e	/* I2C5_SCL */
-			IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA	0x40000b9e	/* I2C5_SDA */
-		>;
-	};
-
-	pinctrl_lpi2c2: lpi2c2grp {
-		fsl,pins = <
-			IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA	0x40000b9e	/* I2C1_SDA_DNU */
-			IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL	0x40000b9e	/* I2C1_SCL_DNU */
-		>;
-	};
-
-	pinctrl_lpi2c3: lpi2c3grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e	/* I2C3_SDA */
-			IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e	/* I2C3_SCL */
-		>;
-	};
-
-	pinctrl_lpi2c4: lpi2c4grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e	/* I2C4_SDA */
-			IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e	/* I2C4_SDL */
-		>;
-	};
-
-	pinctrl_lpi2c5: lpi2c5grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO22__LPI2C5_SDA	0x40000b9e	/* I2C2_SDA */
-			IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e	/* I2C2_SCL */
-		>;
-	};
-
-	pinctrl_lpspi3: lpspi3grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO11__LPSPI3_SCK		0x51e	/* SPI2_SCLK */
-			IMX95_PAD_GPIO_IO10__LPSPI3_SOUT	0x51e	/* SPI2_MOSI */
-			IMX95_PAD_GPIO_IO09__LPSPI3_SIN		0x51e	/* SPI2_MISO */
-			IMX95_PAD_GPIO_IO08__LPSPI3_PCS0	0x51e	/* SPI2_CS */
-		>;
-	};
-
-	pinctrl_lpspi4: lpspi4grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO21__LPSPI4_SCK		0x51e	/* SPI3_SCLK */
-			IMX95_PAD_GPIO_IO20__LPSPI4_SOUT	0x51e	/* SPI3_MOSI */
-			IMX95_PAD_GPIO_IO19__LPSPI4_SIN		0x51e	/* SPI3_MISO */
-			IMX95_PAD_GPIO_IO18__LPSPI4_PCS0	0x51e	/* SPI3_CS */
-		>;
-	};
-
-	pinctrl_lpspi7: lpspi7grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO07__LPSPI7_SCK		0x51e	/* SPI1_SCLK */
-			IMX95_PAD_GPIO_IO06__LPSPI7_SOUT	0x51e	/* SPI1_MOSI */
-			IMX95_PAD_GPIO_IO05__LPSPI7_SIN		0x51e	/* SPI1_MISO */
-			IMX95_PAD_GPIO_IO04__LPSPI7_PCS0	0x51e	/* SPI1_CS */
-		>;
-	};
-
-	pinctrl_lpuart5: lpuart5grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO01__LPUART5_RX		0x51e	/* UART2_RXD */
-			IMX95_PAD_GPIO_IO00__LPUART5_TX		0x51e	/* UART2_TXD */
-			IMX95_PAD_GPIO_IO03__LPUART5_RTS_B	0x51e	/* UART2_RTS */
-			IMX95_PAD_GPIO_IO02__LPUART5_CTS_B	0x51e	/* UART2_CTS */
-		>;
-	};
-
-	pinctrl_lpuart7: lpuart7grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO37__LPUART7_RX	0x31e	/* UART3_RXD */
-			IMX95_PAD_GPIO_IO36__LPUART7_TX	0x31e	/* UART3_TXD */
-		>;
-	};
-
-	pinctrl_lpuart8: lpuart8grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO13__LPUART8_RX		0x51e	/* UART1_RXD */
-			IMX95_PAD_GPIO_IO12__LPUART8_TX		0x51e	/* UART1_TXD */
-			IMX95_PAD_GPIO_IO15__LPUART8_RTS_B	0x51e	/* UART1_RTS */
-			IMX95_PAD_GPIO_IO14__LPUART8_CTS_B	0x51e	/* UART1_CTS */
-		>;
-	};
-
-	pinctrl_pcie0: pcie0grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B		0x31e	/* PCIE1_nCLKREQ */
-			IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10	0x31e	/* PCIE1_nPERST */
-		>;
-	};
-
-	pinctrl_pcie1: pcie1grp {
-		fsl,pins = <
-			IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x31e	/* PCIE2_nCLKREQ */
-			IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14	0x31e	/* PCIE2_nPERST */
-		>;
-	};
-
-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-		fsl,pins = <
-			IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7	0x31e
-		>;
-	};
-
-	pinctrl_sai5: sai5grp {
-		fsl,pins = <
-			IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC		0x51e	/* SAI1_RX_SYNC */
-			IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK		0x51e	/* SAI1_RX_BCLK */
-			IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0	0x51e	/* SAI1_RX_DATA */
-			IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC		0x51e	/* SAI1_TX_SYNC */
-			IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK		0x51e	/* SAI1_TX_BCLK */
-			IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0	0x51e	/* SAI1_TX_DATA */
-		>;
-	};
-
-	pinctrl_tpm3: tpm3grp {
-	      fsl,pins = <
-		      IMX95_PAD_GPIO_IO24__TPM3_CH3	0x51e	/* PWM1 */
-	      >;
-	};
-
-	pinctrl_tpm5: tpm5grp {
-	      fsl,pins = <
-		      IMX95_PAD_GPIO_IO26__TPM5_CH3	0x51e	/* PWM2 */
-	      >;
-	};
-
-	pinctrl_usbc: usbcgrp {
-		fsl,pins = <
-			IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11	0x51e	/* USB1_PWR_EN */
-			IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13		0x51e	/* USB1_OC */
-		>;
-	};
-
-	pinctrl_usb2: usb2grp {
-		fsl,pins = <
-			IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13	0x51e	/* USB2_PWR_EN */
-			IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14		0x51e	/* USB2_OC */
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e
-			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e
-			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e
-			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e
-			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e
-			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e
-			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e
-			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e
-			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e
-			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e
-			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-		fsl,pins = <
-			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x138e
-			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x138e
-			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x138e
-			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x138e
-			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x138e
-			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x138e
-			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x138e
-			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x138e
-			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x138e
-			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x158e
-			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x158e
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-		fsl,pins = <
-			IMX95_PAD_SD1_DATA0__USDHC1_DATA0		0x13fe
-			IMX95_PAD_SD1_DATA1__USDHC1_DATA1		0x13fe
-			IMX95_PAD_SD1_DATA2__USDHC1_DATA2		0x13fe
-			IMX95_PAD_SD1_DATA3__USDHC1_DATA3		0x13fe
-			IMX95_PAD_SD1_DATA4__USDHC1_DATA4		0x13fe
-			IMX95_PAD_SD1_DATA5__USDHC1_DATA5		0x13fe
-			IMX95_PAD_SD1_DATA6__USDHC1_DATA6		0x13fe
-			IMX95_PAD_SD1_DATA7__USDHC1_DATA7		0x13fe
-			IMX95_PAD_SD1_CMD__USDHC1_CMD			0x13fe
-			IMX95_PAD_SD1_CLK__USDHC1_CLK			0x15fe
-			IMX95_PAD_SD1_STROBE__USDHC1_STROBE		0x15fe
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */
-			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */
-			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */
-			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */
-			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */
-			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */
-			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */
-			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
-
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-		fsl,pins = <
-			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */
-			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e	/* CLK */
-			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e	/* CMD */
-			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x138e	/* DATA0 */
-			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x138e	/* DATA1 */
-			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x138e	/* DATA2 */
-			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x138e	/* DATA3 */
-			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-		fsl,pins = <
-			IMX95_PAD_SD2_CD_B__USDHC2_CD_B		0x31e	/* CD */
-			IMX95_PAD_SD2_CLK__USDHC2_CLK		0x15fe	/* CLK */
-			IMX95_PAD_SD2_CMD__USDHC2_CMD		0x13fe	/* CMD */
-			IMX95_PAD_SD2_DATA0__USDHC2_DATA0	0x13fe	/* DATA0 */
-			IMX95_PAD_SD2_DATA1__USDHC2_DATA1	0x13fe	/* DATA1 */
-			IMX95_PAD_SD2_DATA2__USDHC2_DATA2	0x13fe	/* DATA2 */
-			IMX95_PAD_SD2_DATA3__USDHC2_DATA3	0x13fe	/* DATA3 */
-			IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT	0x51e
-		>;
-	};
-
-	pinctrl_usdhc3: usdhc3grp {
-		fsl,pins = <
-			IMX95_PAD_SD3_CLK__USDHC3_CLK		0x158e	/* SDIO_CLK */
-			IMX95_PAD_SD3_CMD__USDHC3_CMD		0x138e	/* SDIO_CMD */
-			IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x138e	/* SDIO_DATA0 */
-			IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x138e	/* SDIO_DATA1 */
-			IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x138e	/* SDIO_DATA2 */
-			IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x138e	/* SDIO_DATA3 */
-		>;
-	};
-};
-
-&tpm3 { /* FPSC PWM1 */
-	pinctrl-0 = <&pinctrl_tpm3>;
-	pinctrl-names = "default";
-};
-
-&tpm5 {	/* FPSC PWM2 */
-	pinctrl-0 = <&pinctrl_tpm5>;
-	pinctrl-names = "default";
-};
-
-&usb3 { /* FPSC USB1 */
-	pinctrl-0 = <&pinctrl_usbc>;
-	pinctrl-names = "default";
-};
-
-&usdhc1 {
-	bus-width = <8>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	pinctrl-3 = <&pinctrl_usdhc1>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
-	status = "okay";
-};
-
-&usdhc2 { /* FPSC SDCARD */
-	bus-width = <4>;
-	disable-wp;
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	pinctrl-3 = <&pinctrl_usdhc2>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
-	sd-uhs-sdr104;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-};
-
-&usdhc3 { /* FPSC SDIO */
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-names = "default";
-};

-- 
2.53.0

[PATCH 5/5] bindings: remove unused binding from old Libra version

[Benjamin Hahn]

Remove unused devicetree binding from old Libra board version.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index f917ae7202e9..dec6e22719b5 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1544,13 +1544,6 @@ properties:
               - fsl,imx952-evk            # i.MX952 EVK Board
           - const: fsl,imx952
 
-      - description: PHYTEC i.MX 95 FPSC based Boards
-        items:
-          - enum:
-              - phytec,imx95-libra-rdk-fpsc   # Libra-i.MX 95 FPSC
-          - const: phytec,imx95-phycore-fpsc  # phyCORE-i.MX 95 FPSC
-          - const: fsl,imx95
-
       - description: PHYTEC phyFLEX-i.MX95 FPSC-Gamma SoM based boards
         items:
           - enum:

-- 
2.53.0

Re: [PATCH 5/5] bindings: remove unused binding from old Libra version

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: arm: fsl: missing ABI removal rationale in commit message
--

commit 59deabe3729dc9f9716dfd3c6cfdb69f11310abd
Author: Benjamin Hahn <B.Hahn@phytec.de>

bindings: remove unused binding from old Libra version

This commit removes the PHYTEC i.MX 95 FPSC board and SoM compatible entries
from the Freescale/NXP arm devicetree binding schema.

>     bindings: remove unused binding from old Libra version
>     
>     Remove unused devicetree binding from old Libra board version.
>     
>     Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index f917ae7202e96..dec6e22719b5d 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1544,13 +1544,6 @@ properties:
>                - fsl,imx952-evk            # i.MX952 EVK Board
>            - const: fsl,imx952
>  
> -      - description: PHYTEC i.MX 95 FPSC based Boards
> -        items:
> -          - enum:
> -              - phytec,imx95-libra-rdk-fpsc   # Libra-i.MX 95 FPSC
> -          - const: phytec,imx95-phycore-fpsc  # phyCORE-i.MX 95 FPSC
> -          - const: fsl,imx95
> -
>        - description: PHYTEC phyFLEX-i.MX95 FPSC-Gamma SoM based boards
>          items:
>            - enum:

[Severity: Medium]
This isn't a bug in the schema syntax, but since devicetree bindings form an
external ABI (Documentation/devicetree/bindings/ABI.rst and
Documentation/devicetree/bindings/submitting-patches.rst section I.9), is
being unused in the kernel tree sufficient justification on its own for
removing phytec,imx95-libra-rdk-fpsc and phytec,imx95-phycore-fpsc from
properties.compatible in Documentation/devicetree/bindings/arm/fsl.yaml?

The current commit message only restates the subject line without explaining
why breaking or removing this binding ABI is acceptable. In the companion DTS
commits 4a096b093cf5 ("dts: imx95-libra-rdk-fpsc: remove devicetree for old
Libra") and 01cb871eca78, it is explained that the old baseboard (1618.0) and
SoM (1620.1) were alpha-only hardware based on i.MX95 silicon revision A1 that
are no longer available, built, or supported, and have been superseded by
hardware revisions 1618.2 and 1620.3 using phytec,imx95-phyflex-libra-rdk and
phytec,imx95-phyflex-fpsc-g.

Because devicetree binding patches and DTS patches are often reviewed and
applied through separate trees, could the commit message be expanded to
include this hardware rationale, mention both the i.MX95 SoC family context
(as fsl.yaml also documents phytec,imx8mp-libra-rdk-fpsc) and the removed
phytec,imx95-phycore-fpsc SoM compatible, and use the standard
"dt-bindings: arm: fsl:" subject prefix?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261030-wip-bhahn-imx95_upstreaming-v1-0-1c1cebb5be99@phytec.de?part=5