From: Sean Anderson <sean.anderson@seco.com>
To: Li Yang <leoyang.li@nxp.com>,
shawnguo@kernel.org, devicetree@vger.kernel.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Laurentiu Tudor <laurentiu.tudor@nxp.com>
Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC
Date: Fri, 23 Sep 2022 12:10:36 -0400 [thread overview]
Message-ID: <e27d295b-abbf-716c-5e0d-97dd63ce07df@seco.com> (raw)
In-Reply-To: <20220915233432.31660-6-leoyang.li@nxp.com>
Hi All,
On 9/15/22 7:34 PM, Li Yang wrote:
> These SoCs are really completely dma coherent in their entirety so add
> the dma-coherent property at the soc level in the device tree and drop
> the instances where it's specifically added to a few select devices.
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 27033c558e3e..e406499a26b4 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -273,6 +273,7 @@ soc: soc {
> #size-cells = <2>;
> ranges;
> dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> + dma-coherent;
>
> ddr: memory-controller@1080000 {
> compatible = "fsl,qoriq-memory-controller";
> @@ -355,7 +356,6 @@ crypto: crypto@1700000 {
> ranges = <0x0 0x00 0x1700000 0x100000>;
> reg = <0x00 0x1700000 0x0 0x100000>;
> interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> - dma-coherent;
>
> sec_jr0: jr@10000 {
> compatible = "fsl,sec-v5.4-job-ring",
> @@ -794,7 +794,6 @@ pcie1: pcie@3400000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
> @@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
> @@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
>
I'd like to summarize the conclusions of [1] below. This patch breaks
I2C0, which is the only user of eDMA at the moment. eDMA is noncoherent
because snooping is not enabled for it. I have submitted a patch [2] to
U-Boot to enable snooping for eDMA. For now, this patch must add
dma-noncoherent to the i2c0 node.
--Sean
[1] https://lore.kernel.org/linux-arm-kernel/29a09f45-24f9-68be-bdc2-8691af41b5db@seco.com/T/#t
[2] https://lore.kernel.org/u-boot/20220923160551.2200873-1-sean.anderson@seco.com/T/#u
WARNING: multiple messages have this Message-ID (diff)
From: Sean Anderson <sean.anderson@seco.com>
To: Li Yang <leoyang.li@nxp.com>,
shawnguo@kernel.org, devicetree@vger.kernel.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Laurentiu Tudor <laurentiu.tudor@nxp.com>
Subject: Re: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC
Date: Fri, 23 Sep 2022 12:10:36 -0400 [thread overview]
Message-ID: <e27d295b-abbf-716c-5e0d-97dd63ce07df@seco.com> (raw)
In-Reply-To: <20220915233432.31660-6-leoyang.li@nxp.com>
Hi All,
On 9/15/22 7:34 PM, Li Yang wrote:
> These SoCs are really completely dma coherent in their entirety so add
> the dma-coherent property at the soc level in the device tree and drop
> the instances where it's specifically added to a few select devices.
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Signed-off-by: Li Yang <leoyang.li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index 27033c558e3e..e406499a26b4 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -273,6 +273,7 @@ soc: soc {
> #size-cells = <2>;
> ranges;
> dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
> + dma-coherent;
>
> ddr: memory-controller@1080000 {
> compatible = "fsl,qoriq-memory-controller";
> @@ -355,7 +356,6 @@ crypto: crypto@1700000 {
> ranges = <0x0 0x00 0x1700000 0x100000>;
> reg = <0x00 0x1700000 0x0 0x100000>;
> interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> - dma-coherent;
>
> sec_jr0: jr@10000 {
> compatible = "fsl,sec-v5.4-job-ring",
> @@ -794,7 +794,6 @@ pcie1: pcie@3400000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
> @@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
> @@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - dma-coherent;
> num-viewport = <8>;
> bus-range = <0x0 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
>
I'd like to summarize the conclusions of [1] below. This patch breaks
I2C0, which is the only user of eDMA at the moment. eDMA is noncoherent
because snooping is not enabled for it. I have submitted a patch [2] to
U-Boot to enable snooping for eDMA. For now, this patch must add
dma-noncoherent to the i2c0 node.
--Sean
[1] https://lore.kernel.org/linux-arm-kernel/29a09f45-24f9-68be-bdc2-8691af41b5db@seco.com/T/#t
[2] https://lore.kernel.org/u-boot/20220923160551.2200873-1-sean.anderson@seco.com/T/#u
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-23 16:10 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-15 23:34 [PATCH v2 0/9] accumulated dts updates for ls1046a Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 2/9] arm64: dts: ls1046a: Add the PME interrupt and big-endian to PCIe EP nodes Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 4/9] arm64: dts: ls1046a: add missing dma ranges property Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-23 16:10 ` Sean Anderson [this message]
2022-09-23 16:10 ` Sean Anderson
2022-09-23 16:26 ` Leo Li
2022-09-23 16:26 ` Leo Li
2022-09-23 16:35 ` Sean Anderson
2022-09-23 16:35 ` Sean Anderson
2022-09-28 23:15 ` Leo Li
2022-09-28 23:15 ` Leo Li
2022-09-29 15:33 ` Sean Anderson
2022-09-29 15:33 ` Sean Anderson
2022-09-15 23:34 ` [PATCH v2 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux nodes for FPGA Li Yang
2022-09-15 23:34 ` Li Yang
2022-09-15 23:34 ` [PATCH v2 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency Li Yang
2022-09-15 23:34 ` Li Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e27d295b-abbf-716c-5e0d-97dd63ce07df@seco.com \
--to=sean.anderson@seco.com \
--cc=devicetree@vger.kernel.org \
--cc=laurentiu.tudor@nxp.com \
--cc=leoyang.li@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=shawnguo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.