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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Anand Moon <linux.amoon@gmail.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"moderated list:ARM/Amlogic Meson SoC support"
	<linux-arm-kernel@lists.infradead.org>,
	"open list:ARM/Amlogic Meson SoC support"
	<linux-amlogic@lists.infradead.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
Date: Thu, 4 Sep 2025 15:37:47 +0200	[thread overview]
Message-ID: <e31d35c8-b2b2-4301-a13c-e18ad83a21d6@kernel.org> (raw)
In-Reply-To: <20250825065240.22577-3-linux.amoon@gmail.com>

On 25/08/2025 08:51, Anand Moon wrote:
> As per S905X3 datasheet add missing cache information to the Amlogic
> SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.
> 
> - Each Cortex-A55 core has 32KB of L1 instruction cache available and
> 	32KB of L1 data cache available.
> - Along with 256KB Unified L2 cache.
> 
> Cache memory significantly reduces the time it takes for the CPU
> to access data and instructions, leading to faster program execution
> and overall system responsiveness.


This statement is obvious and completely redundant. Drop it from all of
the commits.

Best regards,
Krzysztof

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Anand Moon <linux.amoon@gmail.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"moderated list:ARM/Amlogic Meson SoC support"
	<linux-arm-kernel@lists.infradead.org>,
	"open list:ARM/Amlogic Meson SoC support"
	<linux-amlogic@lists.infradead.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC
Date: Thu, 4 Sep 2025 15:37:47 +0200	[thread overview]
Message-ID: <e31d35c8-b2b2-4301-a13c-e18ad83a21d6@kernel.org> (raw)
In-Reply-To: <20250825065240.22577-3-linux.amoon@gmail.com>

On 25/08/2025 08:51, Anand Moon wrote:
> As per S905X3 datasheet add missing cache information to the Amlogic
> SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.
> 
> - Each Cortex-A55 core has 32KB of L1 instruction cache available and
> 	32KB of L1 data cache available.
> - Along with 256KB Unified L2 cache.
> 
> Cache memory significantly reduces the time it takes for the CPU
> to access data and instructions, leading to faster program execution
> and overall system responsiveness.


This statement is obvious and completely redundant. Drop it from all of
the commits.

Best regards,
Krzysztof


  reply	other threads:[~2025-09-04 16:28 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-25  6:51 [PATCH v2 00/11] Add cache information to Amlogic SoC Anand Moon
2025-08-25  6:51 ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  7:58   ` Christian Hewitt
2025-08-25 12:57     ` Anand Moon
2025-08-25 12:57       ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-09-04 13:37   ` Krzysztof Kozlowski [this message]
2025-09-04 13:37     ` Krzysztof Kozlowski
2025-09-05  3:51     ` Anand Moon
2025-09-05  3:51       ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 03/11] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 04/11] arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 05/11] arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 06/11] arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 07/11] arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 08/11] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 09/11] arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 10/11] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-08-25  6:51 ` [PATCH v2 11/11] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC Anand Moon
2025-08-25  6:51   ` Anand Moon
2025-09-04 13:28 ` [PATCH v2 00/11] Add cache information to Amlogic SoC Neil Armstrong
2025-09-04 13:28   ` Neil Armstrong
2025-09-05  4:01   ` Anand Moon
2025-09-05  4:01     ` Anand Moon
2025-09-05 10:20     ` Neil Armstrong
2025-09-05 10:20       ` Neil Armstrong

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