* [PATCH v6 0/9] Add i.MX91 platform support
@ 2025-06-23 9:57 Joy Zou
2025-06-23 9:57 ` [PATCH v6 1/9] dt-bindings: arm: fsl: add i.MX91 11x11 evk board Joy Zou
` (9 more replies)
0 siblings, 10 replies; 21+ messages in thread
From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will,
andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32,
alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev,
linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong
The design of i.MX91 platform is very similar to i.MX93.
Extracts the common parts in order to reuse code.
The mainly difference between i.MX91 and i.MX93 is as follows:
- i.MX91 removed some clocks and modified the names of some clocks.
- i.MX91 only has one A core.
- i.MX91 has different pinmux.
- i.MX91 has updated to new temperature sensor same with i.MX95.
---
Changes for v6:
- add changelog in per patch.
- correct commit message spell for patch #1.
- merge rename imx93.dtsi to imx91_93_common.dtsi and move i.MX93
specific part from imx91_93_common.dtsi to imx93.dtsi for patch #3.
- modify the commit message for patch #3.
- restore copyright time and add modification time for common dtsi for patch #3.
- remove unused map0 label in imx91_93_common.dtsi for patch #3.
- remove tmu related node for patch #4.
- remove unused regulators and pinctrl settings for patch #5.
- add new modification for aliases change patch #6.
Changes for v5:
- rename imx93.dtsi to imx91_93_common.dtsi.
- move imx93 specific part from imx91_93_common.dtsi to imx93.dtsi.
- modify the imx91.dtsi to use imx91_93_common.dtsi.
- add new the imx93-blk-ctrl binding and driver patch for imx91 support.
- add new net patch for imx91 support.
- change node name codec and lsm6dsm into common name audio-codec and
inertial-meter, and add BT compatible string for imx91 board dts.
Changes for v4:
- Add one imx93 patch that add labels in imx93.dtsi
- modify the references in imx91.dtsi
- modify the code alignment
- remove unused newline
- delete the status property
- align pad hex values
Changes for v3:
- Add Conor's ack on patch #1
- format imx91-11x11-evk.dts with the dt-format tool
- add lpi2c1 node
Changes for v2:
- change ddr node pmu compatible
- remove mu1 and mu2
- change iomux node compatible and enable 91 pinctrl
- refine commit message for patch #2
- change hex to lowercase in pinfunc.h
- ordering nodes with the dt-format tool
Joy Zou (8):
dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible
arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and
modify them
arm64: dts: imx91: add i.MX91 dtsi support
arm64: dts: freescale: add i.MX91 11x11 EVK basic support
arm64: dts: freescale: move aliases from imx91_93_common.dtsi to board
dts
arm64: defconfig: enable i.MX91 pinctrl
pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on
i.MX91
net: stmmac: imx: add i.MX91 support
Pengfei Li (1):
dt-bindings: arm: fsl: add i.MX91 11x11 evk board
.../devicetree/bindings/arm/fsl.yaml | 6 +
.../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 55 +-
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../boot/dts/freescale/imx91-11x11-evk.dts | 679 ++++++++
arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 +++++++++
arch/arm64/boot/dts/freescale/imx91.dtsi | 71 +
.../{imx93.dtsi => imx91_93_common.dtsi} | 176 +-
.../boot/dts/freescale/imx93-11x11-evk.dts | 19 +
arch/arm64/boot/dts/freescale/imx93.dtsi | 1512 ++---------------
arch/arm64/configs/defconfig | 1 +
.../net/ethernet/stmicro/stmmac/dwmac-imx.c | 2 +
drivers/pmdomain/imx/imx93-blk-ctrl.c | 15 +
12 files changed, 1771 insertions(+), 1536 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h
create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi
copy arch/arm64/boot/dts/freescale/{imx93.dtsi => imx91_93_common.dtsi} (90%)
rewrite arch/arm64/boot/dts/freescale/imx93.dtsi (97%)
--
2.37.1
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH v6 1/9] dt-bindings: arm: fsl: add i.MX91 11x11 evk board 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 9:57 ` [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible Joy Zou ` (8 subsequent siblings) 9 siblings, 0 replies; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong From: Pengfei Li <pengfei.li_1@nxp.com> Add the board imx91-11x11-evk in the binding document. Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Signed-off-by: Joy Zou <joy.zou@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- Changes for v6: 1. correct the commit message spell. Changes for v3: 1. add Acked-by tag. --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d3b5e6923e41..a778666b1d42 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1374,6 +1374,12 @@ properties: - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp + - description: i.MX91 based Boards + items: + - enum: + - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - const: fsl,imx91 + - description: i.MX93 based Boards items: - enum: -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou 2025-06-23 9:57 ` [PATCH v6 1/9] dt-bindings: arm: fsl: add i.MX91 11x11 evk board Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 14:51 ` Frank Li 2025-06-24 7:28 ` Krzysztof Kozlowski 2025-06-23 9:57 ` [PATCH v6 3/9] arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them Joy Zou ` (7 subsequent siblings) 9 siblings, 2 replies; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong Add new compatible string "fsl,imx91-media-blk-ctrl" for i.MX91, which has different input clocks compared to i.MX93. Update the clock-names list and handle it in the if-else branch accordingly. Keep the same restriction for the existed compatible strings. Signed-off-by: Joy Zou <joy.zou@nxp.com> --- Changes for v5: 1. modify the imx93-blk-ctrl binding for imx91 support. --- .../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 55 +++++++++++++++---- 1 file changed, 43 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml index b3554e7f9e76..db5ee65f8eb8 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -18,7 +18,9 @@ description: properties: compatible: items: - - const: fsl,imx93-media-blk-ctrl + - enum: + - fsl,imx91-media-blk-ctrl + - fsl,imx93-media-blk-ctrl - const: syscon reg: @@ -31,21 +33,50 @@ properties: maxItems: 1 clocks: + minItems: 8 maxItems: 10 clock-names: - items: - - const: apb - - const: axi - - const: nic - - const: disp - - const: cam - - const: pxp - - const: lcdif - - const: isi - - const: csi - - const: dsi + minItems: 8 + maxItems: 10 +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx93-media-blk-ctrl + then: + properties: + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: pxp + - const: lcdif + - const: isi + - const: csi + - const: dsi + - if: + properties: + compatible: + contains: + const: fsl,imx91-media-blk-ctrl + then: + properties: + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: lcdif + - const: isi + - const: csi required: - compatible - reg -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible 2025-06-23 9:57 ` [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible Joy Zou @ 2025-06-23 14:51 ` Frank Li 2025-06-24 7:28 ` Krzysztof Kozlowski 1 sibling, 0 replies; 21+ messages in thread From: Frank Li @ 2025-06-23 14:51 UTC (permalink / raw) To: Joy Zou Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, ye.li, ping.bai, aisheng.dong On Mon, Jun 23, 2025 at 05:57:25PM +0800, Joy Zou wrote: > Add new compatible string "fsl,imx91-media-blk-ctrl" for i.MX91, > which has different input clocks compared to i.MX93. Update the > clock-names list and handle it in the if-else branch accordingly. > > Keep the same restriction for the existed compatible strings. > > Signed-off-by: Joy Zou <joy.zou@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- > Changes for v5: > 1. modify the imx93-blk-ctrl binding for imx91 support. > --- > .../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 55 +++++++++++++++---- > 1 file changed, 43 insertions(+), 12 deletions(-) > > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > index b3554e7f9e76..db5ee65f8eb8 100644 > --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > @@ -18,7 +18,9 @@ description: > properties: > compatible: > items: > - - const: fsl,imx93-media-blk-ctrl > + - enum: > + - fsl,imx91-media-blk-ctrl > + - fsl,imx93-media-blk-ctrl > - const: syscon > > reg: > @@ -31,21 +33,50 @@ properties: > maxItems: 1 > > clocks: > + minItems: 8 > maxItems: 10 > > clock-names: > - items: > - - const: apb > - - const: axi > - - const: nic > - - const: disp > - - const: cam > - - const: pxp > - - const: lcdif > - - const: isi > - - const: csi > - - const: dsi > + minItems: 8 > + maxItems: 10 > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx93-media-blk-ctrl > + then: > + properties: > + clock-names: > + items: > + - const: apb > + - const: axi > + - const: nic > + - const: disp > + - const: cam > + - const: pxp > + - const: lcdif > + - const: isi > + - const: csi > + - const: dsi > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx91-media-blk-ctrl > + then: > + properties: > + clock-names: > + items: > + - const: apb > + - const: axi > + - const: nic > + - const: disp > + - const: cam > + - const: lcdif > + - const: isi > + - const: csi > required: > - compatible > - reg > -- > 2.37.1 > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible 2025-06-23 9:57 ` [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible Joy Zou 2025-06-23 14:51 ` Frank Li @ 2025-06-24 7:28 ` Krzysztof Kozlowski 2025-06-24 14:51 ` Frank Li 1 sibling, 1 reply; 21+ messages in thread From: Krzysztof Kozlowski @ 2025-06-24 7:28 UTC (permalink / raw) To: Joy Zou Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong On Mon, Jun 23, 2025 at 05:57:25PM +0800, Joy Zou wrote: > Add new compatible string "fsl,imx91-media-blk-ctrl" for i.MX91, > which has different input clocks compared to i.MX93. Update the > clock-names list and handle it in the if-else branch accordingly. > > Keep the same restriction for the existed compatible strings. > > Signed-off-by: Joy Zou <joy.zou@nxp.com> > --- > Changes for v5: > 1. modify the imx93-blk-ctrl binding for imx91 support. This is just vague. Anything can be "modify". Why are you doing this? What are you doing here? > --- > .../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 55 +++++++++++++++---- > 1 file changed, 43 insertions(+), 12 deletions(-) > > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > index b3554e7f9e76..db5ee65f8eb8 100644 > --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > @@ -18,7 +18,9 @@ description: > properties: > compatible: > items: > - - const: fsl,imx93-media-blk-ctrl > + - enum: > + - fsl,imx91-media-blk-ctrl > + - fsl,imx93-media-blk-ctrl > - const: syscon > > reg: > @@ -31,21 +33,50 @@ properties: > maxItems: 1 > > clocks: > + minItems: 8 > maxItems: 10 > > clock-names: > - items: > - - const: apb > - - const: axi > - - const: nic > - - const: disp > - - const: cam > - - const: pxp > - - const: lcdif > - - const: isi > - - const: csi > - - const: dsi > + minItems: 8 > + maxItems: 10 > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx93-media-blk-ctrl > + then: > + properties: Missing constraints for clocks > + clock-names: > + items: > + - const: apb > + - const: axi > + - const: nic > + - const: disp > + - const: cam > + - const: pxp > + - const: lcdif > + - const: isi > + - const: csi > + - const: dsi Keep list in comon part. > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx91-media-blk-ctrl This should be before if: for imx93. 91 < 93 > + then: > + properties: Why imx91 now has 10 clocks? v6 and this has basic issues. The quality of NXP patches decreases :/ > + clock-names: > + items: > + - const: apb > + - const: axi > + - const: nic > + - const: disp > + - const: cam > + - const: lcdif > + - const: isi > + - const: csi No, look at other bindings how they share clock lists. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible 2025-06-24 7:28 ` Krzysztof Kozlowski @ 2025-06-24 14:51 ` Frank Li 2025-06-24 15:39 ` Krzysztof Kozlowski 0 siblings, 1 reply; 21+ messages in thread From: Frank Li @ 2025-06-24 14:51 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Joy Zou, robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, ye.li, ping.bai, aisheng.dong On Tue, Jun 24, 2025 at 09:28:43AM +0200, Krzysztof Kozlowski wrote: > On Mon, Jun 23, 2025 at 05:57:25PM +0800, Joy Zou wrote: > > Add new compatible string "fsl,imx91-media-blk-ctrl" for i.MX91, > > which has different input clocks compared to i.MX93. Update the > > clock-names list and handle it in the if-else branch accordingly. > > > > Keep the same restriction for the existed compatible strings. > > > > Signed-off-by: Joy Zou <joy.zou@nxp.com> > > --- > > Changes for v5: > > 1. modify the imx93-blk-ctrl binding for imx91 support. > > This is just vague. Anything can be "modify". Why are you doing this? > What are you doing here? > > > --- > > .../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 55 +++++++++++++++---- > > 1 file changed, 43 insertions(+), 12 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > > index b3554e7f9e76..db5ee65f8eb8 100644 > > --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml > > @@ -18,7 +18,9 @@ description: > > properties: > > compatible: > > items: > > - - const: fsl,imx93-media-blk-ctrl > > + - enum: > > + - fsl,imx91-media-blk-ctrl > > + - fsl,imx93-media-blk-ctrl > > - const: syscon > > > > reg: > > @@ -31,21 +33,50 @@ properties: > > maxItems: 1 > > > > clocks: > > + minItems: 8 > > maxItems: 10 > > > > clock-names: > > - items: > > - - const: apb > > - - const: axi > > - - const: nic > > - - const: disp > > - - const: cam > > - - const: pxp > > - - const: lcdif > > - - const: isi > > - - const: csi > > - - const: dsi > > + minItems: 8 > > + maxItems: 10 > > > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: fsl,imx93-media-blk-ctrl > > + then: > > + properties: > > Missing constraints for clocks > > > + clock-names: > > + items: > > + - const: apb > > + - const: axi > > + - const: nic > > + - const: disp > > + - const: cam > > + - const: pxp > > + - const: lcdif > > + - const: isi > > + - const: csi > > + - const: dsi > > Keep list in comon part. > > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: fsl,imx91-media-blk-ctrl > > This should be before if: for imx93. 91 < 93 > > > + then: > > + properties: > > Why imx91 now has 10 clocks? > > v6 and this has basic issues. The quality of NXP patches decreases :/ > > > + clock-names: > > + items: > > + - const: apb > > + - const: axi > > + - const: nic > > + - const: disp > > + - const: cam > > + - const: lcdif > > + - const: isi > > + - const: csi > > No, look at other bindings how they share clock lists. Sorry, this method is what I suggested. becuase there are pxp between cam and lcdif, can't use simple minItems/maxItems to limit list. If put two lists at top, clock-names list have to dupliate at both top and if-else branch. If there are better solution, please point me which file have good method to share two totally difference list. Frank > > Best regards, > Krzysztof > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible 2025-06-24 14:51 ` Frank Li @ 2025-06-24 15:39 ` Krzysztof Kozlowski 2025-06-24 19:08 ` Frank Li 0 siblings, 1 reply; 21+ messages in thread From: Krzysztof Kozlowski @ 2025-06-24 15:39 UTC (permalink / raw) To: Frank Li Cc: Joy Zou, robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, ye.li, ping.bai, aisheng.dong On 24/06/2025 16:51, Frank Li wrote: >> >> Why imx91 now has 10 clocks? >> >> v6 and this has basic issues. The quality of NXP patches decreases :/ >> >>> + clock-names: >>> + items: >>> + - const: apb >>> + - const: axi >>> + - const: nic >>> + - const: disp >>> + - const: cam >>> + - const: lcdif >>> + - const: isi >>> + - const: csi >> >> No, look at other bindings how they share clock lists. > > Sorry, this method is what I suggested. becuase there are pxp between cam > and lcdif, can't use simple minItems/maxItems to limit list. The point is to put new items, so pxp, at the end. > > If put two lists at top, clock-names list have to dupliate at both top and > if-else branch. > > If there are better solution, please point me which file have good method > to share two totally difference list. > Best regards, Krzysztof ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible 2025-06-24 15:39 ` Krzysztof Kozlowski @ 2025-06-24 19:08 ` Frank Li 2025-06-25 6:10 ` Krzysztof Kozlowski 0 siblings, 1 reply; 21+ messages in thread From: Frank Li @ 2025-06-24 19:08 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Joy Zou, robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, ye.li, ping.bai, aisheng.dong On Tue, Jun 24, 2025 at 05:39:43PM +0200, Krzysztof Kozlowski wrote: > On 24/06/2025 16:51, Frank Li wrote: > >> > >> Why imx91 now has 10 clocks? > >> > >> v6 and this has basic issues. The quality of NXP patches decreases :/ > >> > >>> + clock-names: > >>> + items: > >>> + - const: apb > >>> + - const: axi > >>> + - const: nic > >>> + - const: disp > >>> + - const: cam > >>> + - const: lcdif > >>> + - const: isi > >>> + - const: csi > >> > >> No, look at other bindings how they share clock lists. > > > > Sorry, this method is what I suggested. becuase there are pxp between cam > > and lcdif, can't use simple minItems/maxItems to limit list. > > The point is to put new items, so pxp, at the end. There are already a list for imx93. If change list order, it will break ABI. This was rejected at other binding doc review. Frank > > > > > If put two lists at top, clock-names list have to dupliate at both top and > > if-else branch. > > > > If there are better solution, please point me which file have good method > > to share two totally difference list. > > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible 2025-06-24 19:08 ` Frank Li @ 2025-06-25 6:10 ` Krzysztof Kozlowski 0 siblings, 0 replies; 21+ messages in thread From: Krzysztof Kozlowski @ 2025-06-25 6:10 UTC (permalink / raw) To: Frank Li Cc: Joy Zou, robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, ye.li, ping.bai, aisheng.dong On 24/06/2025 21:08, Frank Li wrote: >>>>> + clock-names: >>>>> + items: >>>>> + - const: apb >>>>> + - const: axi >>>>> + - const: nic >>>>> + - const: disp >>>>> + - const: cam >>>>> + - const: lcdif >>>>> + - const: isi >>>>> + - const: csi >>>> >>>> No, look at other bindings how they share clock lists. >>> >>> Sorry, this method is what I suggested. becuase there are pxp between cam >>> and lcdif, can't use simple minItems/maxItems to limit list. >> >> The point is to put new items, so pxp, at the end. > > There are already a list for imx93. If change list order, it will break > ABI. This was rejected at other binding doc review. I see, I mixed the SoCs. It is a pity you upstream that way and do not try to make the list common. Anyway names indeed need to be constrained per variant, but the rest of the comments stay. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 3/9] arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou 2025-06-23 9:57 ` [PATCH v6 1/9] dt-bindings: arm: fsl: add i.MX91 11x11 evk board Joy Zou 2025-06-23 9:57 ` [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 9:57 ` [PATCH v6 4/9] arm64: dts: imx91: add i.MX91 dtsi support Joy Zou ` (6 subsequent siblings) 9 siblings, 0 replies; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong The design of i.MX91 platform is very similar to i.MX93 and only some small differences. If the imx91.dtsi include the imx93.dtsi, each add to imx93.dtsi requires an remove in imx91.dtsi for this unique to i.MX93, e.g. NPU. The i.MX91 isn't the i.MX93 subset, if the imx93.dtsi include the imx91.dtsi, the same problem will occur. Common + delta is better than common - delta, so add imx91_93_common.dtsi for i.MX91 and i.MX93, then the imx93.dtsi and imx91.dtsi will include the imx91_93_common.dtsi. Rename imx93.dtsi to imx91_93_common.dtsi and move i.MX93 specific part from imx91_93_common.dtsi to imx93.dtsi. Signed-off-by: Joy Zou <joy.zou@nxp.com> --- Changes for v6: 1. merge rename imx93.dtsi to imx91_93_common.dtsi and move i.MX93 specific part from imx91_93_common.dtsi to imx93.dtsi patch. 2. restore copyright time and add modification time. 3. remove unused map0 label in imx91_93_common.dtsi. --- .../{imx93.dtsi => imx91_93_common.dtsi} | 140 +- arch/arm64/boot/dts/freescale/imx93.dtsi | 1512 ++--------------- 2 files changed, 163 insertions(+), 1489 deletions(-) copy arch/arm64/boot/dts/freescale/{imx93.dtsi => imx91_93_common.dtsi} (92%) rewrite arch/arm64/boot/dts/freescale/imx93.dtsi (97%) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi similarity index 92% copy from arch/arm64/boot/dts/freescale/imx93.dtsi copy to arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index 64cd0776b43d..fd303dbe7a01 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2022 NXP + * Copyright 2022,2025 NXP */ #include <dt-bindings/clock/imx93-clock.h> @@ -52,7 +52,7 @@ aliases { spi7 = &lpspi8; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; @@ -77,58 +77,6 @@ A55_0: cpu@0 { enable-method = "psci"; #cooling-cells = <2>; cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - }; - - A55_1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <262144>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <3>; - cache-unified; }; }; @@ -184,44 +132,6 @@ gic: interrupt-controller@48000000 { interrupt-parent = <&gic>; }; - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - cm33: remoteproc-cm33 { - compatible = "fsl,imx93-cm33"; - clocks = <&clk IMX93_CLK_CM33_GATE>; - status = "disabled"; - }; - mqs1: mqs1 { compatible = "fsl,imx93-mqs"; gpr = <&aonmix_ns_gpr>; @@ -307,15 +217,6 @@ aonmix_ns_gpr: syscon@44210000 { reg = <0x44210000 0x1000>; }; - mu1: mailbox@44230000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x44230000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU1_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - system_counter: timer@44290000 { compatible = "nxp,sysctr-timer"; reg = <0x44290000 0x30000>; @@ -519,14 +420,6 @@ src: system-controller@44460000 { #size-cells = <1>; ranges; - mlmix: power-domain@44461800 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44461800 0x400>, <0x44464800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_ML_APB>, - <&clk IMX93_CLK_ML>; - }; - mediamix: power-domain@44462400 { compatible = "fsl,imx93-src-slice"; reg = <0x44462400 0x400>, <0x44465800 0x400>; @@ -542,26 +435,6 @@ clock-controller@44480000 { #clock-cells = <1>; }; - tmu: tmu@44482000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x44482000 0x1000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_TMC_GATE>; - little-endian; - fsl,tmu-range = <0x800000da 0x800000e9 - 0x80000102 0x8000012a - 0x80000166 0x800001a7 - 0x800001b6>; - fsl,tmu-calibration = <0x00000000 0x0000000e - 0x00000001 0x00000029 - 0x00000002 0x00000056 - 0x00000003 0x000000a2 - 0x00000004 0x00000116 - 0x00000005 0x00000195 - 0x00000006 0x000001b2>; - #thermal-sensor-cells = <1>; - }; - micfil: micfil@44520000 { compatible = "fsl,imx93-micfil"; reg = <0x44520000 0x10000>; @@ -677,15 +550,6 @@ wakeupmix_gpr: syscon@42420000 { reg = <0x42420000 0x1000>; }; - mu2: mailbox@42440000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x42440000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU2_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - wdog3: watchdog@42490000 { compatible = "fsl,imx93-wdt"; reg = <0x42490000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi dissimilarity index 97% index 64cd0776b43d..7b27012dfcb5 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1,1351 +1,161 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 NXP - */ - -#include <dt-bindings/clock/imx93-clock.h> -#include <dt-bindings/dma/fsl-edma.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/fsl,imx93-power.h> -#include <dt-bindings/thermal/thermal.h> - -#include "imx93-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - i2c3 = &lpi2c4; - i2c4 = &lpi2c5; - i2c5 = &lpi2c6; - i2c6 = &lpi2c7; - i2c7 = &lpi2c8; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - serial5 = &lpuart6; - serial6 = &lpuart7; - serial7 = &lpuart8; - spi0 = &lpspi1; - spi1 = &lpspi2; - spi2 = &lpspi3; - spi3 = &lpspi4; - spi4 = &lpspi5; - spi5 = &lpspi6; - spi6 = &lpspi7; - spi7 = &lpspi8; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_pd_wait: cpu-pd-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <10000>; - exit-latency-us = <7000>; - min-residency-us = <27000>; - wakeup-latency-us = <15000>; - }; - }; - - A55_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - }; - - A55_1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <262144>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <3>; - cache-unified; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48000000 { - compatible = "arm,gic-v3"; - reg = <0 0x48000000 0 0x10000>, - <0 0x48040000 0 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - cm33: remoteproc-cm33 { - compatible = "fsl,imx93-cm33"; - clocks = <&clk IMX93_CLK_CM33_GATE>; - status = "disabled"; - }; - - mqs1: mqs1 { - compatible = "fsl,imx93-mqs"; - gpr = <&aonmix_ns_gpr>; - status = "disabled"; - }; - - mqs2: mqs2 { - compatible = "fsl,imx93-mqs"; - gpr = <&wakeupmix_gpr>; - status = "disabled"; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x80000000>, - <0x28000000 0x0 0x28000000 0x10000000>; - - aips1: bus@44000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x44000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edma1: dma-controller@44000000 { - compatible = "fsl,imx93-edma3"; - reg = <0x44000000 0x200000>; - #dma-cells = <3>; - dma-channels = <31>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved - <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 - <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow - <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 - <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 - <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow - <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM - <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1 - clocks = <&clk IMX93_CLK_EDMA1_GATE>; - clock-names = "dma"; - }; - - aonmix_ns_gpr: syscon@44210000 { - compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; - reg = <0x44210000 0x1000>; - }; - - mu1: mailbox@44230000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x44230000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU1_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@44290000 { - compatible = "nxp,sysctr-timer"; - reg = <0x44290000 0x30000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc_24m>; - clock-names = "per"; - nxp,no-divider; - }; - - wdog1: watchdog@442d0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x442d0000 0x10000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG1_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog2: watchdog@442e0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x442e0000 0x10000>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG2_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - tpm1: pwm@44310000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44310000 0x1000>; - clocks = <&clk IMX93_CLK_TPM1_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm2: pwm@44320000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44320000 0x10000>; - clocks = <&clk IMX93_CLK_TPM2_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i3c1: i3c@44330000 { - compatible = "silvaco,i3c-master-v1"; - reg = <0x44330000 0x10000>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <3>; - #size-cells = <0>; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_I3C1_GATE>, - <&clk IMX93_CLK_I3C1_SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; - status = "disabled"; - }; - - lpi2c1: i2c@44340000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44340000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c2: i2c@44350000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44350000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi1: spi@44360000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44360000 0x10000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi2: spi@44370000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44370000 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44380000 0x1000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg"; - dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44390000 0x1000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART2_GATE>; - clock-names = "ipg"; - dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - flexcan1: can@443a0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x443a0000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_CAN1_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; - status = "disabled"; - }; - - sai1: sai@443b0000 { - compatible = "fsl,imx93-sai"; - reg = <0x443b0000 0x10000>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - iomuxc: pinctrl@443c0000 { - compatible = "fsl,imx93-iomuxc"; - reg = <0x443c0000 0x10000>; - status = "okay"; - }; - - bbnsm: bbnsm@44440000 { - compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; - reg = <0x44440000 0x10000>; - - bbnsm_rtc: rtc { - compatible = "nxp,imx93-bbnsm-rtc"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - }; - - bbnsm_pwrkey: pwrkey { - compatible = "nxp,imx93-bbnsm-pwrkey"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - linux,code = <KEY_POWER>; - }; - }; - - clk: clock-controller@44450000 { - compatible = "fsl,imx93-ccm"; - reg = <0x44450000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; - clock-names = "osc_32k", "osc_24m", "clk_ext1"; - assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <393216000>; - status = "okay"; - }; - - src: system-controller@44460000 { - compatible = "fsl,imx93-src", "syscon"; - reg = <0x44460000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mlmix: power-domain@44461800 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44461800 0x400>, <0x44464800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_ML_APB>, - <&clk IMX93_CLK_ML>; - }; - - mediamix: power-domain@44462400 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44462400 0x400>, <0x44465800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_APB>; - }; - }; - - clock-controller@44480000 { - compatible = "fsl,imx93-anatop"; - reg = <0x44480000 0x2000>; - #clock-cells = <1>; - }; - - tmu: tmu@44482000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x44482000 0x1000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_TMC_GATE>; - little-endian; - fsl,tmu-range = <0x800000da 0x800000e9 - 0x80000102 0x8000012a - 0x80000166 0x800001a7 - 0x800001b6>; - fsl,tmu-calibration = <0x00000000 0x0000000e - 0x00000001 0x00000029 - 0x00000002 0x00000056 - 0x00000003 0x000000a2 - 0x00000004 0x00000116 - 0x00000005 0x00000195 - 0x00000006 0x000001b2>; - #thermal-sensor-cells = <1>; - }; - - micfil: micfil@44520000 { - compatible = "fsl,imx93-micfil"; - reg = <0x44520000 0x10000>; - interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_PDM_IPG>, - <&clk IMX93_CLK_PDM_GATE>, - <&clk IMX93_CLK_AUDIO_PLL>; - clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; - dmas = <&edma1 29 0 5>; - dma-names = "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - adc1: adc@44530000 { - compatible = "nxp,imx93-adc"; - reg = <0x44530000 0x10000>; - interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ADC1_GATE>; - clock-names = "ipg"; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; - - aips2: bus@42000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edma2: dma-controller@42000000 { - compatible = "fsl,imx93-edma4"; - reg = <0x42000000 0x210000>; - #dma-cells = <3>; - dma-channels = <64>; - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_EDMA2_GATE>; - clock-names = "dma"; - }; - - wakeupmix_gpr: syscon@42420000 { - compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; - reg = <0x42420000 0x1000>; - }; - - mu2: mailbox@42440000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x42440000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU2_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - wdog3: watchdog@42490000 { - compatible = "fsl,imx93-wdt"; - reg = <0x42490000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG3_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog4: watchdog@424a0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x424a0000 0x10000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG4_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog5: watchdog@424b0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x424b0000 0x10000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG5_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - tpm3: pwm@424e0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424e0000 0x1000>; - clocks = <&clk IMX93_CLK_TPM3_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm4: pwm@424f0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424f0000 0x10000>; - clocks = <&clk IMX93_CLK_TPM4_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: pwm@42500000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42500000 0x10000>; - clocks = <&clk IMX93_CLK_TPM5_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm6: pwm@42510000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42510000 0x10000>; - clocks = <&clk IMX93_CLK_TPM6_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i3c2: i3c@42520000 { - compatible = "silvaco,i3c-master-v1"; - reg = <0x42520000 0x10000>; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <3>; - #size-cells = <0>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_I3C2_GATE>, - <&clk IMX93_CLK_I3C2_SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; - status = "disabled"; - }; - - lpi2c3: i2c@42530000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42530000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c4: i2c@42540000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42540000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi3: spi@42550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42550000 0x10000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi4: spi@42560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42560000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42570000 0x1000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART3_GATE>; - clock-names = "ipg"; - dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42580000 0x1000>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART4_GATE>; - clock-names = "ipg"; - dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42590000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART5_GATE>; - clock-names = "ipg"; - dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x425a0000 0x1000>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART6_GATE>; - clock-names = "ipg"; - dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - flexcan2: can@425b0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x425b0000 0x10000>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_CAN2_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; - status = "disabled"; - }; - - flexspi1: spi@425e0000 { - compatible = "nxp,imx8mm-fspi"; - reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, - <&clk IMX93_CLK_FLEXSPI1_GATE>; - clock-names = "fspi_en", "fspi"; - assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - status = "disabled"; - }; - - sai2: sai@42650000 { - compatible = "fsl,imx93-sai"; - reg = <0x42650000 0x10000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - sai3: sai@42660000 { - compatible = "fsl,imx93-sai"; - reg = <0x42660000 0x10000>; - interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - xcvr: xcvr@42680000 { - compatible = "fsl,imx93-xcvr"; - reg = <0x42680000 0x800>, - <0x42680800 0x400>, - <0x42680c00 0x080>, - <0x42680e00 0x080>; - reg-names = "ram", "regs", "rxfifo", "txfifo"; - interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_SPDIF_IPG>, - <&clk IMX93_CLK_SPDIF_GATE>, - <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_AUD_XCVR_GATE>; - clock-names = "ipg", "phy", "spba", "pll_ipg"; - dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42690000 0x1000>; - interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART7_GATE>; - clock-names = "ipg"; - dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x426a0000 0x1000>; - interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART8_GATE>; - clock-names = "ipg"; - dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpi2c5: i2c@426b0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c6: i2c@426c0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426c0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c7: i2c@426d0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426d0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c8: i2c@426e0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426e0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi5: spi@426f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x426f0000 0x10000>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi6: spi@42700000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42700000 0x10000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi7: spi@42710000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42710000 0x10000>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi8: spi@42720000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42720000 0x10000>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - }; - - aips3: bus@42800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42800000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usdhc1: mmc@42850000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42850000 0x10000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC1_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - usdhc2: mmc@42860000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42860000 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC2_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - fec: ethernet@42890000 { - compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x42890000 0x10000>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <250000000>, <50000000>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; - nvmem-cells = <ð_mac1>; - nvmem-cell-names = "mac-address"; - status = "disabled"; - }; - - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_ENET_QOS_GATE>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - snps,clk-csr = <6>; - nvmem-cells = <ð_mac2>; - nvmem-cell-names = "mac-address"; - status = "disabled"; - }; - - usdhc3: mmc@428b0000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x428b0000 0x10000>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC3_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC3>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - }; - - gpio2: gpio@43810000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43810000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO2_GATE>, - <&clk IMX93_CLK_GPIO2_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 4 30>; - }; - - gpio3: gpio@43820000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43820000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO3_GATE>, - <&clk IMX93_CLK_GPIO3_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, - <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; - }; - - gpio4: gpio@43830000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43830000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO4_GATE>, - <&clk IMX93_CLK_GPIO4_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; - }; - - gpio1: gpio@47400000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x47400000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO1_GATE>, - <&clk IMX93_CLK_GPIO1_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 92 16>; - }; - - ocotp: efuse@47510000 { - compatible = "fsl,imx93-ocotp", "syscon"; - reg = <0x47510000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - eth_mac1: mac-address@4ec { - reg = <0x4ec 0x6>; - }; - - eth_mac2: mac-address@4f2 { - reg = <0x4f2 0x6>; - }; - - }; - - s4muap: mailbox@47520000 { - compatible = "fsl,imx93-mu-s4"; - reg = <0x47520000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - #mbox-cells = <2>; - }; - - media_blk_ctrl: system-controller@4ac10000 { - compatible = "fsl,imx93-media-blk-ctrl", "syscon"; - reg = <0x4ac10000 0x10000>; - power-domains = <&mediamix>; - clocks = <&clk IMX93_CLK_MEDIA_APB>, - <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_DISP_PIX>, - <&clk IMX93_CLK_CAM_PIX>, - <&clk IMX93_CLK_PXP_GATE>, - <&clk IMX93_CLK_LCDIF_GATE>, - <&clk IMX93_CLK_ISI_GATE>, - <&clk IMX93_CLK_MIPI_CSI_GATE>, - <&clk IMX93_CLK_MIPI_DSI_GATE>; - clock-names = "apb", "axi", "nic", "disp", "cam", - "pxp", "lcdif", "isi", "csi", "dsi"; - #power-domain-cells = <1>; - status = "disabled"; - }; - - usbotg1: usb@4c100000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c100000 0x200>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@4c100200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c100200 0x200>; - #index-cells = <1>; - }; - - usbotg2: usb@4c200000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c200000 0x200>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@4c200200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c200200 0x200>; - #index-cells = <1>; - }; - - memory-controller@4e300000 { - compatible = "nxp,imx9-memory-controller"; - reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; - reg-names = "ctrl", "inject"; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - little-endian; - }; - - ddr-pmu@4e300dc0 { - compatible = "fsl,imx93-ddr-pmu"; - reg = <0x4e300dc0 0x200>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - }; - }; -}; +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022,2025 NXP + */ + +#include "imx91_93_common.dtsi" + +/{ + cm33: remoteproc-cm33 { + compatible = "fsl,imx93-cm33"; + clocks = <&clk IMX93_CLK_CM33_GATE>; + status = "disabled"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&aips1 { + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU1_B_GATE>; + #mbox-cells = <2>; + status = "disabled"; + }; + + tmu: tmu@44482000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x44482000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + #thermal-sensor-cells = <1>; + little-endian; + fsl,tmu-range = <0x800000da 0x800000e9 + 0x80000102 0x8000012a + 0x80000166 0x800001a7 + 0x800001b6>; + fsl,tmu-calibration = <0x00000000 0x0000000e + 0x00000001 0x00000029 + 0x00000002 0x00000056 + 0x00000003 0x000000a2 + 0x00000004 0x00000116 + 0x00000005 0x00000195 + 0x00000006 0x000001b2>; + }; +}; + +&aips2 { + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU2_B_GATE>; + #mbox-cells = <2>; + status = "disabled"; + }; +}; + +&cpus { + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <3>; + cache-unified; + }; +}; + +&src { + mlmix: power-domain@44461800 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44461800 0x400>, <0x44464800 0x400>; + clocks = <&clk IMX93_CLK_ML_APB>, + <&clk IMX93_CLK_ML>; + #power-domain-cells = <0>; + }; +}; -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 4/9] arm64: dts: imx91: add i.MX91 dtsi support 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou ` (2 preceding siblings ...) 2025-06-23 9:57 ` [PATCH v6 3/9] arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 9:57 ` [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support Joy Zou ` (5 subsequent siblings) 9 siblings, 0 replies; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong The i.MX 91 family features an Arm Cortex-A55 running at up to 1.4GHz, support for modern LPDDR4 memory to enable platform longevity, along with a rich set of peripherals targeting medical, industrial and consumer IoT market segments. The mainly difference between i.MX91 and i.MX93 is as follows: - i.MX91 removed some clocks and modified the names of some clocks. - i.MX91 only has one A core. - i.MX91 has different pinmux. - i.MX91 has updated to new temperature sensor same with i.MX95. Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Signed-off-by: Joy Zou <joy.zou@nxp.com> --- Changes for v6: 1. remove tmu related node due to dtb-check warning. Changes for v5: 1. modify the imx91.dtsi to use imx91_93_common.dtsi. Changes for v4: 1. modify the references in imx91.dtsi. 2. modify the code alignment. Changes for v2: 1. change ddr node pmu compatible. 2. remove mu1 and mu2. 3. change iomux node compatible and enable 91 pinctr. 4. refine commit message. 5. change hex to lowercase in pinfunc.h. 6. ordering nodes with the dt-format tool --- arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx91.dtsi | 71 ++ .../boot/dts/freescale/imx91_93_common.dtsi | 2 +- 3 files changed, 842 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h new file mode 100644 index 000000000000..3e19945f5ce3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h @@ -0,0 +1,770 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DTS_IMX91_PINFUNC_H +#define __DTS_IMX91_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00 +#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00 +#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00 + +#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00 + +#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00 + +#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00 + +#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01 +#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00 +#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00 + +#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01 +#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00 +#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00 + +#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01 +#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00 +#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00 + +#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00 +#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00 + +#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01 +#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00 + +#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00 +#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01 +#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00 + +#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00 +#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00 +#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00 + +#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00 +#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00 + +#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01 +#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00 + +#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01 +#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00 + +#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00 +#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00 + +#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00 +#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00 + +#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00 +#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01 +#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00 + +#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00 +#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01 +#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00 + +#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00 +#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00 + +#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00 +#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00 + +#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01 +#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00 +#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00 +#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00 + +#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00 + +#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00 + +#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01 +#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01 +#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01 +#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00 + +#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01 + +#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00 +#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00 +#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01 +#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00 + +#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00 +#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01 +#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00 + +#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00 +#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00 + +#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00 +#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01 +#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00 + +#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00 +#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01 +#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01 +#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00 + +#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00 +#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01 +#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01 +#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00 + +#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01 +#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01 +#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00 +#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00 + +#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00 +#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01 + +#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00 +#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00 + +#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00 +#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00 + +#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00 + +#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02 +#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00 + +#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00 + +#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01 +#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00 + +#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00 + +#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00 + +#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00 + +#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01 +#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01 +#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00 +#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00 +#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00 +#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00 + +#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01 + +#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01 + +#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01 +#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00 + +#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01 + +#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01 + +#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01 +#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01 + +#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01 + +#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01 + +#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01 + +#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01 + +#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01 +#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01 + +#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01 +#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01 + +#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01 +#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01 + +#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02 +#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00 + +#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01 +#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01 + +#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01 +#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01 + +#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01 +#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01 + +#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01 +#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01 + +#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00 +#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00 + +#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01 +#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00 + +#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01 +#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00 + +#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01 +#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00 + +#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01 +#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00 + +#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01 +#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00 + +#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01 +#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00 +#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00 +#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01 +#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00 +#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00 +#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00 + +#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01 +#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00 +#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01 +#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01 +#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00 +#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00 +#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01 +#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00 +#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01 +#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01 +#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00 +#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01 +#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01 +#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01 +#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01 +#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01 +#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01 +#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01 +#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01 +#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01 +#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01 + +#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01 +#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01 +#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00 +#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01 + +#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01 +#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01 +#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00 +#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03 +#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01 +#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00 +#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01 +#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00 +#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01 +#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01 +#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00 +#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00 +#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01 +#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01 +#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00 +#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00 + +#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02 +#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00 + +#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02 +#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00 + +#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01 +#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00 +#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00 +#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00 + +#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01 +#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01 +#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00 +#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02 +#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00 +#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01 +#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00 +#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02 +#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00 +#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01 +#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01 +#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02 +#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00 +#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00 +#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01 +#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00 +#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02 +#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00 +#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00 +#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02 + +#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00 +#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00 +#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00 +#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00 +#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00 + +#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01 + +#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01 + +#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01 +#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01 +#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01 +#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02 +#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01 +#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00 +#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01 + +#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02 +#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01 +#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00 + +#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00 +#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00 +#endif /* __DTS_IMX91_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi new file mode 100644 index 000000000000..4d8300b2a7bc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include "imx91-pinfunc.h" +#include "imx91_93_common.dtsi" + +&clk { + compatible = "fsl,imx91-ccm"; +}; + +&ddr_pmu { + compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu"; +}; + +&eqos { + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&fec { + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>, + <&clk IMX93_CLK_DUMMY>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&i3c1 { + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&i3c2 { + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&iomuxc { + compatible = "fsl,imx91-iomuxc"; +}; + +&media_blk_ctrl { + compatible = "fsl,imx91-media-blk-ctrl", "syscon"; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "lcdif", "isi", "csi"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index fd303dbe7a01..2a2ed0266c1e 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -1206,7 +1206,7 @@ memory-controller@4e300000 { little-endian; }; - ddr-pmu@4e300dc0 { + ddr_pmu: ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou ` (3 preceding siblings ...) 2025-06-23 9:57 ` [PATCH v6 4/9] arm64: dts: imx91: add i.MX91 dtsi support Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 14:57 ` Frank Li 2025-06-23 18:17 ` Andrew Lunn 2025-06-23 9:57 ` [PATCH v6 6/9] arm64: dts: freescale: move aliases from imx91_93_common.dtsi to board dts Joy Zou ` (4 subsequent siblings) 9 siblings, 2 replies; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong Add i.MX91 11x11 EVK board support. - Enable ADC1. - Enable lpuart1 and lpuart5. - Enable network eqos and fec. - Enable I2C bus and children nodes under I2C bus. - Enable USB and related nodes. - Enable uSDHC1 and uSDHC2. - Enable Watchdog3. Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Signed-off-by: Joy Zou <joy.zou@nxp.com> --- Changes for v6: 1. remove unused regulators and pinctrl settings. Changes for v5: 1. change node name codec and lsm6dsm into common name audio-codec and inertial-meter, and add BT compatible string. Changes for v4: 1. remove pmic node unused newline. 2. delete the tcpc@50 status property. 3. align pad hex values. Changes for v3: 1. format imx91-11x11-evk.dts with the dt-format tool. 2. add lpi2c1 node. --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-11x11-evk.dts | 666 ++++++++++++++++++ 2 files changed, 667 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0b473a23d120..fbedb3493c09 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -315,6 +315,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts new file mode 100644 index 000000000000..0acd97ed14da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; + model = "NXP i.MX91 11X11 EVK board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + rtc0 = &bbnsm_rtc; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-pwr"; + gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x40000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + eee-broken-1000t; + realtek,clkout-disable; + }; + }; +}; + +/* + * When add, delete or change any target device setting in &lpi2c1, + * please synchronize the changes to the &i3c1 bus in imx91-11x11-evk-i3c.dts. + */ +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; + + audio_codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + inertial-meter@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio3>; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + + regulators { + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2237500>; + regulator-min-microvolt = <650000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-name = "LDO1"; + }; + + ldo4: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO4"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + #gpio-cells = <2>; + gpio-controller; + #pwm-cells = <3>; + gpio-reserved-ranges = <5 1>; + + exp-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + status = "okay"; + + typec2_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + status = "okay"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + +}; -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support 2025-06-23 9:57 ` [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support Joy Zou @ 2025-06-23 14:57 ` Frank Li 2025-06-23 18:17 ` Andrew Lunn 1 sibling, 0 replies; 21+ messages in thread From: Frank Li @ 2025-06-23 14:57 UTC (permalink / raw) To: Joy Zou Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, ye.li, ping.bai, aisheng.dong On Mon, Jun 23, 2025 at 05:57:28PM +0800, Joy Zou wrote: > Add i.MX91 11x11 EVK board support. > - Enable ADC1. > - Enable lpuart1 and lpuart5. > - Enable network eqos and fec. > - Enable I2C bus and children nodes under I2C bus. > - Enable USB and related nodes. > - Enable uSDHC1 and uSDHC2. > - Enable Watchdog3. > > Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> > Signed-off-by: Joy Zou <joy.zou@nxp.com> > --- > Changes for v6: > 1. remove unused regulators and pinctrl settings. > > Changes for v5: > 1. change node name codec and lsm6dsm into common name audio-codec and > inertial-meter, and add BT compatible string. > > Changes for v4: > 1. remove pmic node unused newline. > 2. delete the tcpc@50 status property. > 3. align pad hex values. > > Changes for v3: > 1. format imx91-11x11-evk.dts with the dt-format tool. > 2. add lpi2c1 node. > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/imx91-11x11-evk.dts | 666 ++++++++++++++++++ > 2 files changed, 667 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 0b473a23d120..fbedb3493c09 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -315,6 +315,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb > > imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo > dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts > new file mode 100644 > index 000000000000..0acd97ed14da > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts > @@ -0,0 +1,666 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2025 NXP > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/usb/pd.h> > +#include "imx91.dtsi" > + > +/ { > + compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; > + model = "NXP i.MX91 11X11 EVK board"; > + > + aliases { > + ethernet0 = &fec; > + ethernet1 = &eqos; > + rtc0 = &bbnsm_rtc; > + }; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + reg_vref_1v8: regulator-adc-vref { > + compatible = "regulator-fixed"; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <1800000>; > + regulator-name = "vref_1v8"; > + }; > + > + reg_audio_pwr: regulator-audio-pwr { > + compatible = "regulator-fixed"; > + regulator-always-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "audio-pwr"; > + gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + off-on-delay-us = <12000>; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + pinctrl-names = "default"; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + regulator-name = "VSD_3V3"; > + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reserved-memory { > + ranges; > + #address-cells = <2>; > + #size-cells = <2>; > + > + linux,cma { > + compatible = "shared-dma-pool"; > + alloc-ranges = <0 0x80000000 0 0x40000000>; > + reusable; > + size = <0 0x10000000>; > + linux,cma-default; > + }; > + }; > +}; > + > +&adc1 { > + vref-supply = <®_vref_1v8>; > + status = "okay"; > +}; > + > +&eqos { > + phy-handle = <ðphy1>; > + phy-mode = "rgmii-id"; > + pinctrl-0 = <&pinctrl_eqos>; > + pinctrl-1 = <&pinctrl_eqos_sleep>; > + pinctrl-names = "default", "sleep"; > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <5000000>; > + > + ethphy1: ethernet-phy@1 { > + reg = <1>; > + realtek,clkout-disable; > + }; > + }; > +}; > + > +&fec { > + phy-handle = <ðphy2>; > + phy-mode = "rgmii-id"; > + pinctrl-0 = <&pinctrl_fec>; > + pinctrl-1 = <&pinctrl_fec_sleep>; > + pinctrl-names = "default", "sleep"; > + fsl,magic-packet; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <5000000>; > + > + ethphy2: ethernet-phy@2 { > + reg = <2>; > + eee-broken-1000t; > + realtek,clkout-disable; > + }; > + }; > +}; > + > +/* > + * When add, delete or change any target device setting in &lpi2c1, > + * please synchronize the changes to the &i3c1 bus in imx91-11x11-evk-i3c.dts. > + */ Please remove this unused comments, there are not imx91-11x11-evk-i3c.dts yet. > +&lpi2c1 { > + clock-frequency = <400000>; > + pinctrl-0 = <&pinctrl_lpi2c1>; > + pinctrl-names = "default"; > + status = "okay"; > + > + audio_codec: wm8962@1a { > + compatible = "wlf,wm8962"; > + reg = <0x1a>; > + clocks = <&clk IMX93_CLK_SAI3_GATE>; > + AVDD-supply = <®_audio_pwr>; > + CPVDD-supply = <®_audio_pwr>; > + DBVDD-supply = <®_audio_pwr>; > + DCVDD-supply = <®_audio_pwr>; > + MICVDD-supply = <®_audio_pwr>; > + PLLVDD-supply = <®_audio_pwr>; > + SPKVDD1-supply = <®_audio_pwr>; > + SPKVDD2-supply = <®_audio_pwr>; > + gpio-cfg = < > + 0x0000 /* 0:Default */ > + 0x0000 /* 1:Default */ > + 0x0000 /* 2:FN_DMICCLK */ > + 0x0000 /* 3:Default */ > + 0x0000 /* 4:FN_DMICCDAT */ > + 0x0000 /* 5:Default */ > + >; > + }; > + > + inertial-meter@6a { > + compatible = "st,lsm6dso"; > + reg = <0x6a>; > + }; > +}; > + > +&lpi2c2 { > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <400000>; > + pinctrl-0 = <&pinctrl_lpi2c2>; > + pinctrl-names = "default"; > + status = "okay"; > + > + pcal6524: gpio@22 { > + compatible = "nxp,pcal6524"; > + reg = <0x22>; > + #interrupt-cells = <2>; > + interrupt-controller; > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > + #gpio-cells = <2>; > + gpio-controller; > + interrupt-parent = <&gpio3>; > + pinctrl-0 = <&pinctrl_pcal6524>; > + pinctrl-names = "default"; > + }; > + > + pmic@25 { > + compatible = "nxp,pca9451a"; > + reg = <0x25>; > + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; > + interrupt-parent = <&pcal6524>; > + > + regulators { > + buck1: BUCK1 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <2237500>; > + regulator-min-microvolt = <650000>; > + regulator-name = "BUCK1"; > + regulator-ramp-delay = <3125>; > + }; > + > + buck2: BUCK2 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <2187500>; > + regulator-min-microvolt = <600000>; > + regulator-name = "BUCK2"; > + regulator-ramp-delay = <3125>; > + }; > + > + buck4: BUCK4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3400000>; > + regulator-min-microvolt = <600000>; > + regulator-name = "BUCK4"; > + }; > + > + buck5: BUCK5 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3400000>; > + regulator-min-microvolt = <600000>; > + regulator-name = "BUCK5"; > + }; > + > + buck6: BUCK6 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3400000>; > + regulator-min-microvolt = <600000>; > + regulator-name = "BUCK6"; > + }; > + > + ldo1: LDO1 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <1600000>; > + regulator-name = "LDO1"; > + }; > + > + ldo4: LDO4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <800000>; > + regulator-name = "LDO4"; > + }; > + > + ldo5: LDO5 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <1800000>; > + regulator-name = "LDO5"; > + }; > + }; > + }; > + > + adp5585: io-expander@34 { > + compatible = "adi,adp5585-00", "adi,adp5585"; > + reg = <0x34>; > + #gpio-cells = <2>; > + gpio-controller; > + #pwm-cells = <3>; > + gpio-reserved-ranges = <5 1>; > + > + exp-sel-hog { > + gpio-hog; > + gpios = <4 GPIO_ACTIVE_HIGH>; > + output-low; > + }; > + }; > +}; > + > +&lpi2c3 { > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <400000>; > + pinctrl-0 = <&pinctrl_lpi2c3>; > + pinctrl-names = "default"; > + status = "okay"; > + > + ptn5110: tcpc@50 { > + compatible = "nxp,ptn5110", "tcpci"; > + reg = <0x50>; > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > + interrupt-parent = <&gpio3>; > + > + typec1_con: connector { > + compatible = "usb-c-connector"; > + data-role = "dual"; > + label = "USB-C"; > + op-sink-microwatt = <15000000>; > + power-role = "dual"; > + self-powered; > + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) > + PDO_VAR(5000, 20000, 3000)>; > + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; > + try-power-role = "sink"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + typec1_dr_sw: endpoint { > + remote-endpoint = <&usb1_drd_sw>; > + }; > + }; > + }; > + }; > + }; > + > + ptn5110_2: tcpc@51 { > + compatible = "nxp,ptn5110", "tcpci"; > + reg = <0x51>; > + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; > + interrupt-parent = <&gpio3>; > + status = "okay"; > + > + typec2_con: connector { > + compatible = "usb-c-connector"; > + data-role = "dual"; > + label = "USB-C"; > + op-sink-microwatt = <15000000>; > + power-role = "dual"; > + self-powered; > + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) > + PDO_VAR(5000, 20000, 3000)>; > + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; > + try-power-role = "sink"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + typec2_dr_sw: endpoint { > + remote-endpoint = <&usb2_drd_sw>; > + }; > + }; > + }; > + }; > + }; > + > + pcf2131: rtc@53 { > + compatible = "nxp,pcf2131"; > + reg = <0x53>; > + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; > + interrupt-parent = <&pcal6524>; > + status = "okay"; > + }; > +}; > + > +&lpuart1 { > + pinctrl-0 = <&pinctrl_uart1>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&lpuart5 { > + pinctrl-0 = <&pinctrl_uart5>; > + pinctrl-names = "default"; > + status = "okay"; > + > + bluetooth { > + compatible = "nxp,88w8987-bt"; > + }; > +}; > + > +&usbotg1 { > + adp-disable; > + disable-over-current; > + dr_mode = "otg"; > + hnp-disable; > + srp-disable; > + usb-role-switch; > + samsung,picophy-dc-vol-level-adjust = <7>; > + samsung,picophy-pre-emp-curr-control = <3>; > + status = "okay"; > + > + port { > + usb1_drd_sw: endpoint { > + remote-endpoint = <&typec1_dr_sw>; > + }; > + }; > +}; > + > +&usbotg2 { > + adp-disable; > + disable-over-current; > + dr_mode = "otg"; > + hnp-disable; > + srp-disable; > + usb-role-switch; > + samsung,picophy-dc-vol-level-adjust = <7>; > + samsung,picophy-pre-emp-curr-control = <3>; > + status = "okay"; > + > + port { > + usb2_drd_sw: endpoint { > + remote-endpoint = <&typec2_dr_sw>; > + }; > + }; > +}; > + > +&usdhc1 { > + bus-width = <8>; > + non-removable; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + status = "okay"; > +}; > + > +&usdhc2 { > + bus-width = <4>; > + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; > + no-mmc; > + no-sdio; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > + vmmc-supply = <®_usdhc2_vmmc>; > + status = "okay"; > +}; > + > +&wdog3 { > + fsl,ext-reset-output; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl_eqos: eqosgrp { > + fsl,pins = < > + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e > + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e > + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e > + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e > + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e > + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e > + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe > + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e > + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e > + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e > + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e > + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e > + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe > + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e > + >; > + }; > + > + pinctrl_eqos_sleep: eqossleepgrp { > + fsl,pins = < > + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e > + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e > + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e > + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e > + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e > + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e > + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e > + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e > + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e > + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e > + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e > + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e > + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e > + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e > + >; > + }; > + > + pinctrl_fec: fecgrp { > + fsl,pins = < > + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e > + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e > + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e > + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e > + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e > + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e > + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe > + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e > + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e > + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e > + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e > + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e > + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe > + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e Can you align all these number to the same column. Frank > + >; > + }; > + > + pinctrl_fec_sleep: fecsleepgrp { > + fsl,pins = < > + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e > + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e > + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e > + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e > + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e > + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e > + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e > + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e > + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e > + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e > + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e > + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e > + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e > + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e > + >; > + }; > + > + pinctrl_lpi2c1: lpi2c1grp { > + fsl,pins = < > + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e > + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e > + >; > + }; > + > + pinctrl_lpi2c2: lpi2c2grp { > + fsl,pins = < > + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e > + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e > + >; > + }; > + > + pinctrl_lpi2c3: lpi2c3grp { > + fsl,pins = < > + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e > + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e > + >; > + }; > + > + pinctrl_pcal6524: pcal6524grp { > + fsl,pins = < > + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e > + >; > + }; > + > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > + fsl,pins = < > + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e > + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e > + >; > + }; > + > + pinctrl_uart5: uart5grp { > + fsl,pins = < > + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e > + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e > + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e > + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e > + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e > + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e > + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e > + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e > + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e > + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e > + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e > + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e > + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e > + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe > + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe > + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe > + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe > + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe > + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe > + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe > + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe > + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe > + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe > + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 > + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 > + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 > + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 > + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 > + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 > + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 > + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 > + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 > + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 > + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = < > + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e > + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e > + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e > + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e > + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e > + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e > + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = < > + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe > + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe > + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe > + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe > + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe > + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe > + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e > + >; > + }; > + > + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { > + fsl,pins = < > + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 > + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 > + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 > + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 > + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 > + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 > + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_sleep: usdhc2sleepgrp { > + fsl,pins = < > + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e > + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e > + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e > + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e > + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e > + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e > + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e > + >; > + }; > + > +}; > -- > 2.37.1 > ^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support 2025-06-23 9:57 ` [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support Joy Zou 2025-06-23 14:57 ` Frank Li @ 2025-06-23 18:17 ` Andrew Lunn 1 sibling, 0 replies; 21+ messages in thread From: Andrew Lunn @ 2025-06-23 18:17 UTC (permalink / raw) To: Joy Zou Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong > +&eqos { > + phy-handle = <ðphy1>; > + phy-mode = "rgmii-id"; > + pinctrl-0 = <&pinctrl_eqos>; > + pinctrl-1 = <&pinctrl_eqos_sleep>; > + pinctrl-names = "default", "sleep"; > + status = "okay"; > + > + mdio { > + compatible = "snps,dwmac-mdio"; > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <5000000>; > + > + ethphy1: ethernet-phy@1 { > + reg = <1>; > + realtek,clkout-disable; > + }; > + }; > +}; > + > +&fec { > + phy-handle = <ðphy2>; > + phy-mode = "rgmii-id"; > + pinctrl-0 = <&pinctrl_fec>; > + pinctrl-1 = <&pinctrl_fec_sleep>; > + pinctrl-names = "default", "sleep"; > + fsl,magic-packet; > + status = "okay"; > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + clock-frequency = <5000000>; > + > + ethphy2: ethernet-phy@2 { > + reg = <2>; > + eee-broken-1000t; > + realtek,clkout-disable; > + }; What is actually broken with EEE? Is it actually the FEC? Andrew ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 6/9] arm64: dts: freescale: move aliases from imx91_93_common.dtsi to board dts 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou ` (4 preceding siblings ...) 2025-06-23 9:57 ` [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 15:10 ` Frank Li 2025-06-23 9:57 ` [PATCH v6 7/9] arm64: defconfig: enable i.MX91 pinctrl Joy Zou ` (3 subsequent siblings) 9 siblings, 1 reply; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong These aliases aren't common and need to drop in imx91_93_common.dtsi. The part aliases are moved from imx91_93_common.dtsi to imx91-11x11-evk.dts and imx93-11x11-evk.dts for the convenience of customers. Signed-off-by: Joy Zou <joy.zou@nxp.com> --- Changes in v6: 1. add new modification for aliases change. --- .../boot/dts/freescale/imx91-11x11-evk.dts | 13 +++++++ .../boot/dts/freescale/imx91_93_common.dtsi | 34 ------------------- .../boot/dts/freescale/imx93-11x11-evk.dts | 19 +++++++++++ 3 files changed, 32 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 0acd97ed14da..52b3f57ba347 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -15,7 +15,20 @@ / { aliases { ethernet0 = &fec; ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; }; chosen { diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index 2a2ed0266c1e..7c8c68151b14 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -18,40 +18,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - i2c3 = &lpi2c4; - i2c4 = &lpi2c5; - i2c5 = &lpi2c6; - i2c6 = &lpi2c7; - i2c7 = &lpi2c8; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - serial5 = &lpuart6; - serial6 = &lpuart7; - serial7 = &lpuart8; - spi0 = &lpspi1; - spi1 = &lpspi2; - spi2 = &lpspi3; - spi3 = &lpspi4; - spi4 = &lpspi5; - spi5 = &lpspi6; - spi6 = &lpspi7; - spi7 = &lpspi8; - }; - cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 8491eb53120e..674b2be900e6 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -12,6 +12,25 @@ / { model = "NXP i.MX93 11X11 EVK board"; compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + chosen { stdout-path = &lpuart1; }; -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v6 6/9] arm64: dts: freescale: move aliases from imx91_93_common.dtsi to board dts 2025-06-23 9:57 ` [PATCH v6 6/9] arm64: dts: freescale: move aliases from imx91_93_common.dtsi to board dts Joy Zou @ 2025-06-23 15:10 ` Frank Li 0 siblings, 0 replies; 21+ messages in thread From: Frank Li @ 2025-06-23 15:10 UTC (permalink / raw) To: Joy Zou Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, ye.li, ping.bai, aisheng.dong On Mon, Jun 23, 2025 at 05:57:29PM +0800, Joy Zou wrote: > These aliases aren't common and need to drop in imx91_93_common.dtsi. > The part aliases are moved from imx91_93_common.dtsi to imx91-11x11-evk.dts > and imx93-11x11-evk.dts for the convenience of customers. > > Signed-off-by: Joy Zou <joy.zou@nxp.com> > --- > Changes in v6: > 1. add new modification for aliases change. > --- > .../boot/dts/freescale/imx91-11x11-evk.dts | 13 +++++++ > .../boot/dts/freescale/imx91_93_common.dtsi | 34 ------------------- > .../boot/dts/freescale/imx93-11x11-evk.dts | 19 +++++++++++ There are 10 imx93 boards at upstream kernel. Krzysztof Kozlowski: In https://lore.kernel.org/imx/4e8f2426-92a1-4c7e-b860-0e10e8dd886c@kernel.org/ You provide comments about "no common aliases". Consider there are 10 imx93 boards. Do you think it is worth to move it to 10 boards' dts file? Frank > 3 files changed, 32 insertions(+), 34 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts > index 0acd97ed14da..52b3f57ba347 100644 > --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts > @@ -15,7 +15,20 @@ / { > aliases { > ethernet0 = &fec; > ethernet1 = &eqos; > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + i2c0 = &lpi2c1; > + i2c1 = &lpi2c2; > + i2c2 = &lpi2c3; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > rtc0 = &bbnsm_rtc; > + serial0 = &lpuart1; > + serial1 = &lpuart2; > + serial2 = &lpuart3; > + serial3 = &lpuart4; > + serial4 = &lpuart5; > }; > > chosen { > diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi > index 2a2ed0266c1e..7c8c68151b14 100644 > --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi > @@ -18,40 +18,6 @@ / { > #address-cells = <2>; > #size-cells = <2>; > > - aliases { > - gpio0 = &gpio1; > - gpio1 = &gpio2; > - gpio2 = &gpio3; > - gpio3 = &gpio4; > - i2c0 = &lpi2c1; > - i2c1 = &lpi2c2; > - i2c2 = &lpi2c3; > - i2c3 = &lpi2c4; > - i2c4 = &lpi2c5; > - i2c5 = &lpi2c6; > - i2c6 = &lpi2c7; > - i2c7 = &lpi2c8; > - mmc0 = &usdhc1; > - mmc1 = &usdhc2; > - mmc2 = &usdhc3; > - serial0 = &lpuart1; > - serial1 = &lpuart2; > - serial2 = &lpuart3; > - serial3 = &lpuart4; > - serial4 = &lpuart5; > - serial5 = &lpuart6; > - serial6 = &lpuart7; > - serial7 = &lpuart8; > - spi0 = &lpspi1; > - spi1 = &lpspi2; > - spi2 = &lpspi3; > - spi3 = &lpspi4; > - spi4 = &lpspi5; > - spi5 = &lpspi6; > - spi6 = &lpspi7; > - spi7 = &lpspi8; > - }; > - > cpus: cpus { > #address-cells = <1>; > #size-cells = <0>; > diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts > index 8491eb53120e..674b2be900e6 100644 > --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts > +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts > @@ -12,6 +12,25 @@ / { > model = "NXP i.MX93 11X11 EVK board"; > compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; > > + aliases { > + ethernet0 = &fec; > + ethernet1 = &eqos; > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + i2c0 = &lpi2c1; > + i2c1 = &lpi2c2; > + i2c2 = &lpi2c3; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + rtc0 = &bbnsm_rtc; > + serial0 = &lpuart1; > + serial1 = &lpuart2; > + serial2 = &lpuart3; > + serial3 = &lpuart4; > + serial4 = &lpuart5; > + }; > + > chosen { > stdout-path = &lpuart1; > }; > -- > 2.37.1 > ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 7/9] arm64: defconfig: enable i.MX91 pinctrl 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou ` (5 preceding siblings ...) 2025-06-23 9:57 ` [PATCH v6 6/9] arm64: dts: freescale: move aliases from imx91_93_common.dtsi to board dts Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 9:57 ` [PATCH v6 8/9] pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91 Joy Zou ` (2 subsequent siblings) 9 siblings, 0 replies; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong Enable i.MX91 pinctrl driver for booting the system. Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Signed-off-by: Joy Zou <joy.zou@nxp.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1052af7c9860..2ae60f66ceb3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -602,6 +602,7 @@ CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8DXL=y CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ5018=y -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v6 8/9] pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou ` (6 preceding siblings ...) 2025-06-23 9:57 ` [PATCH v6 7/9] arm64: defconfig: enable i.MX91 pinctrl Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-23 12:56 ` Fabio Estevam 2025-06-23 9:57 ` [PATCH v6 9/9] net: stmmac: imx: add i.MX91 support Joy Zou 2025-06-24 7:29 ` [PATCH v6 0/9] Add i.MX91 platform support Krzysztof Kozlowski 9 siblings, 1 reply; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong The i.MX91 is derived from i.MX93, but there is no DSI and PXP in i.MX91, so mask these. Signed-off-by: Joy Zou <joy.zou@nxp.com> --- Changes for v5: 1. add imx93-blk-ctrl driver change for imx91 support. --- drivers/pmdomain/imx/imx93-blk-ctrl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pmdomain/imx/imx93-blk-ctrl.c b/drivers/pmdomain/imx/imx93-blk-ctrl.c index 0e2ba8ec55d7..04014dd5bd84 100644 --- a/drivers/pmdomain/imx/imx93-blk-ctrl.c +++ b/drivers/pmdomain/imx/imx93-blk-ctrl.c @@ -86,6 +86,7 @@ struct imx93_blk_ctrl_domain { struct imx93_blk_ctrl_data { const struct imx93_blk_ctrl_domain_data *domains; + u32 skip_mask; int num_domains; const char * const *clk_names; int num_clks; @@ -250,6 +251,8 @@ static int imx93_blk_ctrl_probe(struct platform_device *pdev) int j; domain->data = data; + if (bc_data->skip_mask & BIT(i)) + continue; for (j = 0; j < data->num_clks; j++) domain->clks[j].id = data->clk_names[j]; @@ -418,6 +421,15 @@ static const struct regmap_access_table imx93_media_blk_ctl_access_table = { .n_yes_ranges = ARRAY_SIZE(imx93_media_blk_ctl_yes_ranges), }; +static const struct imx93_blk_ctrl_data imx91_media_blk_ctl_dev_data = { + .domains = imx93_media_blk_ctl_domain_data, + .skip_mask = BIT(IMX93_MEDIABLK_PD_MIPI_DSI) | BIT(IMX93_MEDIABLK_PD_PXP), + .num_domains = ARRAY_SIZE(imx93_media_blk_ctl_domain_data), + .clk_names = (const char *[]){ "axi", "apb", "nic", }, + .num_clks = 3, + .reg_access_table = &imx93_media_blk_ctl_access_table, +}; + static const struct imx93_blk_ctrl_data imx93_media_blk_ctl_dev_data = { .domains = imx93_media_blk_ctl_domain_data, .num_domains = ARRAY_SIZE(imx93_media_blk_ctl_domain_data), @@ -428,6 +440,9 @@ static const struct imx93_blk_ctrl_data imx93_media_blk_ctl_dev_data = { static const struct of_device_id imx93_blk_ctrl_of_match[] = { { + .compatible = "fsl,imx91-media-blk-ctrl", + .data = &imx91_media_blk_ctl_dev_data + }, { .compatible = "fsl,imx93-media-blk-ctrl", .data = &imx93_media_blk_ctl_dev_data }, { -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v6 8/9] pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91 2025-06-23 9:57 ` [PATCH v6 8/9] pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91 Joy Zou @ 2025-06-23 12:56 ` Fabio Estevam 0 siblings, 0 replies; 21+ messages in thread From: Fabio Estevam @ 2025-06-23 12:56 UTC (permalink / raw) To: Joy Zou Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong On Mon, Jun 23, 2025 at 7:00 AM Joy Zou <joy.zou@nxp.com> wrote: > +static const struct imx93_blk_ctrl_data imx91_media_blk_ctl_dev_data = { > + .domains = imx93_media_blk_ctl_domain_data, > + .skip_mask = BIT(IMX93_MEDIABLK_PD_MIPI_DSI) | BIT(IMX93_MEDIABLK_PD_PXP), > + .num_domains = ARRAY_SIZE(imx93_media_blk_ctl_domain_data), > + .clk_names = (const char *[]){ "axi", "apb", "nic", }, > + .num_clks = 3, Instead of hardcoding the number of clocks, what about using ARRAY_SIZE() instead? Like it was done here: https://lore.kernel.org/linux-arm-kernel/20250619062108.2016511-1-xiaolei.wang@windriver.com/ ^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v6 9/9] net: stmmac: imx: add i.MX91 support 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou ` (7 preceding siblings ...) 2025-06-23 9:57 ` [PATCH v6 8/9] pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91 Joy Zou @ 2025-06-23 9:57 ` Joy Zou 2025-06-24 7:29 ` [PATCH v6 0/9] Add i.MX91 platform support Krzysztof Kozlowski 9 siblings, 0 replies; 21+ messages in thread From: Joy Zou @ 2025-06-23 9:57 UTC (permalink / raw) To: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam Cc: devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong Add i.MX91 specific settings for EQoS. Signed-off-by: Joy Zou <joy.zou@nxp.com> --- Changes for v5: 1. add imx91 support. --- drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c index 889e2bb6f7f5..54243bacebfd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c @@ -301,6 +301,7 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev) dwmac->clk_mem = NULL; if (of_machine_is_compatible("fsl,imx8dxl") || + of_machine_is_compatible("fsl,imx91") || of_machine_is_compatible("fsl,imx93")) { dwmac->clk_mem = devm_clk_get(dev, "mem"); if (IS_ERR(dwmac->clk_mem)) { @@ -310,6 +311,7 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev) } if (of_machine_is_compatible("fsl,imx8mp") || + of_machine_is_compatible("fsl,imx91") || of_machine_is_compatible("fsl,imx93")) { /* Binding doc describes the propety: * is required by i.MX8MP, i.MX93. -- 2.37.1 ^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v6 0/9] Add i.MX91 platform support 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou ` (8 preceding siblings ...) 2025-06-23 9:57 ` [PATCH v6 9/9] net: stmmac: imx: add i.MX91 support Joy Zou @ 2025-06-24 7:29 ` Krzysztof Kozlowski 9 siblings, 0 replies; 21+ messages in thread From: Krzysztof Kozlowski @ 2025-06-24 7:29 UTC (permalink / raw) To: Joy Zou Cc: robh, krzk+dt, conor+dt, shawnguo, s.hauer, catalin.marinas, will, andrew+netdev, davem, edumazet, kuba, pabeni, mcoquelin.stm32, alexandre.torgue, ulf.hansson, richardcochran, kernel, festevam, devicetree, linux-kernel, imx, linux-arm-kernel, netdev, linux-stm32, linux-pm, frank.li, ye.li, ping.bai, aisheng.dong On Mon, Jun 23, 2025 at 05:57:23PM +0800, Joy Zou wrote: > The design of i.MX91 platform is very similar to i.MX93. > Extracts the common parts in order to reuse code. > > The mainly difference between i.MX91 and i.MX93 is as follows: > - i.MX91 removed some clocks and modified the names of some clocks. > - i.MX91 only has one A core. > - i.MX91 has different pinmux. > - i.MX91 has updated to new temperature sensor same with i.MX95. > > --- > Changes for v6: > - add changelog in per patch. > - correct commit message spell for patch #1. > - merge rename imx93.dtsi to imx91_93_common.dtsi and move i.MX93 > specific part from imx91_93_common.dtsi to imx93.dtsi for patch #3. > - modify the commit message for patch #3. > - restore copyright time and add modification time for common dtsi for patch #3. > - remove unused map0 label in imx91_93_common.dtsi for patch #3. > - remove tmu related node for patch #4. > - remove unused regulators and pinctrl settings for patch #5. > - add new modification for aliases change patch #6. Where are the links to the previous versions? Why are you not using b4? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2025-06-25 6:10 UTC | newest] Thread overview: 21+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-06-23 9:57 [PATCH v6 0/9] Add i.MX91 platform support Joy Zou 2025-06-23 9:57 ` [PATCH v6 1/9] dt-bindings: arm: fsl: add i.MX91 11x11 evk board Joy Zou 2025-06-23 9:57 ` [PATCH v6 2/9] dt-bindings: soc: imx-blk-ctrl: add i.MX91 blk-ctrl compatible Joy Zou 2025-06-23 14:51 ` Frank Li 2025-06-24 7:28 ` Krzysztof Kozlowski 2025-06-24 14:51 ` Frank Li 2025-06-24 15:39 ` Krzysztof Kozlowski 2025-06-24 19:08 ` Frank Li 2025-06-25 6:10 ` Krzysztof Kozlowski 2025-06-23 9:57 ` [PATCH v6 3/9] arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them Joy Zou 2025-06-23 9:57 ` [PATCH v6 4/9] arm64: dts: imx91: add i.MX91 dtsi support Joy Zou 2025-06-23 9:57 ` [PATCH v6 5/9] arm64: dts: freescale: add i.MX91 11x11 EVK basic support Joy Zou 2025-06-23 14:57 ` Frank Li 2025-06-23 18:17 ` Andrew Lunn 2025-06-23 9:57 ` [PATCH v6 6/9] arm64: dts: freescale: move aliases from imx91_93_common.dtsi to board dts Joy Zou 2025-06-23 15:10 ` Frank Li 2025-06-23 9:57 ` [PATCH v6 7/9] arm64: defconfig: enable i.MX91 pinctrl Joy Zou 2025-06-23 9:57 ` [PATCH v6 8/9] pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91 Joy Zou 2025-06-23 12:56 ` Fabio Estevam 2025-06-23 9:57 ` [PATCH v6 9/9] net: stmmac: imx: add i.MX91 support Joy Zou 2025-06-24 7:29 ` [PATCH v6 0/9] Add i.MX91 platform support Krzysztof Kozlowski
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