From: Nicolin Chen <nicolinc@nvidia.com>
To: <will@kernel.org>, <robin.murphy@arm.com>, <jgg@nvidia.com>,
"Jonathan Cameron" <jonathan.cameron@oss.qualcomm.com>
Cc: <joro@8bytes.org>, <bhelgaas@google.com>, <praan@google.com>,
<kevin.tian@intel.com>, <kees@kernel.org>, <smostafa@google.com>,
<baolu.lu@linux.intel.com>,
Jean-Philippe Brucker <jpb@kernel.org>,
"Eric Auger" <eric.auger@redhat.com>,
<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<skaestle@nvidia.com>, <mmarrid@nvidia.com>,
<skolothumtho@nvidia.com>, <bbiber@nvidia.com>,
<harsha.v@oss.qualcomm.com>
Subject: [PATCH v4 09/15] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered
Date: Thu, 10 Sep 2026 16:17:01 -0700 [thread overview]
Message-ID: <e35aa8feef5208fffa7faba93725ceeb0ee2be93.1789081084.git.nicolinc@nvidia.com> (raw)
In-Reply-To: <cover.1789081084.git.nicolinc@nvidia.com>
arm_smmu_setup_irqs() can leave the PRIQ without any registered handler if
its IRQ is missing, its request fails, or the combined IRQ request fails.
These paths warn but leave ARM_SMMU_FEAT_PRI set.
This function itself would then go on to enable IRQ_CTRL_PRIQ_IRQEN, even
though no handler will drain the queue. A later patch also enables PRI on
such endpoints. The caller already enabled CR0_PRIQEN before this function
even runs.
Clear ARM_SMMU_FEAT_PRI in all three failure paths, so that subsequent code
treats PRI as unavailable. And disable CR0_PRIQEN after the setup function
returns.
A kdump kernel doesn't service page requests: strip FEAT_PRI when detecting
features, so downstream PRI setup is skipped.
Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index bd7615ce69581..43a6029cef430 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -4936,9 +4936,11 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
dev_warn(smmu->dev,
"failed to enable priq irq\n");
smmu->priq.q.irq = 0;
+ smmu->features &= ~ARM_SMMU_FEAT_PRI;
}
} else {
dev_warn(smmu->dev, "no priq irq - PRI will be broken\n");
+ smmu->features &= ~ARM_SMMU_FEAT_PRI;
}
} else {
/* An unrequested IRQ (e.g. set by DT) must not be disabled */
@@ -4973,6 +4975,7 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu)
if (ret < 0) {
dev_warn(smmu->dev, "failed to enable combined irq\n");
smmu->combined_irq = 0;
+ smmu->features &= ~ARM_SMMU_FEAT_PRI;
}
} else
arm_smmu_setup_unique_irqs(smmu);
@@ -5153,6 +5156,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu)
return ret;
}
+ /* arm_smmu_setup_irqs() might have unset the ARM_SMMU_FEAT_PRI */
+ if (!(smmu->features & ARM_SMMU_FEAT_PRI))
+ enables &= ~CR0_PRIQEN;
+
if (is_kdump_kernel())
enables &= ~(CR0_EVTQEN | CR0_PRIQEN);
@@ -5294,7 +5301,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
}
/* Boolean feature flags */
- if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI)
+ if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI && !is_kdump_kernel())
smmu->features |= ARM_SMMU_FEAT_PRI;
if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS)
--
2.43.0
next prev parent reply other threads:[~2026-09-10 23:17 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 23:16 [PATCH v4 00/15] iommu/arm-smmu-v3: Add PRI support Nicolin Chen
2026-09-10 23:16 ` [PATCH v4 01/15] iommu/arm-smmu-v3: Disable the impl before disabling the SMMU on shutdown Nicolin Chen
2026-09-10 23:32 ` sashiko-bot
2026-09-11 0:14 ` Jonathan Cameron
2026-09-11 23:17 ` Nicolin Chen
2026-09-10 23:16 ` [PATCH v4 02/15] iommu/arm-smmu-v3: Add arm_smmu_attach_release() Nicolin Chen
2026-09-10 23:28 ` sashiko-bot
2026-09-11 0:14 ` Jonathan Cameron
2026-09-10 23:16 ` [PATCH v4 03/15] iommu/arm-smmu-v3: Add Q_POS() macro Nicolin Chen
2026-09-10 23:21 ` sashiko-bot
2026-09-10 23:16 ` [PATCH v4 04/15] iommu/arm-smmu-v3: Drain in-flight fault events on domain detach Nicolin Chen
2026-09-10 23:31 ` sashiko-bot
2026-09-11 0:14 ` Jonathan Cameron
2026-09-10 23:16 ` [PATCH v4 05/15] iommu/arm-smmu-v3: Flush in-flight fault work " Nicolin Chen
2026-09-10 23:35 ` sashiko-bot
2026-09-11 0:14 ` Jonathan Cameron
2026-09-10 23:16 ` [PATCH v4 06/15] iommu/arm-smmu-v3: Allocate IOPF queue without FEAT_SVA Nicolin Chen
2026-09-10 23:28 ` sashiko-bot
2026-09-10 23:16 ` [PATCH v4 07/15] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Nicolin Chen
2026-09-10 23:36 ` sashiko-bot
2026-09-10 23:17 ` [PATCH v4 08/15] iommu/arm-smmu-v3: Disable the queue IRQs before disabling the SMMU Nicolin Chen
2026-09-10 23:28 ` sashiko-bot
2026-09-10 23:17 ` Nicolin Chen [this message]
2026-09-10 23:36 ` [PATCH v4 09/15] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered sashiko-bot
2026-09-10 23:17 ` [PATCH v4 10/15] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Nicolin Chen
2026-09-10 23:35 ` sashiko-bot
2026-09-11 0:14 ` Jonathan Cameron
2026-09-11 23:16 ` Nicolin Chen
2026-09-14 21:10 ` Jonathan Cameron
2026-09-10 23:17 ` [PATCH v4 11/15] iommu/arm-smmu-v3: Discard partial PRI faults on PRIQ overflow Nicolin Chen
2026-09-10 23:33 ` sashiko-bot
2026-09-11 0:14 ` Jonathan Cameron
2026-09-10 23:17 ` [PATCH v4 12/15] iommu/arm-smmu-v3: Allocate IOPF queue for ARM_SMMU_FEAT_PRI Nicolin Chen
2026-09-10 23:31 ` sashiko-bot
2026-09-10 23:17 ` [PATCH v4 13/15] PCI/ATS: Add PRI stubs Nicolin Chen
2026-09-10 23:25 ` sashiko-bot
2026-09-10 23:17 ` [PATCH v4 14/15] PCI/ATS: Export pci_enable_pri() and pci_reset_pri() Nicolin Chen
2026-09-10 23:28 ` sashiko-bot
2026-09-10 23:17 ` [PATCH v4 15/15] iommu/arm-smmu-v3: Enable PRI for PCI device in arm_smmu_probe_device() Nicolin Chen
2026-09-10 23:36 ` sashiko-bot
2026-09-11 0:14 ` Jonathan Cameron
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