From: Chris Wilson <chris@chris-wilson.co.uk>
To: Ben Widawsky <ben@bwidawsk.net>, Kenneth Graunke <kenneth@whitecape.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.
Date: Thu, 06 Oct 2011 00:36:03 +0100 [thread overview]
Message-ID: <e39f63$27lah8@fmsmga002.fm.intel.com> (raw)
In-Reply-To: <20111005155713.6e2f0c6c@bwidawsk.net>
On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky <ben@bwidawsk.net> wrote:
> I think we also want a TLB invalidate here, bit 18. This requires another
> workaround before issuing this flush: We need 2 Store Data Commands (such as
> MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ stall
> (20) and TLB inv bit (18) set
Isn't that workaround itself rather hand-wavy? As in it gives the
hardware sufficient time to complete outstanding writes, but not
necessarily. Or am I thinking of yet another workaround...
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2011-10-05 23:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-10-04 6:02 [PATCH 1/3] i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Kenneth Graunke
2011-10-04 6:02 ` [PATCH 2/3] i915: Rename PIPE_CONTROL bit defines to be less terse Kenneth Graunke
2011-10-04 8:30 ` Daniel Vetter
2011-10-05 5:13 ` Kenneth Graunke
2011-10-05 10:05 ` Daniel Vetter
2011-10-05 22:29 ` Ben Widawsky
2011-10-04 6:02 ` [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Kenneth Graunke
2011-10-05 22:57 ` Ben Widawsky
2011-10-05 23:36 ` Chris Wilson [this message]
2011-10-05 23:54 ` Daniel Vetter
2011-10-06 0:59 ` Eric Anholt
2011-10-06 5:15 ` Ben Widawsky
2011-10-06 18:00 ` Eric Anholt
2011-10-06 19:01 ` Ben Widawsky
2011-10-05 23:39 ` Ben Widawsky
2011-10-05 20:35 ` [PATCH 1/3] i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define Ben Widawsky
2011-10-11 11:09 ` Daniel Vetter
2011-10-11 17:20 ` Jesse Barnes
2011-10-11 18:39 ` Ben Widawsky
2011-10-11 18:53 ` Jesse Barnes
2011-10-11 22:17 ` Keith Packard
-- strict thread matches above, loose matches on Subject: below --
2011-10-11 21:41 [PATCH 1/3] drm/i915: " Daniel Vetter
2011-10-11 21:41 ` [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Daniel Vetter
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