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* [PATCH 0/4] drm/i915: Optimize registers accesses in irq handlers
@ 2026-10-22 11:55 Ville Syrjala
  2026-10-22 11:55 ` [PATCH 1/4] drm/i915: Use intel_de_read64_2x32_volatile_fw() for IVB_TIMESTAMP_CTR+PIPE_FRMTMSTMP query Ville Syrjala
                   ` (15 more replies)
  0 siblings, 16 replies; 22+ messages in thread
From: Ville Syrjala @ 2026-10-22 11:55 UTC (permalink / raw)
  To: intel-gfx; +Cc: intel-xe

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

MMIO is incredible expensive on some of our platforms (especially
the new ones). Switch to the cheaper _fw() register accessors
in irq handlers to avoid adding a lot more costly FPGA_DBG MMIO
reads to them when I (eventually) hoist the unclaimed register
detection to the display code (and thus bring it over to xe
as well).

ILK-HSW are still left with the more costly variants. I'm thinking
I might try to convert them as well at some point, but that'll
need some extra testing (especially on IVB/HSW which might
suffer from some system hangs from parallel MMIO accesses to the
same cacheline). MMIO isn't super expnsive on those platforms
so might not matter too much. SNB/IVB are epscially cheap with
~70 ns for both reads and writes. ILK and HSW are bit more
expensive in the 100-200 ns range.

Ville Syrjälä (4):
  drm/i915: Use intel_de_read64_2x32_volatile_fw() for
    IVB_TIMESTAMP_CTR+PIPE_FRMTMSTMP query
  drm/i915: Use intel_de_{read,write})fw() in BDW+ irq handlers
  drm/i915: Use intel_de_{read,write})fw() in VLV/CHV irq handlers
  drm/i915: Skip redundant frame/scanline/time reads for async flips

 drivers/gpu/drm/i915/display/intel_crtc.c     | 10 +-
 .../gpu/drm/i915/display/intel_display_irq.c  | 94 +++++++++----------
 drivers/gpu/drm/i915/display/intel_dmc.c      |  6 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  | 26 ++---
 drivers/gpu/drm/i915/display/intel_vblank.c   | 34 +++----
 5 files changed, 81 insertions(+), 89 deletions(-)

-- 
2.55.0


^ permalink raw reply	[flat|nested] 22+ messages in thread

end of thread, other threads:[~2026-10-28 11:04 UTC | newest]

Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-22 11:55 [PATCH 0/4] drm/i915: Optimize registers accesses in irq handlers Ville Syrjala
2026-10-22 11:55 ` [PATCH 1/4] drm/i915: Use intel_de_read64_2x32_volatile_fw() for IVB_TIMESTAMP_CTR+PIPE_FRMTMSTMP query Ville Syrjala
2026-10-22 12:10   ` Jani Nikula
2026-10-22 11:55 ` [PATCH 2/4] drm/i915: Use intel_de_{read, write})fw() in BDW+ irq handlers Ville Syrjala
2026-10-22 12:29   ` Jani Nikula
2026-10-22 11:55 ` [PATCH 3/4] drm/i915: Use intel_de_{read, write})fw() in VLV/CHV " Ville Syrjala
2026-10-22 12:31   ` Jani Nikula
2026-10-22 11:55 ` [PATCH 4/4] drm/i915: Skip redundant frame/scanline/time reads for async flips Ville Syrjala
2026-10-22 12:15   ` Jani Nikula
2026-10-22 12:02 ` ✗ CI.checkpatch: warning for drm/i915: Optimize registers accesses in irq handlers Patchwork
2026-10-22 12:05 ` ✓ CI.KUnit: success " Patchwork
2026-10-22 12:41 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-10-22 13:25 ` ✓ i915.CI.BAT: success " Patchwork
2026-10-22 19:28 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-10-23  0:54 ` ✗ i915.CI.Full: " Patchwork
2026-10-23 18:20 ` ✗ CI.checkpatch: warning for drm/i915: Optimize registers accesses in irq handlers (rev2) Patchwork
2026-10-23 18:23 ` ✓ CI.KUnit: success " Patchwork
2026-10-23 18:45 ` ✓ i915.CI.BAT: " Patchwork
2026-10-23 19:00 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-24  2:08 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-10-28 11:04   ` Saarinen, Jani
2026-10-24  3:50 ` ✓ i915.CI.Full: success " Patchwork

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