* [PATCH 1/2] drm/amdkfd: convert to IP-based version checking
@ 2021-11-05 19:58 Graham Sider
2021-11-05 19:58 ` [PATCH 2/2] drm/amdkfd: convert misc checks to IP " Graham Sider
2021-11-08 22:29 ` [PATCH 1/2] drm/amdkfd: convert to IP-based " Felix Kuehling
0 siblings, 2 replies; 4+ messages in thread
From: Graham Sider @ 2021-11-05 19:58 UTC (permalink / raw)
To: amd-gfx; +Cc: Felix.Kuehling, Harish.Kasiviswanathan, Graham Sider
Patches to change KFD to use IP versions rather than asic_type.
Converting IP version checking in main switch statements.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 124 +++++++++---------
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 56 ++++----
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 52 ++++----
.../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 56 ++++----
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 54 ++++----
5 files changed, 189 insertions(+), 153 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 1dc6cb7446e0..500bc7e40309 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1377,67 +1377,71 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
pcache_info = vegam_cache_info;
num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
break;
- case CHIP_VEGA10:
- pcache_info = vega10_cache_info;
- num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
- break;
- case CHIP_VEGA12:
- pcache_info = vega12_cache_info;
- num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
- break;
- case CHIP_VEGA20:
- case CHIP_ARCTURUS:
- pcache_info = vega20_cache_info;
- num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
- break;
- case CHIP_ALDEBARAN:
- pcache_info = aldebaran_cache_info;
- num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
- break;
- case CHIP_RAVEN:
- pcache_info = raven_cache_info;
- num_of_cache_types = ARRAY_SIZE(raven_cache_info);
- break;
- case CHIP_RENOIR:
- pcache_info = renoir_cache_info;
- num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
- break;
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_CYAN_SKILLFISH:
- pcache_info = navi10_cache_info;
- num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
- break;
- case CHIP_NAVI14:
- pcache_info = navi14_cache_info;
- num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
- break;
- case CHIP_SIENNA_CICHLID:
- pcache_info = sienna_cichlid_cache_info;
- num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
- break;
- case CHIP_NAVY_FLOUNDER:
- pcache_info = navy_flounder_cache_info;
- num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
- break;
- case CHIP_DIMGREY_CAVEFISH:
- pcache_info = dimgrey_cavefish_cache_info;
- num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
- break;
- case CHIP_VANGOGH:
- pcache_info = vangogh_cache_info;
- num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
- break;
- case CHIP_BEIGE_GOBY:
- pcache_info = beige_goby_cache_info;
- num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
- break;
- case CHIP_YELLOW_CARP:
- pcache_info = yellow_carp_cache_info;
- num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
- break;
default:
- return -EINVAL;
+ switch(kdev->adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ pcache_info = vega10_cache_info;
+ num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
+ break;
+ case IP_VERSION(9, 2, 1):
+ pcache_info = vega12_cache_info;
+ num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
+ break;
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ pcache_info = vega20_cache_info;
+ num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
+ break;
+ case IP_VERSION(9, 4, 2):
+ pcache_info = aldebaran_cache_info;
+ num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
+ break;
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ pcache_info = raven_cache_info;
+ num_of_cache_types = ARRAY_SIZE(raven_cache_info);
+ break;
+ case IP_VERSION(9, 3, 0):
+ pcache_info = renoir_cache_info;
+ num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
+ break;
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 3):
+ pcache_info = navi10_cache_info;
+ num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
+ break;
+ case IP_VERSION(10, 1, 1):
+ pcache_info = navi14_cache_info;
+ num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
+ break;
+ case IP_VERSION(10, 3, 0):
+ pcache_info = sienna_cichlid_cache_info;
+ num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
+ break;
+ case IP_VERSION(10, 3, 2):
+ pcache_info = navy_flounder_cache_info;
+ num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
+ break;
+ case IP_VERSION(10, 3, 4):
+ pcache_info = dimgrey_cavefish_cache_info;
+ num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
+ break;
+ case IP_VERSION(10, 3, 1):
+ pcache_info = vangogh_cache_info;
+ num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
+ break;
+ case IP_VERSION(10, 3, 5):
+ pcache_info = beige_goby_cache_info;
+ num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
+ break;
+ case IP_VERSION(10, 3, 3):
+ pcache_info = yellow_carp_cache_info;
+ num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
+ break;
+ default:
+ return -EINVAL;
+ }
}
*size_filled = 0;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 0a60317509c8..8a39494fa093 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -1947,31 +1947,39 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
device_queue_manager_init_vi_tonga(&dqm->asic_ops);
break;
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_RENOIR:
- case CHIP_ARCTURUS:
- case CHIP_ALDEBARAN:
- device_queue_manager_init_v9(&dqm->asic_ops);
- break;
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_NAVI14:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
- device_queue_manager_init_v10_navi10(&dqm->asic_ops);
- break;
default:
- WARN(1, "Unexpected ASIC family %u",
- dev->device_info->asic_family);
- goto out_free;
+ switch (dev->adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ device_queue_manager_init_v9(&dqm->asic_ops);
+ break;
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 1, 3):
+ device_queue_manager_init_v10_navi10(&dqm->asic_ops);
+ break;
+ default:
+ if (dev->adev->ip_versions[GC_HWIP][0])
+ WARN(1, "Unexpected GC HWIP version %06x",
+ dev->adev->ip_versions[GC_HWIP][0]);
+ else
+ WARN(1, "Unexpected ASIC family %u",
+ dev->device_info->asic_family);
+ goto out_free;
+ }
}
if (init_mqd_managers(dqm))
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 2e86692def19..6c56e43e2f7b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -406,29 +406,37 @@ int kfd_init_apertures(struct kfd_process *process)
case CHIP_VEGAM:
kfd_init_apertures_vi(pdd, id);
break;
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_RENOIR:
- case CHIP_ARCTURUS:
- case CHIP_ALDEBARAN:
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_NAVI14:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
- kfd_init_apertures_v9(pdd, id);
- break;
default:
- WARN(1, "Unexpected ASIC family %u",
- dev->device_info->asic_family);
- return -EINVAL;
+ switch (dev->adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 1, 3):
+ kfd_init_apertures_v9(pdd, id);
+ break;
+ default:
+ if (dev->adev->ip_versions[GC_HWIP][0])
+ WARN(1, "Unexpected GC HWIP version %06x",
+ dev->adev->ip_versions[GC_HWIP][0]);
+ else
+ WARN(1, "Unexpected ASIC family %u",
+ dev->device_info->asic_family);
+ return -EINVAL;
+ }
}
if (!dev->use_iommu_v2) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index e547f1f8c49f..0bee4b965e1f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -236,31 +236,39 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
case CHIP_VEGAM:
pm->pmf = &kfd_vi_pm_funcs;
break;
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_RENOIR:
- case CHIP_ARCTURUS:
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_NAVI14:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
- pm->pmf = &kfd_v9_pm_funcs;
- break;
- case CHIP_ALDEBARAN:
- pm->pmf = &kfd_aldebaran_pm_funcs;
- break;
default:
- WARN(1, "Unexpected ASIC family %u",
- dqm->dev->device_info->asic_family);
- return -EINVAL;
+ switch (dqm->dev->adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 1, 3):
+ pm->pmf = &kfd_v9_pm_funcs;
+ break;
+ case IP_VERSION(9, 4, 2):
+ pm->pmf = &kfd_aldebaran_pm_funcs;
+ break;
+ default:
+ if (dqm->dev->adev->ip_versions[GC_HWIP][0])
+ WARN(1, "Unexpected GC HWIP version %06x",
+ dqm->dev->adev->ip_versions[GC_HWIP][0]);
+ else
+ WARN(1, "Unexpected ASIC family %u",
+ dqm->dev->device_info->asic_family);
+ return -EINVAL;
+ }
}
pm->dqm = dqm;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index ae7c9944dc4a..5353f43c67f3 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1425,30 +1425,38 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
break;
- case CHIP_VEGA10:
- case CHIP_VEGA12:
- case CHIP_VEGA20:
- case CHIP_RAVEN:
- case CHIP_RENOIR:
- case CHIP_ARCTURUS:
- case CHIP_ALDEBARAN:
- case CHIP_NAVI10:
- case CHIP_NAVI12:
- case CHIP_NAVI14:
- case CHIP_SIENNA_CICHLID:
- case CHIP_NAVY_FLOUNDER:
- case CHIP_VANGOGH:
- case CHIP_DIMGREY_CAVEFISH:
- case CHIP_BEIGE_GOBY:
- case CHIP_YELLOW_CARP:
- case CHIP_CYAN_SKILLFISH:
- dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
- HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
- HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
- break;
default:
- WARN(1, "Unexpected ASIC family %u",
- dev->gpu->device_info->asic_family);
+ switch (dev->gpu->adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 0, 1):
+ case IP_VERSION(9, 2, 1):
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 1, 0):
+ case IP_VERSION(9, 2, 2):
+ case IP_VERSION(9, 3, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ case IP_VERSION(10, 1, 10):
+ case IP_VERSION(10, 1, 2):
+ case IP_VERSION(10, 1, 1):
+ case IP_VERSION(10, 3, 0):
+ case IP_VERSION(10, 3, 2):
+ case IP_VERSION(10, 3, 1):
+ case IP_VERSION(10, 3, 4):
+ case IP_VERSION(10, 3, 5):
+ case IP_VERSION(10, 3, 3):
+ case IP_VERSION(10, 1, 3):
+ dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
+ HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
+ HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
+ break;
+ default:
+ if (dev->gpu->adev->ip_versions[GC_HWIP][0])
+ WARN(1, "Unexpected GC HWIP version %06x",
+ dev->gpu->adev->ip_versions[GC_HWIP][0]);
+ else
+ WARN(1, "Unexpected ASIC family %u",
+ dev->gpu->device_info->asic_family);
+ }
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amdkfd: convert misc checks to IP version checking
2021-11-05 19:58 [PATCH 1/2] drm/amdkfd: convert to IP-based version checking Graham Sider
@ 2021-11-05 19:58 ` Graham Sider
2021-11-08 22:21 ` Felix Kuehling
2021-11-08 22:29 ` [PATCH 1/2] drm/amdkfd: convert to IP-based " Felix Kuehling
1 sibling, 1 reply; 4+ messages in thread
From: Graham Sider @ 2021-11-05 19:58 UTC (permalink / raw)
To: amd-gfx; +Cc: Felix.Kuehling, Harish.Kasiviswanathan, Graham Sider
Switch to IP version checking instead of asic_type on various KFD
version checks.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++--
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_device.c | 24 ++++++++++---------
.../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
.../amd/amdkfd/kfd_device_queue_manager_v9.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_events.c | 6 +++--
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 +++----
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 6 ++---
drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++--
11 files changed, 35 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 2e3d74f7fbfb..f66c78fda5be 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -321,7 +321,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
/* Return gpu_id as doorbell offset for mmap usage */
args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
- if (KFD_IS_SOC15(dev->device_info->asic_family))
+ if (KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0]))
/* On SOC15 ASICs, include the doorbell offset within the
* process doorbell frame, which is 2 pages.
*/
@@ -1603,7 +1603,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
}
mutex_unlock(&p->mutex);
- if (dev->device_info->asic_family == CHIP_ALDEBARAN) {
+ if (dev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev,
(struct kgd_mem *) mem, true);
if (err) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 500bc7e40309..b41e62a324f6 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1992,7 +1992,7 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
sub_type_hdr->num_hops_xgmi = 1;
- if (kdev->adev->asic_type == CHIP_ALDEBARAN) {
+ if (kdev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
sub_type_hdr->minimum_bandwidth_mbs =
amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(
kdev->adev, NULL, true);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index b752dc36a2cd..29f8fcd4b779 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -844,23 +844,23 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
static void kfd_cwsr_init(struct kfd_dev *kfd)
{
if (cwsr_enable && kfd->device_info->supports_cwsr) {
- if (kfd->device_info->asic_family < CHIP_VEGA10) {
+ if (kfd->adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 1)) {
BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_gfx8_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
- } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
+ } else if (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_arcturus_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
- } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) {
+ } else if (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
- } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
+ } else if (kfd->adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 1, 1)) {
BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_gfx9_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
- } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) {
+ } else if (kfd->adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)) {
BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
kfd->cwsr_isa = cwsr_trap_nv1x_hex;
kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
@@ -882,14 +882,16 @@ static int kfd_gws_init(struct kfd_dev *kfd)
return 0;
if (hws_gws_support
- || (kfd->device_info->asic_family == CHIP_VEGA10
+ || (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1)
&& kfd->mec2_fw_version >= 0x81b3)
- || (kfd->device_info->asic_family >= CHIP_VEGA12
- && kfd->device_info->asic_family <= CHIP_RAVEN
+ || ((kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)
+ || kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)
+ || kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 1, 0)
+ || kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 2))
&& kfd->mec2_fw_version >= 0x1b3)
- || (kfd->device_info->asic_family == CHIP_ARCTURUS
+ || (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)
&& kfd->mec2_fw_version >= 0x30)
- || (kfd->device_info->asic_family == CHIP_ALDEBARAN
+ || (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)
&& kfd->mec2_fw_version >= 0x28))
ret = amdgpu_amdkfd_alloc_gws(kfd->adev,
kfd->adev->gds.gws_size, &kfd->gws);
@@ -959,7 +961,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
* There can be only 2 packets at once
*/
map_process_packet_size =
- kfd->device_info->asic_family == CHIP_ALDEBARAN ?
+ kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ?
sizeof(struct pm4_mes_map_process_aldebaran) :
sizeof(struct pm4_mes_map_process);
size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 8a39494fa093..7cadcdd9ffd2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -157,7 +157,7 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
{
struct kfd_dev *dev = qpd->dqm->dev;
- if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
+ if (!KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0])) {
/* On pre-SOC15 chips we need to use the queue ID to
* preserve the user mode ABI.
*/
@@ -202,7 +202,7 @@ static void deallocate_doorbell(struct qcm_process_device *qpd,
unsigned int old;
struct kfd_dev *dev = qpd->dqm->dev;
- if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
+ if (!KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0]) ||
q->properties.type == KFD_QUEUE_TYPE_SDMA ||
q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
return;
@@ -250,7 +250,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,
program_sh_mem_settings(dqm, qpd);
- if (dqm->dev->device_info->asic_family >= CHIP_VEGA10 &&
+ if (dqm->dev->adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 1) &&
dqm->dev->cwsr_enabled)
program_trap_handler_settings(dqm, qpd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
index b5c3d13643f1..0f7471796667 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
@@ -62,7 +62,7 @@ static int update_qpd_v9(struct device_queue_manager *dqm,
SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
- if (dqm->dev->device_info->asic_family == CHIP_ALDEBARAN) {
+ if (dqm->dev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
/* Aldebaran can safely support different XNACK modes
* per process
*/
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
index 3eea4edee355..20745086308e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
@@ -935,8 +935,10 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, u32 pasid,
/* Workaround on Raven to not kill the process when memory is freed
* before IOMMU is able to finish processing all the excessive PPRs
*/
- if (dev->device_info->asic_family != CHIP_RAVEN &&
- dev->device_info->asic_family != CHIP_RENOIR) {
+
+ if (dev->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 1, 0) &&
+ dev->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 2) &&
+ dev->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) {
mutex_lock(&p->event_mutex);
/* Lookup events by type and signal them */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index aeade32ec298..c376c43a6c16 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -940,7 +940,7 @@ int svm_migrate_init(struct amdgpu_device *adev)
void *r;
/* Page migration works on Vega10 or newer */
- if (kfddev->device_info->asic_family < CHIP_VEGA10)
+ if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 1))
return -EINVAL;
pgmap = &kfddev->pgmap;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 2a5b4d86bf40..013678fabc0c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -183,7 +183,7 @@ enum cache_policy {
cache_policy_noncoherent
};
-#define KFD_IS_SOC15(chip) ((chip) >= CHIP_VEGA10)
+#define KFD_IS_SOC15(gcipv) ((gcipv) >= (IP_VERSION(9, 0, 1)))
struct kfd_event_interrupt_class {
bool (*interrupt_isr)(struct kfd_dev *dev,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index f29b3932e3dc..f260f30b996c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -1317,14 +1317,14 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported)
* support the SVM APIs and don't need to be considered
* for the XNACK mode selection.
*/
- if (dev->device_info->asic_family < CHIP_VEGA10)
+ if (dev->adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 1))
continue;
/* Aldebaran can always support XNACK because it can support
* per-process XNACK mode selection. But let the dev->noretry
* setting still influence the default XNACK mode.
*/
if (supported &&
- dev->device_info->asic_family == CHIP_ALDEBARAN)
+ dev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
continue;
/* GFXv10 and later GPUs do not support shader preemption
@@ -1332,7 +1332,7 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported)
* management and memory-manager-related preemptions or
* even deadlocks.
*/
- if (dev->device_info->asic_family >= CHIP_NAVI10)
+ if (dev->adev->ip_versions[GC_HWIP][0] > IP_VERSION(10, 1, 1))
return false;
if (dev->noretry)
@@ -1431,7 +1431,7 @@ static int init_doorbell_bitmap(struct qcm_process_device *qpd,
int range_start = dev->shared_resources.non_cp_doorbells_start;
int range_end = dev->shared_resources.non_cp_doorbells_end;
- if (!KFD_IS_SOC15(dev->device_info->asic_family))
+ if (!KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0]))
return 0;
qpd->doorbell_bitmap =
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 065fa2a74c78..3be0ccb7a880 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1051,8 +1051,8 @@ svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange,
if (domain == SVM_RANGE_VRAM_DOMAIN)
bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev);
- switch (adev->asic_type) {
- case CHIP_ARCTURUS:
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(9, 4, 1):
if (domain == SVM_RANGE_VRAM_DOMAIN) {
if (bo_adev == adev) {
mapping_flags |= coherent ?
@@ -1068,7 +1068,7 @@ svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange,
AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
}
break;
- case CHIP_ALDEBARAN:
+ case IP_VERSION(9, 4, 2):
if (domain == SVM_RANGE_VRAM_DOMAIN) {
if (bo_adev == adev) {
mapping_flags |= coherent ?
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 5353f43c67f3..27c4d2599990 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1239,7 +1239,7 @@ static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,
*/
if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS ||
(inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
- to_dev->gpu->device_info->asic_family == CHIP_VEGA20)) {
+ to_dev->gpu->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0))) {
outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
}
@@ -1487,7 +1487,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
HSA_CAP_MEM_EDCSUPPORTED : 0;
- if (dev->gpu->adev->asic_type != CHIP_VEGA10)
+ if (dev->gpu->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 0, 1))
dev->node_props.capability |= (dev->gpu->adev->ras_enabled != 0) ?
HSA_CAP_RASEVENTNOTIFY : 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/amdkfd: convert misc checks to IP version checking
2021-11-05 19:58 ` [PATCH 2/2] drm/amdkfd: convert misc checks to IP " Graham Sider
@ 2021-11-08 22:21 ` Felix Kuehling
0 siblings, 0 replies; 4+ messages in thread
From: Felix Kuehling @ 2021-11-08 22:21 UTC (permalink / raw)
To: Graham Sider, amd-gfx; +Cc: Harish.Kasiviswanathan
Am 2021-11-05 um 3:58 p.m. schrieb Graham Sider:
> Switch to IP version checking instead of asic_type on various KFD
> version checks.
>
> Signed-off-by: Graham Sider <Graham.Sider@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++--
> drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_device.c | 24 ++++++++++---------
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 ++---
> .../amd/amdkfd/kfd_device_queue_manager_v9.c | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_events.c | 6 +++--
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 +++----
> drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 6 ++---
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++--
> 11 files changed, 35 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index 2e3d74f7fbfb..f66c78fda5be 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -321,7 +321,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
> /* Return gpu_id as doorbell offset for mmap usage */
> args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
> args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
> - if (KFD_IS_SOC15(dev->device_info->asic_family))
> + if (KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0]))
Given the way this is used, you can probably change the definition of
KFD_IS_SOC15 to take "dev" as its parameter. It saves you some typing.
Or better yet, replace it with a more general macro you can use in the
other places as well:
#define KFD_GC_VERSION(dev) ((dev)->adev->ip_versions[GC_HWIP][0])
...
if (KFD_GC_VERSION(dev) >= IP_VERSION(9,0,1)) {
...
Regards,
Felix
> /* On SOC15 ASICs, include the doorbell offset within the
> * process doorbell frame, which is 2 pages.
> */
> @@ -1603,7 +1603,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
> }
> mutex_unlock(&p->mutex);
>
> - if (dev->device_info->asic_family == CHIP_ALDEBARAN) {
> + if (dev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
> err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev,
> (struct kgd_mem *) mem, true);
> if (err) {
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index 500bc7e40309..b41e62a324f6 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -1992,7 +1992,7 @@ static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
> sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
> sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
> sub_type_hdr->num_hops_xgmi = 1;
> - if (kdev->adev->asic_type == CHIP_ALDEBARAN) {
> + if (kdev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
> sub_type_hdr->minimum_bandwidth_mbs =
> amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(
> kdev->adev, NULL, true);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index b752dc36a2cd..29f8fcd4b779 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> @@ -844,23 +844,23 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
> static void kfd_cwsr_init(struct kfd_dev *kfd)
> {
> if (cwsr_enable && kfd->device_info->supports_cwsr) {
> - if (kfd->device_info->asic_family < CHIP_VEGA10) {
> + if (kfd->adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 1)) {
> BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
> kfd->cwsr_isa = cwsr_trap_gfx8_hex;
> kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
> - } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
> + } else if (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)) {
> BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
> kfd->cwsr_isa = cwsr_trap_arcturus_hex;
> kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
> - } else if (kfd->device_info->asic_family == CHIP_ALDEBARAN) {
> + } else if (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
> BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
> kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
> kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
> - } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
> + } else if (kfd->adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 1, 1)) {
> BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
> kfd->cwsr_isa = cwsr_trap_gfx9_hex;
> kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
> - } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) {
> + } else if (kfd->adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)) {
> BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
> kfd->cwsr_isa = cwsr_trap_nv1x_hex;
> kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
> @@ -882,14 +882,16 @@ static int kfd_gws_init(struct kfd_dev *kfd)
> return 0;
>
> if (hws_gws_support
> - || (kfd->device_info->asic_family == CHIP_VEGA10
> + || (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 0, 1)
> && kfd->mec2_fw_version >= 0x81b3)
> - || (kfd->device_info->asic_family >= CHIP_VEGA12
> - && kfd->device_info->asic_family <= CHIP_RAVEN
> + || ((kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 1)
> + || kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)
> + || kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 1, 0)
> + || kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 2, 2))
> && kfd->mec2_fw_version >= 0x1b3)
> - || (kfd->device_info->asic_family == CHIP_ARCTURUS
> + || (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1)
> && kfd->mec2_fw_version >= 0x30)
> - || (kfd->device_info->asic_family == CHIP_ALDEBARAN
> + || (kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)
> && kfd->mec2_fw_version >= 0x28))
> ret = amdgpu_amdkfd_alloc_gws(kfd->adev,
> kfd->adev->gds.gws_size, &kfd->gws);
> @@ -959,7 +961,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
> * There can be only 2 packets at once
> */
> map_process_packet_size =
> - kfd->device_info->asic_family == CHIP_ALDEBARAN ?
> + kfd->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) ?
> sizeof(struct pm4_mes_map_process_aldebaran) :
> sizeof(struct pm4_mes_map_process);
> size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 8a39494fa093..7cadcdd9ffd2 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -157,7 +157,7 @@ static int allocate_doorbell(struct qcm_process_device *qpd, struct queue *q)
> {
> struct kfd_dev *dev = qpd->dqm->dev;
>
> - if (!KFD_IS_SOC15(dev->device_info->asic_family)) {
> + if (!KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0])) {
> /* On pre-SOC15 chips we need to use the queue ID to
> * preserve the user mode ABI.
> */
> @@ -202,7 +202,7 @@ static void deallocate_doorbell(struct qcm_process_device *qpd,
> unsigned int old;
> struct kfd_dev *dev = qpd->dqm->dev;
>
> - if (!KFD_IS_SOC15(dev->device_info->asic_family) ||
> + if (!KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0]) ||
> q->properties.type == KFD_QUEUE_TYPE_SDMA ||
> q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
> return;
> @@ -250,7 +250,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,
>
> program_sh_mem_settings(dqm, qpd);
>
> - if (dqm->dev->device_info->asic_family >= CHIP_VEGA10 &&
> + if (dqm->dev->adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 0, 1) &&
> dqm->dev->cwsr_enabled)
> program_trap_handler_settings(dqm, qpd);
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> index b5c3d13643f1..0f7471796667 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v9.c
> @@ -62,7 +62,7 @@ static int update_qpd_v9(struct device_queue_manager *dqm,
> SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
> SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
>
> - if (dqm->dev->device_info->asic_family == CHIP_ALDEBARAN) {
> + if (dqm->dev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2)) {
> /* Aldebaran can safely support different XNACK modes
> * per process
> */
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> index 3eea4edee355..20745086308e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
> @@ -935,8 +935,10 @@ void kfd_signal_iommu_event(struct kfd_dev *dev, u32 pasid,
> /* Workaround on Raven to not kill the process when memory is freed
> * before IOMMU is able to finish processing all the excessive PPRs
> */
> - if (dev->device_info->asic_family != CHIP_RAVEN &&
> - dev->device_info->asic_family != CHIP_RENOIR) {
> +
> + if (dev->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 1, 0) &&
> + dev->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 2, 2) &&
> + dev->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 3, 0)) {
> mutex_lock(&p->event_mutex);
>
> /* Lookup events by type and signal them */
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> index aeade32ec298..c376c43a6c16 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> @@ -940,7 +940,7 @@ int svm_migrate_init(struct amdgpu_device *adev)
> void *r;
>
> /* Page migration works on Vega10 or newer */
> - if (kfddev->device_info->asic_family < CHIP_VEGA10)
> + if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 1))
> return -EINVAL;
>
> pgmap = &kfddev->pgmap;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index 2a5b4d86bf40..013678fabc0c 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -183,7 +183,7 @@ enum cache_policy {
> cache_policy_noncoherent
> };
>
> -#define KFD_IS_SOC15(chip) ((chip) >= CHIP_VEGA10)
> +#define KFD_IS_SOC15(gcipv) ((gcipv) >= (IP_VERSION(9, 0, 1)))
>
> struct kfd_event_interrupt_class {
> bool (*interrupt_isr)(struct kfd_dev *dev,
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> index f29b3932e3dc..f260f30b996c 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
> @@ -1317,14 +1317,14 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported)
> * support the SVM APIs and don't need to be considered
> * for the XNACK mode selection.
> */
> - if (dev->device_info->asic_family < CHIP_VEGA10)
> + if (dev->adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 1))
> continue;
> /* Aldebaran can always support XNACK because it can support
> * per-process XNACK mode selection. But let the dev->noretry
> * setting still influence the default XNACK mode.
> */
> if (supported &&
> - dev->device_info->asic_family == CHIP_ALDEBARAN)
> + dev->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2))
> continue;
>
> /* GFXv10 and later GPUs do not support shader preemption
> @@ -1332,7 +1332,7 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported)
> * management and memory-manager-related preemptions or
> * even deadlocks.
> */
> - if (dev->device_info->asic_family >= CHIP_NAVI10)
> + if (dev->adev->ip_versions[GC_HWIP][0] > IP_VERSION(10, 1, 1))
> return false;
>
> if (dev->noretry)
> @@ -1431,7 +1431,7 @@ static int init_doorbell_bitmap(struct qcm_process_device *qpd,
> int range_start = dev->shared_resources.non_cp_doorbells_start;
> int range_end = dev->shared_resources.non_cp_doorbells_end;
>
> - if (!KFD_IS_SOC15(dev->device_info->asic_family))
> + if (!KFD_IS_SOC15(dev->adev->ip_versions[GC_HWIP][0]))
> return 0;
>
> qpd->doorbell_bitmap =
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> index 065fa2a74c78..3be0ccb7a880 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> @@ -1051,8 +1051,8 @@ svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange,
> if (domain == SVM_RANGE_VRAM_DOMAIN)
> bo_adev = amdgpu_ttm_adev(prange->svm_bo->bo->tbo.bdev);
>
> - switch (adev->asic_type) {
> - case CHIP_ARCTURUS:
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 4, 1):
> if (domain == SVM_RANGE_VRAM_DOMAIN) {
> if (bo_adev == adev) {
> mapping_flags |= coherent ?
> @@ -1068,7 +1068,7 @@ svm_range_get_pte_flags(struct amdgpu_device *adev, struct svm_range *prange,
> AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC;
> }
> break;
> - case CHIP_ALDEBARAN:
> + case IP_VERSION(9, 4, 2):
> if (domain == SVM_RANGE_VRAM_DOMAIN) {
> if (bo_adev == adev) {
> mapping_flags |= coherent ?
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index 5353f43c67f3..27c4d2599990 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1239,7 +1239,7 @@ static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,
> */
> if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS ||
> (inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
> - to_dev->gpu->device_info->asic_family == CHIP_VEGA20)) {
> + to_dev->gpu->adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0))) {
> outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
> inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
> }
> @@ -1487,7 +1487,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
> ((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
> HSA_CAP_MEM_EDCSUPPORTED : 0;
>
> - if (dev->gpu->adev->asic_type != CHIP_VEGA10)
> + if (dev->gpu->adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 0, 1))
> dev->node_props.capability |= (dev->gpu->adev->ras_enabled != 0) ?
> HSA_CAP_RASEVENTNOTIFY : 0;
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/amdkfd: convert to IP-based version checking
2021-11-05 19:58 [PATCH 1/2] drm/amdkfd: convert to IP-based version checking Graham Sider
2021-11-05 19:58 ` [PATCH 2/2] drm/amdkfd: convert misc checks to IP " Graham Sider
@ 2021-11-08 22:29 ` Felix Kuehling
1 sibling, 0 replies; 4+ messages in thread
From: Felix Kuehling @ 2021-11-08 22:29 UTC (permalink / raw)
To: Graham Sider, amd-gfx; +Cc: Harish.Kasiviswanathan
Am 2021-11-05 um 3:58 p.m. schrieb Graham Sider:
> Patches to change KFD to use IP versions rather than asic_type.
> Converting IP version checking in main switch statements.
>
> Signed-off-by: Graham Sider <Graham.Sider@amd.com>
> ---
> drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 124 +++++++++---------
> .../drm/amd/amdkfd/kfd_device_queue_manager.c | 56 ++++----
> drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c | 52 ++++----
> .../gpu/drm/amd/amdkfd/kfd_packet_manager.c | 56 ++++----
> drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 54 ++++----
> 5 files changed, 189 insertions(+), 153 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index 1dc6cb7446e0..500bc7e40309 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -1377,67 +1377,71 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
> pcache_info = vegam_cache_info;
> num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
> break;
> - case CHIP_VEGA10:
> - pcache_info = vega10_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
> - break;
> - case CHIP_VEGA12:
> - pcache_info = vega12_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
> - break;
> - case CHIP_VEGA20:
> - case CHIP_ARCTURUS:
> - pcache_info = vega20_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
> - break;
> - case CHIP_ALDEBARAN:
> - pcache_info = aldebaran_cache_info;
> - num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
> - break;
> - case CHIP_RAVEN:
> - pcache_info = raven_cache_info;
> - num_of_cache_types = ARRAY_SIZE(raven_cache_info);
> - break;
> - case CHIP_RENOIR:
> - pcache_info = renoir_cache_info;
> - num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
> - break;
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_CYAN_SKILLFISH:
> - pcache_info = navi10_cache_info;
> - num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
> - break;
> - case CHIP_NAVI14:
> - pcache_info = navi14_cache_info;
> - num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
> - break;
> - case CHIP_SIENNA_CICHLID:
> - pcache_info = sienna_cichlid_cache_info;
> - num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
> - break;
> - case CHIP_NAVY_FLOUNDER:
> - pcache_info = navy_flounder_cache_info;
> - num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
> - break;
> - case CHIP_DIMGREY_CAVEFISH:
> - pcache_info = dimgrey_cavefish_cache_info;
> - num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
> - break;
> - case CHIP_VANGOGH:
> - pcache_info = vangogh_cache_info;
> - num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
> - break;
> - case CHIP_BEIGE_GOBY:
> - pcache_info = beige_goby_cache_info;
> - num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
> - break;
> - case CHIP_YELLOW_CARP:
> - pcache_info = yellow_carp_cache_info;
> - num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
> - break;
> default:
> - return -EINVAL;
> + switch(kdev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + pcache_info = vega10_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
> + break;
> + case IP_VERSION(9, 2, 1):
> + pcache_info = vega12_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
> + break;
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 4, 1):
> + pcache_info = vega20_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
> + break;
> + case IP_VERSION(9, 4, 2):
> + pcache_info = aldebaran_cache_info;
> + num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
> + break;
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + pcache_info = raven_cache_info;
> + num_of_cache_types = ARRAY_SIZE(raven_cache_info);
> + break;
> + case IP_VERSION(9, 3, 0):
> + pcache_info = renoir_cache_info;
> + num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
> + break;
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 3):
> + pcache_info = navi10_cache_info;
> + num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
> + break;
> + case IP_VERSION(10, 1, 1):
> + pcache_info = navi14_cache_info;
> + num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
> + break;
> + case IP_VERSION(10, 3, 0):
> + pcache_info = sienna_cichlid_cache_info;
> + num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
> + break;
> + case IP_VERSION(10, 3, 2):
> + pcache_info = navy_flounder_cache_info;
> + num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
> + break;
> + case IP_VERSION(10, 3, 4):
> + pcache_info = dimgrey_cavefish_cache_info;
> + num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
> + break;
> + case IP_VERSION(10, 3, 1):
> + pcache_info = vangogh_cache_info;
> + num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
> + break;
> + case IP_VERSION(10, 3, 5):
> + pcache_info = beige_goby_cache_info;
> + num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
> + break;
> + case IP_VERSION(10, 3, 3):
> + pcache_info = yellow_carp_cache_info;
> + num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
> + break;
> + default:
> + return -EINVAL;
> + }
> }
>
> *size_filled = 0;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> index 0a60317509c8..8a39494fa093 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
> @@ -1947,31 +1947,39 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
> device_queue_manager_init_vi_tonga(&dqm->asic_ops);
> break;
>
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_ALDEBARAN:
> - device_queue_manager_init_v9(&dqm->asic_ops);
> - break;
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - device_queue_manager_init_v10_navi10(&dqm->asic_ops);
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dev->device_info->asic_family);
> - goto out_free;
> + switch (dev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + device_queue_manager_init_v9(&dqm->asic_ops);
> + break;
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
This could probably be replaced with an if (ip_version >= X) kind of
construct. That way you don't need to list every individual supported
chip everywhere. Minor version changes often don't require any changes
anyway. Instead of the default case, you could have a check for version
>= IP_VERSION(11,0,0) (for now) expecting that a major version bump will
probably require some attention. But minor version changes can probably
be supported without changing anything (here and many other places where
we currently have switch (asic_family).
Regards,
Felix
> + device_queue_manager_init_v10_navi10(&dqm->asic_ops);
> + break;
> + default:
> + if (dev->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dev->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dev->device_info->asic_family);
> + goto out_free;
> + }
> }
>
> if (init_mqd_managers(dqm))
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
> index 2e86692def19..6c56e43e2f7b 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
> @@ -406,29 +406,37 @@ int kfd_init_apertures(struct kfd_process *process)
> case CHIP_VEGAM:
> kfd_init_apertures_vi(pdd, id);
> break;
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_ALDEBARAN:
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - kfd_init_apertures_v9(pdd, id);
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dev->device_info->asic_family);
> - return -EINVAL;
> + switch (dev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
> + kfd_init_apertures_v9(pdd, id);
> + break;
> + default:
> + if (dev->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dev->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dev->device_info->asic_family);
> + return -EINVAL;
> + }
> }
>
> if (!dev->use_iommu_v2) {
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> index e547f1f8c49f..0bee4b965e1f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
> @@ -236,31 +236,39 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
> case CHIP_VEGAM:
> pm->pmf = &kfd_vi_pm_funcs;
> break;
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - pm->pmf = &kfd_v9_pm_funcs;
> - break;
> - case CHIP_ALDEBARAN:
> - pm->pmf = &kfd_aldebaran_pm_funcs;
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dqm->dev->device_info->asic_family);
> - return -EINVAL;
> + switch (dqm->dev->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
> + pm->pmf = &kfd_v9_pm_funcs;
> + break;
> + case IP_VERSION(9, 4, 2):
> + pm->pmf = &kfd_aldebaran_pm_funcs;
> + break;
> + default:
> + if (dqm->dev->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dqm->dev->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dqm->dev->device_info->asic_family);
> + return -EINVAL;
> + }
> }
>
> pm->dqm = dqm;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index ae7c9944dc4a..5353f43c67f3 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1425,30 +1425,38 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
> HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
> HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
> break;
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RENOIR:
> - case CHIP_ARCTURUS:
> - case CHIP_ALDEBARAN:
> - case CHIP_NAVI10:
> - case CHIP_NAVI12:
> - case CHIP_NAVI14:
> - case CHIP_SIENNA_CICHLID:
> - case CHIP_NAVY_FLOUNDER:
> - case CHIP_VANGOGH:
> - case CHIP_DIMGREY_CAVEFISH:
> - case CHIP_BEIGE_GOBY:
> - case CHIP_YELLOW_CARP:
> - case CHIP_CYAN_SKILLFISH:
> - dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
> - HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
> - HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
> - break;
> default:
> - WARN(1, "Unexpected ASIC family %u",
> - dev->gpu->device_info->asic_family);
> + switch (dev->gpu->adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(9, 0, 1):
> + case IP_VERSION(9, 2, 1):
> + case IP_VERSION(9, 4, 0):
> + case IP_VERSION(9, 1, 0):
> + case IP_VERSION(9, 2, 2):
> + case IP_VERSION(9, 3, 0):
> + case IP_VERSION(9, 4, 1):
> + case IP_VERSION(9, 4, 2):
> + case IP_VERSION(10, 1, 10):
> + case IP_VERSION(10, 1, 2):
> + case IP_VERSION(10, 1, 1):
> + case IP_VERSION(10, 3, 0):
> + case IP_VERSION(10, 3, 2):
> + case IP_VERSION(10, 3, 1):
> + case IP_VERSION(10, 3, 4):
> + case IP_VERSION(10, 3, 5):
> + case IP_VERSION(10, 3, 3):
> + case IP_VERSION(10, 1, 3):
> + dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
> + HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
> + HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
> + break;
> + default:
> + if (dev->gpu->adev->ip_versions[GC_HWIP][0])
> + WARN(1, "Unexpected GC HWIP version %06x",
> + dev->gpu->adev->ip_versions[GC_HWIP][0]);
> + else
> + WARN(1, "Unexpected ASIC family %u",
> + dev->gpu->device_info->asic_family);
> + }
> }
>
> /*
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-11-08 22:29 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-11-05 19:58 [PATCH 1/2] drm/amdkfd: convert to IP-based version checking Graham Sider
2021-11-05 19:58 ` [PATCH 2/2] drm/amdkfd: convert misc checks to IP " Graham Sider
2021-11-08 22:21 ` Felix Kuehling
2021-11-08 22:29 ` [PATCH 1/2] drm/amdkfd: convert to IP-based " Felix Kuehling
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