From: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Thierry Reding
<thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Jonathan Hunter
<jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver
Date: Wed, 14 Feb 2018 18:42:15 +0300 [thread overview]
Message-ID: <ea94ef04-2eda-51c8-b485-e8c8063f2598@gmail.com> (raw)
In-Reply-To: <20180214111546.GR5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
On 14.02.2018 14:15, Peter De Schrijver wrote:
> On Tue, Feb 13, 2018 at 11:30:39AM +0100, Thierry Reding wrote:
>>> }
>>
>> It's odd that we don't have an MC clock on Tegra2. I wonder if perhaps
>> we just never implemented one, or it uses one which is always on by
>> default. Cc Peter to see if he knows.
>
> We do, it has DT ID TEGRA20_CLK_MC. However, it looks like the modeling is
> incorrect for Tegra20. Unlike on Tegra30 where the MC clock can be either
> half or the same as the EMC clock, it is always half the EMC clock on
> Tegra20. This happens to work because we likely never change the MC clock
> and the non-existing bit just reads as 0, which means half the MC clock.
Yes, and also that clock isn't specified in DT for MC. So probably we would have
to use clk_get_sys even if it was implemented correctly.
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver
Date: Wed, 14 Feb 2018 18:42:15 +0300 [thread overview]
Message-ID: <ea94ef04-2eda-51c8-b485-e8c8063f2598@gmail.com> (raw)
In-Reply-To: <20180214111546.GR5850@tbergstrom-lnx.Nvidia.com>
On 14.02.2018 14:15, Peter De Schrijver wrote:
> On Tue, Feb 13, 2018 at 11:30:39AM +0100, Thierry Reding wrote:
>>> }
>>
>> It's odd that we don't have an MC clock on Tegra2. I wonder if perhaps
>> we just never implemented one, or it uses one which is always on by
>> default. Cc Peter to see if he knows.
>
> We do, it has DT ID TEGRA20_CLK_MC. However, it looks like the modeling is
> incorrect for Tegra20. Unlike on Tegra30 where the MC clock can be either
> half or the same as the EMC clock, it is always half the EMC clock on
> Tegra20. This happens to work because we likely never change the MC clock
> and the non-existing bit just reads as 0, which means half the MC clock.
Yes, and also that clock isn't specified in DT for MC. So probably we would have
to use clk_get_sys even if it was implemented correctly.
next prev parent reply other threads:[~2018-02-14 15:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-12 17:06 [PATCH v2 0/2] Memory controller hot reset Dmitry Osipenko
2018-02-12 17:06 ` Dmitry Osipenko
2018-02-12 17:06 ` [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver Dmitry Osipenko
[not found] ` <148ce8c56ad764fc8133e0d97e43f9639cae15ff.1518452709.git.digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-02-13 10:30 ` Thierry Reding
2018-02-13 10:30 ` Thierry Reding
2018-02-14 11:15 ` Peter De Schrijver
2018-02-14 11:15 ` Peter De Schrijver
[not found] ` <20180214111546.GR5850-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2018-02-14 15:42 ` Dmitry Osipenko [this message]
2018-02-14 15:42 ` Dmitry Osipenko
2018-02-19 2:04 ` Dmitry Osipenko
2018-02-19 2:16 ` Dmitry Osipenko
[not found] ` <cover.1518452709.git.digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-02-12 17:06 ` [PATCH v2 2/2] memory: tegra: Introduce memory client hot reset API Dmitry Osipenko
2018-02-12 17:06 ` Dmitry Osipenko
2018-02-13 11:24 ` Thierry Reding
2018-02-19 12:35 ` Dmitry Osipenko
2018-02-19 12:44 ` Dmitry Osipenko
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