[LTP] [PATCH v16] high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

[LTP] [PATCH v16] high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

[Piotr Kubaj]

Verify for all online logical CPUs that their highest performance value are
the same for HWP Capability MSR 0x771 and CPPC sysfs file.

On HWP-capable x86 platforms the acpi_cppc/highest_perf sysfs attribute is
expected to reflect the same highest-performance value that firmware
programs into the HWP Capabilities MSR (0x771, bits 7:0). A mismatch
between the two interfaces indicates a kernel regression in how CPPC
values are exposed to userspace, and would break tools (e.g. cpupower,
intel_pstate tuning scripts) that rely on the sysfs interface to make
frequency-scaling decisions.

The test is valid only for Intel platforms.

Signed-off-by: Piotr Kubaj <piotr.kubaj@intel.com>
---
Previously wrong patch was sent - the older one with mismatch array.
Pointed out by the AI bot.
 runtest/power_management_tests                |   1 +
 testcases/kernel/power_management/.gitignore  |   1 +
 .../power_management/high_freq_hwp_cap_cppc.c | 128 ++++++++++++++++++
 3 files changed, 130 insertions(+)
 create mode 100644 testcases/kernel/power_management/.gitignore
 create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c

diff --git a/runtest/power_management_tests b/runtest/power_management_tests
index b670da6ec..4da57ee72 100644
--- a/runtest/power_management_tests
+++ b/runtest/power_management_tests
@@ -1,4 +1,5 @@
 #POWER_MANAGEMENT
+high_freq_hwp_cap_cppc high_freq_hwp_cap_cppc
 runpwtests03 runpwtests03.sh
 runpwtests04 runpwtests04.sh
 runpwtests06 runpwtests06.sh
diff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore
new file mode 100644
index 000000000..03f0c83e4
--- /dev/null
+++ b/testcases/kernel/power_management/.gitignore
@@ -0,0 +1 @@
+high_freq_hwp_cap_cppc
diff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
new file mode 100644
index 000000000..19c0fc8f2
--- /dev/null
+++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Piotr Kubaj <piotr.kubaj@intel.com>
+ */
+
+/*\
+ * Verify for all online logical CPUs that their highest performance value are
+ * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
+ *
+ * On HWP-capable x86 platforms the acpi_cppc/highest_perf sysfs attribute is
+ * expected to reflect the same highest-performance value that firmware
+ * programs into the HWP Capabilities MSR (0x771, bits 7:0). A mismatch
+ * between the two interfaces indicates a kernel regression in how CPPC
+ * values are exposed to userspace, and would break tools (e.g. cpupower,
+ * intel_pstate tuning scripts) that rely on the sysfs interface to make
+ * frequency-scaling decisions.
+ *
+ * The test needs root because reading /dev/cpu/N/msr needs CAP_SYS_RAWIO /
+ * root.
+ */
+
+#include "tst_test.h"
+#include "tst_safe_prw.h"
+
+#if defined(__i386__) || defined(__x86_64__)
+#include "lapi/cpuid.h"
+
+#define MSR_HWP_CAPABILITIES	0x771
+#define HIGHEST_PERF_MASK	0xFF
+
+#define CPUID_LEAF_THERMAL	0x6
+#define CPUID_HWP_BIT		(1 << 7)
+
+static int nproc;
+static int fd = -1;
+
+static void setup(void)
+{
+	unsigned int eax, ebx, ecx, edx;
+
+	__cpuid_count(CPUID_LEAF_THERMAL, 0, eax, ebx, ecx, edx);
+	if (!(eax & CPUID_HWP_BIT))
+		tst_brk(TCONF, "HWP not supported (MSR 0x771 unavailable)");
+
+	if (access("/dev/cpu/0/msr", F_OK) == -1)
+		tst_brk(TCONF | TERRNO, "msr driver not loaded");
+
+	if (access("/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf", F_OK) == -1)
+		tst_brk(TCONF | TERRNO, "CPPC sysfs not available");
+
+	nproc = tst_ncpus_conf();
+}
+
+static void cleanup(void)
+{
+	if (fd != -1)
+		SAFE_CLOSE(fd);
+}
+
+static void run(void)
+{
+	bool status = true;
+	char path[PATH_MAX];
+
+	for (int i = 0; i < nproc; i++) {
+		int online = 1;
+		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
+
+		if (i) {
+			snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/online", i);
+			SAFE_FILE_SCANF(path, "%d", &online);
+		}
+
+		if (!online) {
+			tst_res(TINFO, "CPU%d offline, skipping", i);
+			continue;
+		}
+
+		snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
+		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);
+		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
+
+		snprintf(path, sizeof(path), "/dev/cpu/%d/msr", i);
+		fd = SAFE_OPEN(path, O_RDONLY);
+
+		SAFE_PREAD(1, fd, &msr_highest_perf, sizeof(msr_highest_perf), MSR_HWP_CAPABILITIES);
+		SAFE_CLOSE(fd);
+		msr_highest_perf &= HIGHEST_PERF_MASK;
+		tst_res(TDEBUG, "%s: %llu", path, msr_highest_perf);
+
+		bool match = msr_highest_perf == sysfs_highest_perf;
+
+		if (!match) {
+			tst_res(TINFO, "cpu%d: sysfs=%llu MSR=%llu",
+				i, sysfs_highest_perf, msr_highest_perf);
+			status = false;
+		}
+
+		tst_res(TINFO, "cpu%d: %s", i, match ? "OK" : "MISMATCH");
+	}
+
+	if (status)
+		tst_res(TPASS, "Sysfs and MSR values are equal");
+	else
+		tst_res(TFAIL, "Highest performance values differ between sysfs and MSR");
+}
+
+static struct tst_test test = {
+//	.needs_cpu_vendor = "GenuineIntel",
+	.needs_kconfigs = (const char *const []) {
+		"CONFIG_ACPI_CPPC_LIB",
+		"CONFIG_X86_MSR",
+		NULL
+	},
+	.needs_root = 1,
+	.setup = setup,
+	.cleanup = cleanup,
+	.supported_archs = (const char *const []) {
+		"x86",
+		"x86_64",
+		NULL
+	},
+	.test_all = run
+};
+
+#else
+TST_TEST_TCONF("test requires x86");
+#endif
-- 
2.47.3

---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
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Re: [LTP] high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

[linuxtestproject.agent]

Hi Piotr,

On Wed, Jun 10, 2026 at 03:30:49PM +0200, Piotr Kubaj wrote:
> high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

> +//	.needs_cpu_vendor = "GenuineIntel",

This field does not exist in the LTP framework. Is this leftover from
an earlier prototype? Commented-out code should not be committed.

If the intent is to restrict to Intel, the existing CPUID HWP check
in setup() already serves that purpose since HWP is Intel-specific.

> +static void run(void)
> +{
> +	bool status = true;

> +		bool match = msr_highest_perf == sysfs_highest_perf;
> +
> +		if (!match) {
> +			tst_res(TINFO, "cpu%d: sysfs=%llu MSR=%llu",
> +				i, sysfs_highest_perf, msr_highest_perf);
> +			status = false;
> +		}
> +
> +		tst_res(TINFO, "cpu%d: %s", i, match ? "OK" : "MISMATCH");
> +	}
> +
> +	if (status)
> +		tst_res(TPASS, "Sysfs and MSR values are equal");
> +	else
> +		tst_res(TFAIL, "Highest performance values differ between sysfs and MSR");

Results should be reported directly where the outcome is determined,
not accumulated in a flag and reported at the end. Per-CPU mismatches
are logged as TINFO, meaning they won't appear as test failures in
result summaries.

Could this report TFAIL directly for each mismatched CPU and TPASS
once at the end if all matched? Something like:

    if (msr_highest_perf != sysfs_highest_perf) {
            tst_res(TFAIL, "cpu%d: sysfs=%llu MSR=%llu",
                    i, sysfs_highest_perf, msr_highest_perf);
            status = false;
    }

    ...

    if (status)
            tst_res(TPASS, "...");

That way each failing CPU is a proper TFAIL, and the redundant
second TINFO on line 99 can be dropped as well.

Verdict: Needs revision

---
Note:

The agent can sometimes produce false positives although often its
findings are genuine. If you find issues with the review, please
comment this email or ignore the suggestions.

Regards,
LTP AI Reviewer

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Re: [LTP] high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

[Kubaj, Piotr]

2026-06-10 (水) の 13:43 +0000 に linuxtestproject.agent@gmail.com
さんは書きました:
> Hi Piotr,
> 
> On Wed, Jun 10, 2026 at 03:30:49PM +0200, Piotr Kubaj wrote:
> > high_freq_hwp_cap_cppc.c: new test for testing
> > acpi_cppc/highest_perf
> 
> > +//	.needs_cpu_vendor = "GenuineIntel",
> 
> This field does not exist in the LTP framework. Is this leftover from
> an earlier prototype? Commented-out code should not be committed.
> 
> If the intent is to restrict to Intel, the existing CPUID HWP check
> in setup() already serves that purpose since HWP is Intel-specific.

The field is to be uncommented once the patch for its addition is
pushed.
> 
> > +static void run(void)
> > +{
> > +	bool status = true;
> 
> > +		bool match = msr_highest_perf ==
> > sysfs_highest_perf;
> > +
> > +		if (!match) {
> > +			tst_res(TINFO, "cpu%d: sysfs=%llu
> > MSR=%llu",
> > +				i, sysfs_highest_perf,
> > msr_highest_perf);
> > +			status = false;
> > +		}
> > +
> > +		tst_res(TINFO, "cpu%d: %s", i, match ? "OK" :
> > "MISMATCH");
> > +	}
> > +
> > +	if (status)
> > +		tst_res(TPASS, "Sysfs and MSR values are equal");
> > +	else
> > +		tst_res(TFAIL, "Highest performance values differ
> > between sysfs and MSR");
> 
> Results should be reported directly where the outcome is determined,
> not accumulated in a flag and reported at the end. Per-CPU mismatches
> are logged as TINFO, meaning they won't appear as test failures in
> result summaries.
> 
> Could this report TFAIL directly for each mismatched CPU and TPASS
> once at the end if all matched? Something like:
> 
>     if (msr_highest_perf != sysfs_highest_perf) {
>             tst_res(TFAIL, "cpu%d: sysfs=%llu MSR=%llu",
>                     i, sysfs_highest_perf, msr_highest_perf);
>             status = false;
>     }
> 
>     ...
> 
>     if (status)
>             tst_res(TPASS, "...");
> 
> That way each failing CPU is a proper TFAIL, and the redundant
> second TINFO on line 99 can be dropped as well.

That way of reporting was suggested before.

> 
> Verdict: Needs revision
> 
> ---
> Note:
> 
> The agent can sometimes produce false positives although often its
> findings are genuine. If you find issues with the review, please
> comment this email or ignore the suggestions.
> 
> Regards,
> LTP AI Reviewer
---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

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[LTP] [PATCH v15] high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

[Piotr Kubaj]

Verify for all online logical CPUs that their highest performance value are
the same for HWP Capability MSR 0x771 and CPPC sysfs file.

On HWP-capable x86 platforms the acpi_cppc/highest_perf sysfs attribute is
expected to reflect the same highest-performance value that firmware
programs into the HWP Capabilities MSR (0x771, bits 7:0). A mismatch
between the two interfaces indicates a kernel regression in how CPPC
values are exposed to userspace, and would break tools (e.g. cpupower,
intel_pstate tuning scripts) that rely on the sysfs interface to make
frequency-scaling decisions.

The test is valid only for Intel platforms.

Signed-off-by: Piotr Kubaj <piotr.kubaj@intel.com>
---
1. Sets the new needs_cpu_vendor tst_test field - still commented out,
because the commit introducing this field is still not pushed. Please
uncomment it when pushing.
2. Addresses review issues from the bot.
3. Drops mismatch[] array, which is now unnecessary.
 runtest/power_management_tests                |   1 +
 testcases/kernel/power_management/.gitignore  |   1 +
 .../power_management/high_freq_hwp_cap_cppc.c | 112 ++++++++++++++++++
 3 files changed, 114 insertions(+)
 create mode 100644 testcases/kernel/power_management/.gitignore
 create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c

diff --git a/runtest/power_management_tests b/runtest/power_management_tests
index b670da6ec..4da57ee72 100644
--- a/runtest/power_management_tests
+++ b/runtest/power_management_tests
@@ -1,4 +1,5 @@
 #POWER_MANAGEMENT
+high_freq_hwp_cap_cppc high_freq_hwp_cap_cppc
 runpwtests03 runpwtests03.sh
 runpwtests04 runpwtests04.sh
 runpwtests06 runpwtests06.sh
diff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore
new file mode 100644
index 000000000..03f0c83e4
--- /dev/null
+++ b/testcases/kernel/power_management/.gitignore
@@ -0,0 +1 @@
+high_freq_hwp_cap_cppc
diff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
new file mode 100644
index 000000000..d06d9302f
--- /dev/null
+++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Piotr Kubaj <piotr.kubaj@intel.com>
+ */
+
+/*\
+ * Verify for all online logical CPUs that their highest performance value are
+ * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
+ *
+ * On HWP-capable x86 platforms the acpi_cppc/highest_perf sysfs attribute is
+ * expected to reflect the same highest-performance value that firmware
+ * programs into the HWP Capabilities MSR (0x771, bits 7:0). A mismatch
+ * between the two interfaces indicates a kernel regression in how CPPC
+ * values are exposed to userspace, and would break tools (e.g. cpupower,
+ * intel_pstate tuning scripts) that rely on the sysfs interface to make
+ * frequency-scaling decisions.
+ */
+
+#include "tst_test.h"
+#include "tst_safe_prw.h"
+
+#define MSR_HWP_CAPABILITIES	0x771
+#define HIGHEST_PERF_MASK	0xFF
+
+static int nproc;
+static int fd = -1;
+static int *mismatch;
+
+static void setup(void)
+{
+	if (access("/dev/cpu/0/msr", F_OK) == -1)
+		tst_brk(TCONF | TERRNO, "msr driver not loaded");
+
+	if (access("/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf", F_OK) == -1)
+		tst_brk(TCONF | TERRNO, "CPPC sysfs not available");
+
+	nproc = tst_ncpus_conf();
+	mismatch = SAFE_CALLOC(nproc, sizeof(int));
+}
+
+static void cleanup(void)
+{
+	if (fd != -1)
+		SAFE_CLOSE(fd);
+
+	free(mismatch);
+}
+
+static void run(void)
+{
+	bool status = true;
+	char path[PATH_MAX];
+
+	for (int i = 0; i < nproc; i++) {
+		int online = 1;
+		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
+
+		if (i) {
+			snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/online", i);
+			SAFE_FILE_SCANF(path, "%d", &online);
+		}
+
+		if (!online) {
+			tst_res(TINFO, "CPU%d offline, skipping", i);
+			continue;
+		}
+
+		snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
+		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);
+		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
+
+		snprintf(path, sizeof(path), "/dev/cpu/%d/msr", i);
+		fd = SAFE_OPEN(path, O_RDONLY);
+
+		SAFE_PREAD(1, fd, &msr_highest_perf, sizeof(msr_highest_perf), MSR_HWP_CAPABILITIES);
+		SAFE_CLOSE(fd);
+		msr_highest_perf &= HIGHEST_PERF_MASK;
+		tst_res(TDEBUG, "%s: %llu", path, msr_highest_perf);
+
+		if (msr_highest_perf != sysfs_highest_perf) {
+			tst_res(TINFO, "cpu%d: sysfs=%llu MSR=%llu",
+				i, sysfs_highest_perf, msr_highest_perf);
+			mismatch[i] = 1;
+			status = false;
+		}
+	}
+
+	for (int i = 0; i < nproc; i++)
+		tst_res(TINFO, "cpu%d: %s", i, mismatch[i] ? "MISMATCH" : "OK");
+
+	if (status)
+		tst_res(TPASS, "Sysfs and MSR values are equal");
+	else
+		tst_res(TFAIL, "Highest performance values differ between sysfs and MSR");
+}
+
+static struct tst_test test = {
+	.needs_kconfigs = (const char *const []) {
+		"CONFIG_ACPI_CPPC_LIB",
+		"CONFIG_X86_MSR",
+		NULL
+	},
+	.needs_root = 1,
+	.setup = setup,
+	.cleanup = cleanup,
+	.supported_archs = (const char *const []) {
+		"x86",
+		"x86_64",
+		NULL
+	},
+	.test_all = run
+};
-- 
2.47.3

---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.


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Re: [LTP] high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

[linuxtestproject.agent]

Hi Piotr,

On Wed, 10 Jun 2026 13:18:10 +0200, Piotr Kubaj wrote:
> high_freq_hwp_cap_cppc.c: new test for testing acpi_cppc/highest_perf

> +static void run(void)
> +{
> +	bool status = true;
> +	char path[PATH_MAX];
> +
> +	for (int i = 0; i < nproc; i++) {

The static `mismatch` array is zeroed once by SAFE_CALLOC in setup(),
but run() only ever sets elements to 1 and never resets them. When the
test is invoked with `-i N`, stale entries from a previous iteration
survive into the next one.

For example, if CPU 2 mismatches on iteration 1 but matches on
iteration 2, the summary loop still prints "cpu2: MISMATCH" while the
verdict says TPASS. Adding a memset at the top of run() would fix it:

    memset(mismatch, 0, nproc * sizeof(int));

> +		if (msr_highest_perf != sysfs_highest_perf) {
> +			tst_res(TINFO, "cpu%d: sysfs=%llu MSR=%llu",
> +				i, sysfs_highest_perf, msr_highest_perf);
> +			mismatch[i] = 1;
> +			status = false;
> +		}

Per-CPU mismatches are reported with TINFO and the actual TFAIL is
deferred to the end of run() via the `status` flag. LTP convention is
to report results directly where they are determined. Could the
mismatch be reported as TFAIL inline (dropping the `status` flag and
the `mismatch` array), with TPASS emitted at the end only when no
mismatch was found?

Verdict: Needs revision

---
Note:

The agent can sometimes produce false positives although often its
findings are genuine. If you find issues with the review, please
comment this email or ignore the suggestions.

Regards,
LTP AI Reviewer

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Mailing list info: https://lists.linux.it/listinfo/ltp