From: "Kathpalia, Tanmay" <tanmay.kathpalia@altera.com>
To: tze.yee.ng@altera.com, u-boot@lists.denx.de
Cc: Peng Fan <peng.fan@nxp.com>,
Jaehoon Chung <jh80.chung@samsung.com>,
Tom Rini <trini@konsulko.com>,
Marek Vasut <marek.vasut+socfpga@mailbox.org>,
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
Tien Fong Chee <tien.fong.chee@altera.com>,
Ilias Apalodimas <ilias.apalodimas@linaro.org>,
u-boot@lists.u-boot-project.org,
Chen Huei Lok <chen.huei.lok@altera.com>,
Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,
Dinesh Maniyam <dinesh.maniyam@altera.com>,
Boon Khai Ng <boon.khai.ng@altera.com>,
Kok Kiang Hea <kok.kiang.hea@altera.com>
Subject: Re: [PATCH 3/4] mmc: sdhci-cadence6: configure PHY control register per speed mode
Date: Sun, 13 Sep 2026 02:36:52 +0530 [thread overview]
Message-ID: <ec129b92-3fb2-4f1b-bc9d-2a901163fd76@altera.com> (raw)
In-Reply-To: <15e724cc7260e5f280ccced5b453b2978490df79.1787710268.git.tze.yee.ng@altera.com>
Hi Tze,
On 26-08-2026 08:23, tze.yee.ng@altera.com wrote:
> From: Tze Yee Ng <tze.yee.ng@altera.com>
>
> The PHY control register (0x2080) holds phony_dqs_timing (bits [9:4]),
> which shifts the read-capture strobe relative to the data slices.
>
> Extend the per-mode PHY configuration arrays with a "cdns,phy-ctrl-*"
> entry (default 0x41F0) and program register 0x2080 during PHY
> adjustment. This lets each speed mode - and each board via device tree -
> select an appropriate value.
>
> Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
> ---
The PHY_CTRL default needs to be corrected. All six tables also use the
same 0x41F0, so this is not actually per-mode.
Please fix the defaults.
Regards,
Tanmay
next prev parent reply other threads:[~2026-09-12 21:07 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-26 2:52 [PATCH 0/4] mmc: sdhci-cadence6: harden PHY config tables and enable Agilex5 UHS modes tze.yee.ng
2026-08-26 2:53 ` [PATCH 1/4] mmc: sdhci-cadence6: use const PHY config tables with per-call overrides tze.yee.ng
2026-09-12 20:26 ` Kathpalia, Tanmay
2026-09-21 3:39 ` NG, TZE YEE
2026-08-26 2:53 ` [PATCH 2/4] mmc: sdhci-cadence6: name PHY and controller config table slots tze.yee.ng
2026-09-12 20:36 ` Kathpalia, Tanmay
2026-09-21 3:40 ` NG, TZE YEE
2026-08-26 2:53 ` [PATCH 3/4] mmc: sdhci-cadence6: configure PHY control register per speed mode tze.yee.ng
2026-09-12 21:06 ` Kathpalia, Tanmay [this message]
2026-09-21 3:50 ` NG, TZE YEE
2026-10-03 18:53 ` Kathpalia, Tanmay
2026-10-05 8:06 ` NG, TZE YEE
2026-08-26 2:53 ` [PATCH 4/4] arm: dts: socfpga: agilex5: add SD/eMMC UHS PHY timing tze.yee.ng
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