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From: tze.yee.ng@altera.com
To: u-boot@lists.denx.de
Cc: Tanmay Kathpalia <tanmay.kathpalia@altera.com>,
	Peng Fan <peng.fan@nxp.com>,
	Jaehoon Chung <jh80.chung@samsung.com>,
	Tom Rini <trini@konsulko.com>,
	Marek Vasut <marek.vasut+socfpga@mailbox.org>,
	Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,
	Tien Fong Chee <tien.fong.chee@altera.com>,
	Ilias Apalodimas <ilias.apalodimas@linaro.org>,
	u-boot@lists.u-boot-project.org,
	Chen Huei Lok <chen.huei.lok@altera.com>,
	Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,
	Dinesh Maniyam <dinesh.maniyam@altera.com>,
	Boon Khai Ng <boon.khai.ng@altera.com>,
	Kok Kiang Hea <kok.kiang.hea@altera.com>
Subject: [PATCH 0/4] mmc: sdhci-cadence6: harden PHY config tables and enable Agilex5 UHS modes
Date: Wed, 26 Aug 2026 10:52:59 +0800	[thread overview]
Message-ID: <cover.1787710268.git.tze.yee.ng@altera.com> (raw)

From: Tze Yee Ng <tze.yee.ng@altera.com>

This series hardens the per-mode PHY/controller configuration handling in
the Cadence SD6HC (v6) driver and then enables the UHS-I higher-speed
modes (SDR104 and DDR50, plus eMMC DDR52) on the Agilex5 SoCDK and its
013B and modular variants:

  - const config tables + per-call copies, so device-tree overrides can
    no longer mutate the shared defaults and leak between controllers;
  - named enum slots for the PHY/HRS config tables, so reordering or 
    inserting an entry cannot silently reprogram the wrong register
    (no functional change);
  - program the PHY control register (0x2080) per speed mode, with a
    per-mode / per-board device-tree override;
  - add the SDR104 (emmc-hs200) and DDR50 (emmc-ddr) PHY timing for the
    Agilex5 SoCDK, 013B and modular boards and advertise the matching
    sd-uhs-* / mmc-ddr-1_8v capabilities.

Dependencies
------------ 
The driver patches (1-3) apply on top of, and depend on, the fixes 
series (series=519635): 
  "mmc: sdhci-cadence6: fix PHY programming reliability" 

The HRS05 posted-write flush and the post-adjustment settle delay from
that series are required for reliable higher-speed operation.

The device-tree patch (4) additionally depends on two Agilex5 board
patches still under review, as it extends the .dts/.dtsi files they add:

  "arm: dts: socfpga: Add MDK support with external GPIO expander"
      - Tanmay Kathpalia (series=16401)
  "arm: dts: socfpga: Add Agilex5 E-Series 013B SoCDK variant"
      - Dinesh Maniyam (series=32177)

Tze Yee Ng (4):
  mmc: sdhci-cadence6: use const PHY config tables with per-call
    overrides
  mmc: sdhci-cadence6: name PHY and controller config table slots
  mmc: sdhci-cadence6: configure PHY control register per speed mode
  arm: dts: socfpga: agilex5: add SD/eMMC UHS PHY timing

 .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi |  13 ++
 .../socfpga_agilex5_socdk_013b-u-boot.dtsi    |  24 +++-
 arch/arm/dts/socfpga_agilex5_socdk_013b.dts   |   4 +-
 arch/arm/dts/socfpga_agilex5_socdk_emmc.dts   |  13 ++
 .../arm/dts/socfpga_agilex5_socdk_modular.dts |  20 +++
 drivers/mmc/sdhci-cadence6.c                  | 136 ++++++++++++------
 6 files changed, 166 insertions(+), 44 deletions(-)

-- 
2.43.7


             reply	other threads:[~2026-08-26  4:31 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-26  2:52 tze.yee.ng [this message]
2026-08-26  2:53 ` [PATCH 1/4] mmc: sdhci-cadence6: use const PHY config tables with per-call overrides tze.yee.ng
2026-09-12 20:26   ` Kathpalia, Tanmay
2026-09-21  3:39     ` NG, TZE YEE
2026-08-26  2:53 ` [PATCH 2/4] mmc: sdhci-cadence6: name PHY and controller config table slots tze.yee.ng
2026-09-12 20:36   ` Kathpalia, Tanmay
2026-09-21  3:40     ` NG, TZE YEE
2026-08-26  2:53 ` [PATCH 3/4] mmc: sdhci-cadence6: configure PHY control register per speed mode tze.yee.ng
2026-09-12 21:06   ` Kathpalia, Tanmay
2026-09-21  3:50     ` NG, TZE YEE
2026-10-03 18:53       ` Kathpalia, Tanmay
2026-10-05  8:06         ` NG, TZE YEE
2026-08-26  2:53 ` [PATCH 4/4] arm: dts: socfpga: agilex5: add SD/eMMC UHS PHY timing tze.yee.ng

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