RE: Lenovo LOQ rtw_8852be

[Ping-Ke Shih <pkshih@realtek.com>]

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Hi Ali,

> -----Original Message-----
> From: Ping-Ke Shih
> Sent: Tuesday, December 12, 2023 2:02 PM
> To: 'Ali Ghandour' <gandour.ali@gmail.com>
> Cc: linux-wireless@vger.kernel.org
> Subject: RE: Lenovo LOQ rtw_8852be
> 
> > -----Original Message-----
> > From: Ali Ghandour <gandour.ali@gmail.com>
> > Sent: Tuesday, December 12, 2023 1:36 PM
> > To: Ping-Ke Shih <pkshih@realtek.com>
> > Cc: linux-wireless@vger.kernel.org
> > Subject: Re: Lenovo LOQ rtw_8852be
> >
> > > Please try below workaround patch to ignore the setting. I have tried that, and
> > > in my side it still works without obvious problem. I will check internally to
> > > check how much this can affect. If not, I would ignore this if certain platform
> > > like yours can't access PCI space over 0x100.
> >
> > I was able to connect. Thanks a lot Ping-Ke!
> >
> 
> Good. Please use it as usual and monitor if it works stable. I would like
> take your results as reference to decide how I can modify the driver.
> 

After internal discussion, people suggest to implement DBI to access PCI config
space as attached patch. Please help to revert workaround and apply this one,
and give us kernel log to see if it works as expected.

Ping-Ke


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From 0974cd95c6cf3e6096035ee639354b69bd6ca954 Mon Sep 17 00:00:00 2001
From: Chin-Yen Lee <timlee@realtek.com>
Date: Fri, 15 Dec 2023 18:55:28 +0800
Subject: [PATCH] wifi: rtw89: pci: use DBI function for 8852AE/8852BE/8851BE

Sometimes driver can't use kernel api pci_read/write_config_byte
to access the pci config space of above address 0x100 due to
the negotiated pci setting. 8852AE/8852BE/8851BE provide another
way called dbi function, which belongs to wifi mac and could
access all pci config space for this case.

Change-Id: I34f4b70accfab24aec8ff33ddfdc9ee3a31e8e6a
Signed-off-by: Chin-Yen Lee <timlee@realtek.com>
---
 pci.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++--
 pci.h |  1 +
 2 files changed, 68 insertions(+), 2 deletions(-)

diff --git a/pci.c b/pci.c
index e66396dfecb7..c48cb9183c68 100644
--- a/pci.c
+++ b/pci.c
@@ -1907,22 +1907,87 @@ static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u
 	return 0;
 }
 
+static int rtw89_dbi_write8(struct rtw89_dev *rtwdev, u16 addr, u8 data)
+{
+	u16 addr_2lsb = addr & B_AX_DBI_2LSB;
+	u16 write_addr;
+	u8 flag;
+	int ret;
+
+	write_addr = addr & B_AX_DBI_ADDR_MSK;
+	write_addr |= u16_encode_bits(BIT(addr_2lsb), B_AX_DBI_WREN_MSK);
+	rtw89_write8(rtwdev, R_AX_DBI_WDATA + addr_2lsb, data);
+	rtw89_write16(rtwdev, R_AX_DBI_FLAG, write_addr);
+	rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_WFLAG >> 16);
+
+	ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10,
+				       10 * RTW89_PCI_WR_RETRY_CNT, false,
+				       rtwdev, R_AX_DBI_FLAG + 2);
+	if (ret)
+		rtw89_err(rtwdev, "failed to write DBI register, addr=0x%X\n",
+			  addr);
+
+	return ret;
+}
+
+static int rtw89_dbi_read8(struct rtw89_dev *rtwdev, u16 addr, u8 *value)
+{
+	u16 read_addr = addr & B_AX_DBI_ADDR_MSK;
+	u8 flag;
+	int ret;
+
+	rtw89_write16(rtwdev, R_AX_DBI_FLAG, read_addr);
+	rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_RFLAG >> 16);
+
+	ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10,
+				       10 * RTW89_PCI_WR_RETRY_CNT, false,
+				       rtwdev, R_AX_DBI_FLAG + 2);
+	if (ret) {
+		rtw89_err(rtwdev, "failed to read DBI register, addr=0x%X\n",
+			  addr);
+		return ret;
+	}
+
+	read_addr = R_AX_DBI_RDATA + (addr & 3);
+	*value = rtw89_read8(rtwdev, read_addr);
+
+	return 0;
+}
+
 static int rtw89_pci_write_config_byte(struct rtw89_dev *rtwdev, u16 addr,
 				       u8 data)
 {
 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
+	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
 	struct pci_dev *pdev = rtwpci->pdev;
+	int ret;
+
+	ret = pci_write_config_byte(pdev, addr, data);
+	if (!ret)
+		return 0;
 
-	return pci_write_config_byte(pdev, addr, data);
+	if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B)
+		ret = rtw89_dbi_write8(rtwdev, addr, data);
+
+	return ret;
 }
 
 static int rtw89_pci_read_config_byte(struct rtw89_dev *rtwdev, u16 addr,
 				      u8 *value)
 {
 	struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
+	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
 	struct pci_dev *pdev = rtwpci->pdev;
+	int ret;
 
-	return pci_read_config_byte(pdev, addr, value);
+	ret = pci_read_config_byte(pdev, addr, value);
+	if (!ret)
+		return 0;
+
+	if (chip_id == RTL8852A || chip_id == RTL8852B || chip_id == RTL8851B)
+		ret = rtw89_dbi_read8(rtwdev, addr, value);
+
+	return ret;
 }
 
 static int rtw89_pci_config_byte_set(struct rtw89_dev *rtwdev, u16 addr,
diff --git a/pci.h b/pci.h
index ca5de77fee90..1fb7c209fa0d 100644
--- a/pci.h
+++ b/pci.h
@@ -42,6 +42,7 @@
 #define B_AX_DBI_WFLAG			BIT(16)
 #define B_AX_DBI_WREN_MSK		GENMASK(15, 12)
 #define B_AX_DBI_ADDR_MSK		GENMASK(11, 2)
+#define B_AX_DBI_2LSB			GENMASK(1, 0)
 #define R_AX_DBI_WDATA			0x1094
 #define R_AX_DBI_RDATA			0x1098
 
-- 
2.25.1