[igt-dev] [PATCH i-g-t v4 1/4] test/perf: Add support for TGL in perf tests

[igt-dev] [PATCH i-g-t v4 1/4] test/perf: Add support for TGL in perf tests

[Umesh Nerlige Ramappa]

Add following changes to enable perf tests on TGL
- Support only a single OA format
- Add TGL metrics
- Update whitelist test case
- Cleanup mi-rpc test if it fails
- Skip unsupported test - gen8-unprivileged-single-ctx-counters

v2: Remove error cleanup in mi-rpc
v3: Use the right address for NOA WRITE (Lionel)

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 tests/perf.c | 61 +++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 46 insertions(+), 15 deletions(-)

diff --git a/tests/perf.c b/tests/perf.c
index 5ad8b2db..2b6be134 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -159,6 +159,15 @@ static struct oa_format gen8_oa_formats[I915_OA_FORMAT_MAX] = {
 		.b_off = 32, .n_b = 8, },
 };
 
+static struct oa_format gen12_oa_formats[I915_OA_FORMAT_MAX] = {
+	[I915_OA_FORMAT_A32u40_A4u32_B8_C8] = {
+		"A32u40_A4u32_B8_C8", .size = 256,
+		.a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
+		.a_off = 144, .n_a = 4, .first_a = 32,
+		.b_off = 192, .n_b = 8,
+		.c_off = 224, .n_c = 8, },
+};
+
 static bool hsw_undefined_a_counters[45] = {
 	[4] = true,
 	[6] = true,
@@ -206,7 +215,10 @@ get_oa_format(enum drm_i915_oa_format format)
 {
 	if (IS_HASWELL(devid))
 		return hsw_oa_formats[format];
-	return gen8_oa_formats[format];
+	else if (IS_GEN12(devid))
+		return gen12_oa_formats[format];
+	else
+		return gen8_oa_formats[format];
 }
 
 static void
@@ -945,6 +957,8 @@ init_sys_info(void)
 			test_set_uuid = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
 		} else if (IS_ICELAKE(devid)) {
 			test_set_uuid = "a291665e-244b-4b76-9b9a-01de9d3c8068";
+		} else if (IS_TIGERLAKE(devid)) {
+			test_set_uuid = "80a833f0-2504-4321-8894-e9277844ce7b";
 		} else {
 			igt_debug("unsupported GT\n");
 			return false;
@@ -3846,6 +3860,8 @@ test_whitelisted_registers_userspace_config(void)
 	uint32_t b_counters_regs[200];
 	uint32_t flex_regs[200];
 	uint32_t i;
+	uint32_t oa_start_trig1, oa_start_trig8;
+	uint32_t oa_report_trig1, oa_report_trig8;
 	uint64_t config_id;
 	char path[512];
 	int ret;
@@ -3869,14 +3885,26 @@ test_whitelisted_registers_userspace_config(void)
 	memset(&config, 0, sizeof(config));
 	memcpy(config.uuid, uuid, sizeof(config.uuid));
 
+	if (intel_gen(devid) >= 12) {
+		oa_start_trig1 = 0xd900;
+		oa_start_trig8 = 0xd91c;
+		oa_report_trig1 = 0xd920;
+		oa_report_trig8 = 0xd93c;
+	} else {
+		oa_start_trig1 = 0x2710;
+		oa_start_trig8 = 0x272c;
+		oa_report_trig1 = 0x2740;
+		oa_report_trig8 = 0x275c;
+	}
+
 	/* OASTARTTRIG[1-8] */
-	for (i = 0x2710; i <= 0x272c; i += 4) {
+	for (i = oa_start_trig1; i <= oa_start_trig8; i += 4) {
 		b_counters_regs[config.n_boolean_regs * 2] = i;
 		b_counters_regs[config.n_boolean_regs * 2 + 1] = 0;
 		config.n_boolean_regs++;
 	}
 	/* OAREPORTTRIG[1-8] */
-	for (i = 0x2740; i <= 0x275c; i += 4) {
+	for (i = oa_report_trig1; i <= oa_report_trig8; i += 4) {
 		b_counters_regs[config.n_boolean_regs * 2] = i;
 		b_counters_regs[config.n_boolean_regs * 2 + 1] = 0;
 		config.n_boolean_regs++;
@@ -3897,7 +3925,7 @@ test_whitelisted_registers_userspace_config(void)
 	i = 0;
 
 	/* NOA_WRITE */
-	mux_regs[i++] = 0x9800;
+	mux_regs[i++] = 0x9888;
 	mux_regs[i++] = 0;
 
 	if (IS_HASWELL(devid)) {
@@ -3922,10 +3950,6 @@ test_whitelisted_registers_userspace_config(void)
 		mux_regs[i++] = 0;
 	}
 
-	/* HALF_SLICE_CHICKEN2 (shared with kernel workaround) */
-	mux_regs[i++] = 0xE180;
-	mux_regs[i++] = 0;
-
 	if (IS_CHERRYVIEW(devid)) {
 		/* Cherryview specific. undocumented... */
 		mux_regs[i++] = 0x182300;
@@ -3934,12 +3958,17 @@ test_whitelisted_registers_userspace_config(void)
 		mux_regs[i++] = 0;
 	}
 
-	/* PERFCNT[12] */
-	mux_regs[i++] = 0x91B8;
-	mux_regs[i++] = 0;
-	/* PERFMATRIX */
-	mux_regs[i++] = 0x91C8;
-	mux_regs[i++] = 0;
+	if (intel_gen(devid) <= 11) {
+		/* HALF_SLICE_CHICKEN2 (shared with kernel workaround) */
+		mux_regs[i++] = 0xE180;
+		mux_regs[i++] = 0;
+		/* PERFCNT[12] */
+		mux_regs[i++] = 0x91B8;
+		mux_regs[i++] = 0;
+		/* PERFMATRIX */
+		mux_regs[i++] = 0x91C8;
+		mux_regs[i++] = 0;
+	}
 
 	config.mux_regs_ptr = (uintptr_t) mux_regs;
 	config.n_mux_regs = i / 2;
@@ -4170,8 +4199,10 @@ igt_main
 		 * functionality to HW filter timer reports for a specific
 		 * context (SKL+) can't stop multiple applications viewing
 		 * system-wide data via MI_REPORT_PERF_COUNT commands.
+		 *
+		 * For gen12 implement a separate test that uses only OAR
 		 */
-		igt_require(intel_gen(devid) >= 8);
+		igt_require(intel_gen(devid) >= 8 && intel_gen(devid) < 12);
 		gen8_test_single_ctx_render_target_writes_a_counter();
 	}
 
-- 
2.20.1

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[igt-dev] [PATCH i-g-t v4 2/4] test/perf: Dump the report and timestamp frequency for debug

[Umesh Nerlige Ramappa]

Add debug logs to view the reports in comparison with actual formats.
Log the timestamp frequency used to calculate the period exponents.

v2: Split debug patch from OAR test patch (Lionel)

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/perf.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index 2b6be134..506b64ec 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -210,6 +210,19 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
 static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
 				    enum drm_i915_oa_format format);
 
+static void
+dump_report(const uint32_t *report, uint32_t size, const char *message) {
+	uint32_t i;
+	igt_debug("%s\n", message);
+	for (i = 0; i < size; i += 4) {
+		igt_debug("%08x %08x %08x %08x\n",
+				report[i],
+				report[i + 1],
+				report[i + 2],
+				report[i + 3]);
+	}
+}
+
 static struct oa_format
 get_oa_format(enum drm_i915_oa_format format)
 {
@@ -874,6 +887,7 @@ init_sys_info(void)
 	igt_assert_neq(devid, 0);
 
 	timestamp_frequency = get_cs_timestamp_frequency();
+	igt_debug("timestamp_frequency = %lu\n", timestamp_frequency);
 	igt_assert_neq(timestamp_frequency, 0);
 
 	if (IS_HASWELL(devid)) {
@@ -1289,6 +1303,7 @@ read_2_oa_reports(int format_id,
 			igt_assert_eq(header->size, sample_size);
 
 			report = (const void *)(header + 1);
+			dump_report(report, 64, "oa-formats");
 
 			igt_debug("read report: reason = %x, timestamp = %x, exponent mask=%x\n",
 				  report[0], report[1], exponent_mask);
@@ -2856,6 +2871,7 @@ test_mi_rpc(void)
 	igt_assert_eq(ret, 0);
 
 	report32 = bo->virtual;
+	dump_report(report32, 64, "mi-rpc");
 	igt_assert_eq(report32[0], 0xdeadbeef); /* report ID */
 	igt_assert_neq(report32[1], 0); /* timestamp */
 
@@ -3335,11 +3351,13 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 			prev = report0_32;
 			ctx_id = prev[2];
 			igt_debug("MI_RPC(start) CTX ID: %u\n", ctx_id);
+			dump_report(report0_32, 64, "report0_32");
 
 			report1_32 = report0_32 + 64; /* 64 uint32_t = 256bytes offset */
 			igt_assert_eq(report1_32[0], 0xbeefbeef); /* report ID */
 			igt_assert_neq(report1_32[1], 0); /* timestamp */
 			ctx1_id = report1_32[2];
+			dump_report(report1_32, 64, "report1_32");
 
 			memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
 			accumulate_reports(&accumulator, report0_32, report1_32);
@@ -3434,6 +3452,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 				igt_assert_eq(header->size, sample_size);
 
 				report = (void *)(header + 1);
+				dump_report(report, 64, "OA report");
 
 				/* Don't expect zero for timestamps */
 				igt_assert_neq(report[1], 0);
-- 
2.20.1

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Re: [igt-dev] [PATCH i-g-t v4 2/4] test/perf: Dump the report and timestamp frequency for debug

[Lionel Landwerlin]

On 20/11/2019 02:07, Umesh Nerlige Ramappa wrote:
> Add debug logs to view the reports in comparison with actual formats.
> Log the timestamp frequency used to calculate the period exponents.
>
> v2: Split debug patch from OAR test patch (Lionel)
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>   tests/perf.c | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
>
> diff --git a/tests/perf.c b/tests/perf.c
> index 2b6be134..506b64ec 100644
> --- a/tests/perf.c
> +++ b/tests/perf.c
> @@ -210,6 +210,19 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
>   static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
>   				    enum drm_i915_oa_format format);
>   
> +static void
> +dump_report(const uint32_t *report, uint32_t size, const char *message) {
> +	uint32_t i;
> +	igt_debug("%s\n", message);
> +	for (i = 0; i < size; i += 4) {
> +		igt_debug("%08x %08x %08x %08x\n",
> +				report[i],
> +				report[i + 1],
> +				report[i + 2],
> +				report[i + 3]);
> +	}
> +}
> +
>   static struct oa_format
>   get_oa_format(enum drm_i915_oa_format format)
>   {
> @@ -874,6 +887,7 @@ init_sys_info(void)
>   	igt_assert_neq(devid, 0);
>   
>   	timestamp_frequency = get_cs_timestamp_frequency();
> +	igt_debug("timestamp_frequency = %lu\n", timestamp_frequency);
>   	igt_assert_neq(timestamp_frequency, 0);
>   
>   	if (IS_HASWELL(devid)) {
> @@ -1289,6 +1303,7 @@ read_2_oa_reports(int format_id,
>   			igt_assert_eq(header->size, sample_size);
>   
>   			report = (const void *)(header + 1);
> +			dump_report(report, 64, "oa-formats");
>   
>   			igt_debug("read report: reason = %x, timestamp = %x, exponent mask=%x\n",
>   				  report[0], report[1], exponent_mask);
> @@ -2856,6 +2871,7 @@ test_mi_rpc(void)
>   	igt_assert_eq(ret, 0);
>   
>   	report32 = bo->virtual;
> +	dump_report(report32, 64, "mi-rpc");
>   	igt_assert_eq(report32[0], 0xdeadbeef); /* report ID */
>   	igt_assert_neq(report32[1], 0); /* timestamp */
>   
> @@ -3335,11 +3351,13 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   			prev = report0_32;
>   			ctx_id = prev[2];
>   			igt_debug("MI_RPC(start) CTX ID: %u\n", ctx_id);
> +			dump_report(report0_32, 64, "report0_32");
>   
>   			report1_32 = report0_32 + 64; /* 64 uint32_t = 256bytes offset */
>   			igt_assert_eq(report1_32[0], 0xbeefbeef); /* report ID */
>   			igt_assert_neq(report1_32[1], 0); /* timestamp */
>   			ctx1_id = report1_32[2];
> +			dump_report(report1_32, 64, "report1_32");
>   
>   			memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
>   			accumulate_reports(&accumulator, report0_32, report1_32);
> @@ -3434,6 +3452,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   				igt_assert_eq(header->size, sample_size);
>   
>   				report = (void *)(header + 1);
> +				dump_report(report, 64, "OA report");
>   
>   				/* Don't expect zero for timestamps */
>   				igt_assert_neq(report[1], 0);


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Re: [igt-dev] [PATCH i-g-t v4 2/4] test/perf: Dump the report and timestamp frequency for debug

[Lionel Landwerlin]

On 20/11/2019 02:07, Umesh Nerlige Ramappa wrote:
> Add debug logs to view the reports in comparison with actual formats.
> Log the timestamp frequency used to calculate the period exponents.
>
> v2: Split debug patch from OAR test patch (Lionel)
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> ---
>   tests/perf.c | 19 +++++++++++++++++++
>   1 file changed, 19 insertions(+)
>
> diff --git a/tests/perf.c b/tests/perf.c
> index 2b6be134..506b64ec 100644
> --- a/tests/perf.c
> +++ b/tests/perf.c
> @@ -210,6 +210,19 @@ static uint32_t (*read_report_ticks)(uint32_t *report,
>   static void (*sanity_check_reports)(uint32_t *oa_report0, uint32_t *oa_report1,
>   				    enum drm_i915_oa_format format);
>   
> +static void
> +dump_report(const uint32_t *report, uint32_t size, const char *message) {
> +	uint32_t i;
> +	igt_debug("%s\n", message);
> +	for (i = 0; i < size; i += 4) {
> +		igt_debug("%08x %08x %08x %08x\n",
> +				report[i],
> +				report[i + 1],
> +				report[i + 2],
> +				report[i + 3]);
> +	}
> +}
> +
>   static struct oa_format
>   get_oa_format(enum drm_i915_oa_format format)
>   {
> @@ -874,6 +887,7 @@ init_sys_info(void)
>   	igt_assert_neq(devid, 0);
>   
>   	timestamp_frequency = get_cs_timestamp_frequency();
> +	igt_debug("timestamp_frequency = %lu\n", timestamp_frequency);
>   	igt_assert_neq(timestamp_frequency, 0);
>   
>   	if (IS_HASWELL(devid)) {
> @@ -1289,6 +1303,7 @@ read_2_oa_reports(int format_id,
>   			igt_assert_eq(header->size, sample_size);
>   
>   			report = (const void *)(header + 1);
> +			dump_report(report, 64, "oa-formats");
>   
>   			igt_debug("read report: reason = %x, timestamp = %x, exponent mask=%x\n",
>   				  report[0], report[1], exponent_mask);
> @@ -2856,6 +2871,7 @@ test_mi_rpc(void)
>   	igt_assert_eq(ret, 0);
>   
>   	report32 = bo->virtual;
> +	dump_report(report32, 64, "mi-rpc");
>   	igt_assert_eq(report32[0], 0xdeadbeef); /* report ID */
>   	igt_assert_neq(report32[1], 0); /* timestamp */
>   
> @@ -3335,11 +3351,13 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   			prev = report0_32;
>   			ctx_id = prev[2];
>   			igt_debug("MI_RPC(start) CTX ID: %u\n", ctx_id);
> +			dump_report(report0_32, 64, "report0_32");
>   
>   			report1_32 = report0_32 + 64; /* 64 uint32_t = 256bytes offset */
>   			igt_assert_eq(report1_32[0], 0xbeefbeef); /* report ID */
>   			igt_assert_neq(report1_32[1], 0); /* timestamp */
>   			ctx1_id = report1_32[2];
> +			dump_report(report1_32, 64, "report1_32");
>   
>   			memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
>   			accumulate_reports(&accumulator, report0_32, report1_32);
> @@ -3434,6 +3452,7 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   				igt_assert_eq(header->size, sample_size);
>   
>   				report = (void *)(header + 1);
> +				dump_report(report, 64, "OA report");
>   
>   				/* Don't expect zero for timestamps */
>   				igt_assert_neq(report[1], 0);


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[igt-dev] [PATCH i-g-t v4 3/4] test/perf: Add test for TGL OAR unit

[Umesh Nerlige Ramappa]

Add a test that measures work using MI-RPC for the specific context
without using reports from the OA buffer.

Tigerlake introduces an OA unit that measures work specific to render
workloads. This means we do not have to rely on reports from the OA
buffer to normalize the reports obtained from MI REPORT PERF COUNT
anymore.

v2:
- Add igt_drop_root to make the test run in non-privileged mode (Lionel)
- Move parameter to __perf_open inside the same function (Lionel)

v3, v4:
- Add igt test description

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/perf.c | 334 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 334 insertions(+)

diff --git a/tests/perf.c b/tests/perf.c
index 506b64ec..b80a95c7 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -3600,6 +3600,334 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
 	} while (WEXITSTATUS(child_ret) == EAGAIN);
 }
 
+static void gen12_single_ctx_helper(void)
+{
+	uint64_t properties[] = {
+		/* Have a random value here for the context id, but initialize
+		 * it once you figure out the context ID for the work to be
+		 * measured
+		 */
+		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
+
+		/* OA unit configuration:
+		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
+		 * because the OAR unit increments counters only for the
+		 * relevant context. No other parameters are needed since we do
+		 * not rely on the OA buffer anymore to normalize the counter
+		 * values.
+		 */
+		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
+		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
+	};
+	struct drm_i915_perf_open_param param = {
+		.flags = I915_PERF_FLAG_FD_CLOEXEC,
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context0, *context1;
+	struct intel_batchbuffer *batch;
+	struct igt_buf src[3], dst[3];
+	drm_intel_bo *bo;
+	uint32_t *report0_32, *report1_32, *report2_32, *report3_32;
+	uint64_t timestamp0_64, timestamp1_64;
+	uint32_t delta_ts64, delta_oa32;
+	uint64_t delta_ts64_ns, delta_oa32_ns;
+	uint32_t delta_delta;
+	int width = 800;
+	int height = 600;
+#define INVALID_CTX_ID 0xffffffff
+	uint32_t ctx0_id = INVALID_CTX_ID;
+	uint32_t ctx1_id = INVALID_CTX_ID;
+	int ret;
+	struct accumulator accumulator = {
+		.format = test_oa_format
+	};
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
+		scratch_buf_init(bufmgr, &src[i], width, height, 0xff0000ff);
+		scratch_buf_init(bufmgr, &dst[i], width, height, 0x00ff00ff);
+	}
+
+	batch = intel_batchbuffer_alloc(bufmgr, devid);
+
+	context0 = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context0);
+
+	context1 = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context1);
+
+	igt_debug("submitting warm up render_copy\n");
+
+	/* Submit some early, unmeasured, work to the context we want
+	 * to measure to try and catch issues with i915-perf
+	 * initializing the HW context ID for filtering.
+	 *
+	 * We do this because i915-perf single context filtering had
+	 * previously only relied on a hook into context pinning to
+	 * initialize the HW context ID, instead of also trying to
+	 * determine the HW ID while opening the stream, in case it
+	 * has already been pinned.
+	 *
+	 * This wasn't noticed by the previous unit test because we
+	 * were opening the stream while the context hadn't been
+	 * touched or pinned yet and so it worked out correctly to wait
+	 * for the pinning hook.
+	 *
+	 * Now a buggy version of i915-perf will fail to measure
+	 * anything for context0 once this initial render_copy() ends
+	 * up pinning the context since there won't ever be a pinning
+	 * hook callback.
+	 */
+	render_copy(batch, context0,
+		    &src[0], 0, 0, width, height,
+		    &dst[0], 0, 0);
+
+	/* Initialize the context parameter to the perf open ioctl here */
+	ret = drm_intel_gem_context_get_id(context0, &ctx0_id);
+	igt_assert_eq(ret, 0);
+	igt_assert_neq(ctx0_id, 0xffffffff);
+	properties[1] = ctx0_id;
+
+	igt_debug("opening i915-perf stream\n");
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
+
+	/* Set write domain to cpu briefly to fill the buffer with 80s */
+	ret = drm_intel_bo_map(bo, true);
+	igt_assert_eq(ret, 0);
+	memset(bo->virtual, 0x80, 2048);
+	memset(bo->virtual + 2048, 0, 2048);
+	drm_intel_bo_unmap(bo);
+
+	/* Submit an mi-rpc to context0 before measurable work */
+#define BO_TIMESTAMP_OFFSET0 1024
+#define BO_REPORT_OFFSET0 0
+#define BO_REPORT_ID0 0xdeadbeef
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET0,
+				     BO_REPORT_OFFSET0,
+				     BO_REPORT_ID0);
+	intel_batchbuffer_flush_with_context(batch, context0);
+
+	/* This is the work/context that is measured for counter increments */
+	render_copy(batch, context0,
+		    &src[0], 0, 0, width, height,
+		    &dst[0], 0, 0);
+	intel_batchbuffer_flush_with_context(batch, context0);
+
+	/* Submit an mi-rpc to context1 before work
+	 *
+	 * On gen12, this measurement should just yield counters that are
+	 * all zeroes, since the counters will only increment for the
+	 * context passed to perf open ioctl
+	 */
+#define BO_TIMESTAMP_OFFSET2 1040
+#define BO_REPORT_OFFSET2 512
+#define BO_REPORT_ID2 0x00c0ffee
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET2,
+				     BO_REPORT_OFFSET2,
+				     BO_REPORT_ID2);
+	intel_batchbuffer_flush_with_context(batch, context1);
+
+	/* Submit two copies on the other context to avoid a false
+	 * positive in case the driver somehow ended up filtering for
+	 * context1
+	 */
+	render_copy(batch, context1,
+		    &src[1], 0, 0, width, height,
+		    &dst[1], 0, 0);
+	ret = drm_intel_gem_context_get_id(context1, &ctx1_id);
+	igt_assert_eq(ret, 0);
+	igt_assert_neq(ctx1_id, 0xffffffff);
+
+	render_copy(batch, context1,
+		    &src[2], 0, 0, width, height,
+		    &dst[2], 0, 0);
+	intel_batchbuffer_flush_with_context(batch, context1);
+
+	/* Submit an mi-rpc to context1 after all work */
+#define BO_TIMESTAMP_OFFSET3 1048
+#define BO_REPORT_OFFSET3 768
+#define BO_REPORT_ID3 0x01c0ffee
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET3,
+				     BO_REPORT_OFFSET3,
+				     BO_REPORT_ID3);
+	intel_batchbuffer_flush_with_context(batch, context1);
+
+	/* Submit an mi-rpc to context0 after all measurable work */
+#define BO_TIMESTAMP_OFFSET1 1032
+#define BO_REPORT_OFFSET1 256
+#define BO_REPORT_ID1 0xbeefbeef
+	emit_stall_timestamp_and_rpc(batch,
+				     bo,
+				     BO_TIMESTAMP_OFFSET1,
+				     BO_REPORT_OFFSET1,
+				     BO_REPORT_ID1);
+	intel_batchbuffer_flush_with_context(batch, context0);
+
+	/* Set write domain to none */
+	ret = drm_intel_bo_map(bo, false);
+	igt_assert_eq(ret, 0);
+
+	/* Sanity check reports
+	 * reportX_32[0]: report id passed with mi-rpc
+	 * reportX_32[1]: timestamp
+	 * reportX_32[2]: context id
+	 *
+	 * report0_32: start of measurable work
+	 * report1_32: end of measurable work
+	 * report2_32: start of other work
+	 * report3_32: end of other work
+	 */
+	report0_32 = bo->virtual;
+	igt_assert_eq(report0_32[0], 0xdeadbeef);
+	igt_assert_neq(report0_32[1], 0);
+	ctx0_id = report0_32[2];
+	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
+	dump_report(report0_32, 64, "report0_32");
+
+	report1_32 = report0_32 + 64;
+	igt_assert_eq(report1_32[0], 0xbeefbeef);
+	igt_assert_neq(report1_32[1], 0);
+	ctx1_id = report1_32[2];
+	dump_report(report1_32, 64, "report1_32");
+
+	/* Verify that counters in context1 are all zeroes */
+	report2_32 = report0_32 + 128;
+	igt_assert_eq(report2_32[0], 0x00c0ffee);
+	igt_assert_neq(report2_32[1], 0);
+	dump_report(report2_32, 64, "report2_32");
+	igt_assert_eq(0, memcmp(&report2_32[4],
+				bo->virtual + 2048,
+				240));
+
+	report3_32 = report0_32 + 192;
+	igt_assert_eq(report3_32[0], 0x01c0ffee);
+	igt_assert_neq(report3_32[1], 0);
+	dump_report(report3_32, 64, "report3_32");
+	igt_assert_eq(0, memcmp(&report3_32[4],
+				bo->virtual + 2048,
+				240));
+
+	/* Accumulate deltas for counters - A0, A21 and A26 */
+	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
+	accumulate_reports(&accumulator, report0_32, report1_32);
+	igt_debug("total: A0 = %"PRIu64", A21 = %"PRIu64", A26 = %"PRIu64"\n",
+			accumulator.deltas[2 + 0],
+			accumulator.deltas[2 + 21],
+			accumulator.deltas[2 + 26]);
+
+	igt_debug("oa_timestamp32 0 = %u\n", report0_32[1]);
+	igt_debug("oa_timestamp32 1 = %u\n", report1_32[1]);
+	igt_debug("ctx_id 0 = %u\n", report0_32[2]);
+	igt_debug("ctx_id 1 = %u\n", report1_32[2]);
+
+	/* The delta as calculated via the PIPE_CONTROL timestamp or
+	 * the OA report timestamps should be almost identical but
+	 * allow a 500 nanoseconds margin.
+	 */
+	timestamp0_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET0);
+	timestamp1_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET1);
+
+	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
+	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
+
+	delta_ts64 = timestamp1_64 - timestamp0_64;
+	delta_oa32 = report1_32[1] - report0_32[1];
+
+	/* Sanity check that we can pass the delta to timebase_scale */
+	igt_assert(delta_ts64 < UINT32_MAX);
+	delta_oa32_ns = timebase_scale(delta_oa32);
+	delta_ts64_ns = timebase_scale(delta_ts64);
+
+	igt_debug("oa32 delta = %u, = %uns\n",
+			delta_oa32, (unsigned)delta_oa32_ns);
+	igt_debug("ts64 delta = %u, = %uns\n",
+			delta_ts64, (unsigned)delta_ts64_ns);
+
+	delta_delta = delta_ts64_ns > delta_oa32_ns ?
+		      (delta_ts64_ns - delta_oa32_ns) :
+		      (delta_oa32_ns - delta_ts64_ns);
+	if (delta_delta > 500) {
+		igt_debug("delta_delta exceeds margin, skipping..\n");
+		exit(EAGAIN);
+	}
+
+	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
+		  accumulator.deltas[2 + 21],
+		  accumulator.deltas[2 + 26],
+		  width, height);
+	accumulator_print(&accumulator, "filtered");
+
+	/* Verify that the work actually happened by comparing the src
+	 * and dst buffers
+	 */
+	ret = drm_intel_bo_map(src[0].bo, false);
+	igt_assert_eq(ret, 0);
+	ret = drm_intel_bo_map(dst[0].bo, false);
+	igt_assert_eq(ret, 0);
+
+	ret = memcmp(src[0].bo->virtual, dst[0].bo->virtual, 4 * width * height);
+	if (ret != 0) {
+		accumulator_print(&accumulator, "total");
+		exit(EAGAIN);
+	}
+
+	drm_intel_bo_unmap(src[0].bo);
+	drm_intel_bo_unmap(dst[0].bo);
+
+	/* Check that this test passed. The test measures the number of 2x2
+	 * samples written to the render target using the counter A26. For
+	 * OAR, this counter will only have increments relevant to this specific
+	 * context. The value equals the width * height of the rendered work.
+	 */
+	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
+
+	/* Clean up */
+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
+		drm_intel_bo_unreference(src[i].bo);
+		drm_intel_bo_unreference(dst[i].bo);
+	}
+
+	drm_intel_bo_unmap(bo);
+	drm_intel_bo_unreference(bo);
+	intel_batchbuffer_free(batch);
+	drm_intel_gem_context_destroy(context0);
+	drm_intel_gem_context_destroy(context1);
+	drm_intel_bufmgr_destroy(bufmgr);
+	__perf_close(stream_fd);
+}
+
+static void
+gen12_test_single_ctx_render_target_writes_a_counter(void)
+{
+	int child_ret;
+	struct igt_helper_process child = {};
+
+	/* Ensure perf_stream_paranoid is set to 1 by default */
+	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+
+	do {
+		igt_fork_helper(&child) {
+			igt_drop_root();
+			gen12_single_ctx_helper();
+		}
+		child_ret = igt_wait_helper(&child);
+		igt_assert(WEXITSTATUS(child_ret) == EAGAIN ||
+			   WEXITSTATUS(child_ret) == 0);
+	} while (WEXITSTATUS(child_ret) == EAGAIN);
+}
+
 static unsigned long rc6_residency_ms(void)
 {
 	return sysfs_read("power/rc6_residency_ms");
@@ -4225,6 +4553,12 @@ igt_main
 		gen8_test_single_ctx_render_target_writes_a_counter();
 	}
 
+	igt_describe("Measure performance for a specific context using OAR in Gen 12");
+	igt_subtest("gen12-unprivileged-single-ctx-counters") {
+		igt_require(intel_gen(devid) >= 12);
+		gen12_test_single_ctx_render_target_writes_a_counter();
+	}
+
 	igt_subtest("rc6-disable")
 		test_rc6_disable();
 
-- 
2.20.1

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Re: [igt-dev] [PATCH i-g-t v4 3/4] test/perf: Add test for TGL OAR unit

[Lionel Landwerlin]

On 20/11/2019 02:07, Umesh Nerlige Ramappa wrote:
> Add a test that measures work using MI-RPC for the specific context
> without using reports from the OA buffer.
>
> Tigerlake introduces an OA unit that measures work specific to render
> workloads. This means we do not have to rely on reports from the OA
> buffer to normalize the reports obtained from MI REPORT PERF COUNT
> anymore.
>
> v2:
> - Add igt_drop_root to make the test run in non-privileged mode (Lionel)
> - Move parameter to __perf_open inside the same function (Lionel)
>
> v3, v4:
> - Add igt test description
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>   tests/perf.c | 334 +++++++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 334 insertions(+)
>
> diff --git a/tests/perf.c b/tests/perf.c
> index 506b64ec..b80a95c7 100644
> --- a/tests/perf.c
> +++ b/tests/perf.c
> @@ -3600,6 +3600,334 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>   	} while (WEXITSTATUS(child_ret) == EAGAIN);
>   }
>   
> +static void gen12_single_ctx_helper(void)
> +{
> +	uint64_t properties[] = {
> +		/* Have a random value here for the context id, but initialize
> +		 * it once you figure out the context ID for the work to be
> +		 * measured
> +		 */
> +		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
> +
> +		/* OA unit configuration:
> +		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
> +		 * because the OAR unit increments counters only for the
> +		 * relevant context. No other parameters are needed since we do
> +		 * not rely on the OA buffer anymore to normalize the counter
> +		 * values.
> +		 */
> +		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
> +		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
> +	};
> +	struct drm_i915_perf_open_param param = {
> +		.flags = I915_PERF_FLAG_FD_CLOEXEC,
> +		.num_properties = ARRAY_SIZE(properties) / 2,
> +		.properties_ptr = to_user_pointer(properties),
> +	};
> +	drm_intel_bufmgr *bufmgr;
> +	drm_intel_context *context0, *context1;
> +	struct intel_batchbuffer *batch;
> +	struct igt_buf src[3], dst[3];
> +	drm_intel_bo *bo;
> +	uint32_t *report0_32, *report1_32, *report2_32, *report3_32;
> +	uint64_t timestamp0_64, timestamp1_64;
> +	uint32_t delta_ts64, delta_oa32;
> +	uint64_t delta_ts64_ns, delta_oa32_ns;
> +	uint32_t delta_delta;
> +	int width = 800;
> +	int height = 600;
> +#define INVALID_CTX_ID 0xffffffff
> +	uint32_t ctx0_id = INVALID_CTX_ID;
> +	uint32_t ctx1_id = INVALID_CTX_ID;
> +	int ret;
> +	struct accumulator accumulator = {
> +		.format = test_oa_format
> +	};
> +
> +	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> +	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> +
> +	for (int i = 0; i < ARRAY_SIZE(src); i++) {
> +		scratch_buf_init(bufmgr, &src[i], width, height, 0xff0000ff);
> +		scratch_buf_init(bufmgr, &dst[i], width, height, 0x00ff00ff);
> +	}
> +
> +	batch = intel_batchbuffer_alloc(bufmgr, devid);
> +
> +	context0 = drm_intel_gem_context_create(bufmgr);
> +	igt_assert(context0);
> +
> +	context1 = drm_intel_gem_context_create(bufmgr);
> +	igt_assert(context1);
> +
> +	igt_debug("submitting warm up render_copy\n");
> +
> +	/* Submit some early, unmeasured, work to the context we want
> +	 * to measure to try and catch issues with i915-perf
> +	 * initializing the HW context ID for filtering.
> +	 *
> +	 * We do this because i915-perf single context filtering had
> +	 * previously only relied on a hook into context pinning to
> +	 * initialize the HW context ID, instead of also trying to
> +	 * determine the HW ID while opening the stream, in case it
> +	 * has already been pinned.
> +	 *
> +	 * This wasn't noticed by the previous unit test because we
> +	 * were opening the stream while the context hadn't been
> +	 * touched or pinned yet and so it worked out correctly to wait
> +	 * for the pinning hook.
> +	 *
> +	 * Now a buggy version of i915-perf will fail to measure
> +	 * anything for context0 once this initial render_copy() ends
> +	 * up pinning the context since there won't ever be a pinning
> +	 * hook callback.
> +	 */
> +	render_copy(batch, context0,
> +		    &src[0], 0, 0, width, height,
> +		    &dst[0], 0, 0);
> +
> +	/* Initialize the context parameter to the perf open ioctl here */
> +	ret = drm_intel_gem_context_get_id(context0, &ctx0_id);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_neq(ctx0_id, 0xffffffff);
> +	properties[1] = ctx0_id;
> +
> +	igt_debug("opening i915-perf stream\n");
> +	stream_fd = __perf_open(drm_fd, &param, false);
> +
> +	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
> +
> +	/* Set write domain to cpu briefly to fill the buffer with 80s */
> +	ret = drm_intel_bo_map(bo, true);
> +	igt_assert_eq(ret, 0);
> +	memset(bo->virtual, 0x80, 2048);
> +	memset(bo->virtual + 2048, 0, 2048);
> +	drm_intel_bo_unmap(bo);
> +
> +	/* Submit an mi-rpc to context0 before measurable work */
> +#define BO_TIMESTAMP_OFFSET0 1024
> +#define BO_REPORT_OFFSET0 0
> +#define BO_REPORT_ID0 0xdeadbeef
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET0,
> +				     BO_REPORT_OFFSET0,
> +				     BO_REPORT_ID0);
> +	intel_batchbuffer_flush_with_context(batch, context0);
> +
> +	/* This is the work/context that is measured for counter increments */
> +	render_copy(batch, context0,
> +		    &src[0], 0, 0, width, height,
> +		    &dst[0], 0, 0);
> +	intel_batchbuffer_flush_with_context(batch, context0);
> +
> +	/* Submit an mi-rpc to context1 before work
> +	 *
> +	 * On gen12, this measurement should just yield counters that are
> +	 * all zeroes, since the counters will only increment for the
> +	 * context passed to perf open ioctl
> +	 */
> +#define BO_TIMESTAMP_OFFSET2 1040
> +#define BO_REPORT_OFFSET2 512
> +#define BO_REPORT_ID2 0x00c0ffee
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET2,
> +				     BO_REPORT_OFFSET2,
> +				     BO_REPORT_ID2);
> +	intel_batchbuffer_flush_with_context(batch, context1);
> +
> +	/* Submit two copies on the other context to avoid a false
> +	 * positive in case the driver somehow ended up filtering for
> +	 * context1
> +	 */
> +	render_copy(batch, context1,
> +		    &src[1], 0, 0, width, height,
> +		    &dst[1], 0, 0);
> +	ret = drm_intel_gem_context_get_id(context1, &ctx1_id);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_neq(ctx1_id, 0xffffffff);
> +
> +	render_copy(batch, context1,
> +		    &src[2], 0, 0, width, height,
> +		    &dst[2], 0, 0);
> +	intel_batchbuffer_flush_with_context(batch, context1);
> +
> +	/* Submit an mi-rpc to context1 after all work */
> +#define BO_TIMESTAMP_OFFSET3 1048
> +#define BO_REPORT_OFFSET3 768
> +#define BO_REPORT_ID3 0x01c0ffee
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET3,
> +				     BO_REPORT_OFFSET3,
> +				     BO_REPORT_ID3);
> +	intel_batchbuffer_flush_with_context(batch, context1);
> +
> +	/* Submit an mi-rpc to context0 after all measurable work */
> +#define BO_TIMESTAMP_OFFSET1 1032
> +#define BO_REPORT_OFFSET1 256
> +#define BO_REPORT_ID1 0xbeefbeef
> +	emit_stall_timestamp_and_rpc(batch,
> +				     bo,
> +				     BO_TIMESTAMP_OFFSET1,
> +				     BO_REPORT_OFFSET1,
> +				     BO_REPORT_ID1);
> +	intel_batchbuffer_flush_with_context(batch, context0);
> +
> +	/* Set write domain to none */
> +	ret = drm_intel_bo_map(bo, false);
> +	igt_assert_eq(ret, 0);
> +
> +	/* Sanity check reports
> +	 * reportX_32[0]: report id passed with mi-rpc
> +	 * reportX_32[1]: timestamp
> +	 * reportX_32[2]: context id
> +	 *
> +	 * report0_32: start of measurable work
> +	 * report1_32: end of measurable work
> +	 * report2_32: start of other work
> +	 * report3_32: end of other work
> +	 */
> +	report0_32 = bo->virtual;
> +	igt_assert_eq(report0_32[0], 0xdeadbeef);
> +	igt_assert_neq(report0_32[1], 0);
> +	ctx0_id = report0_32[2];
> +	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
> +	dump_report(report0_32, 64, "report0_32");
> +
> +	report1_32 = report0_32 + 64;
> +	igt_assert_eq(report1_32[0], 0xbeefbeef);
> +	igt_assert_neq(report1_32[1], 0);
> +	ctx1_id = report1_32[2];
> +	dump_report(report1_32, 64, "report1_32");
> +
> +	/* Verify that counters in context1 are all zeroes */
> +	report2_32 = report0_32 + 128;
> +	igt_assert_eq(report2_32[0], 0x00c0ffee);
> +	igt_assert_neq(report2_32[1], 0);
> +	dump_report(report2_32, 64, "report2_32");
> +	igt_assert_eq(0, memcmp(&report2_32[4],
> +				bo->virtual + 2048,
> +				240));
> +
> +	report3_32 = report0_32 + 192;
> +	igt_assert_eq(report3_32[0], 0x01c0ffee);
> +	igt_assert_neq(report3_32[1], 0);
> +	dump_report(report3_32, 64, "report3_32");
> +	igt_assert_eq(0, memcmp(&report3_32[4],
> +				bo->virtual + 2048,
> +				240));
> +
> +	/* Accumulate deltas for counters - A0, A21 and A26 */
> +	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
> +	accumulate_reports(&accumulator, report0_32, report1_32);
> +	igt_debug("total: A0 = %"PRIu64", A21 = %"PRIu64", A26 = %"PRIu64"\n",
> +			accumulator.deltas[2 + 0],
> +			accumulator.deltas[2 + 21],
> +			accumulator.deltas[2 + 26]);


What delta do you see for the context that is not given to i915-perf?

Asking because I want to verify that we can actually allow non 
privileged context to open without other context seeing global values 
(i.e. non saved/restored) in OAR.


-Lionel

> +
> +	igt_debug("oa_timestamp32 0 = %u\n", report0_32[1]);
> +	igt_debug("oa_timestamp32 1 = %u\n", report1_32[1]);
> +	igt_debug("ctx_id 0 = %u\n", report0_32[2]);
> +	igt_debug("ctx_id 1 = %u\n", report1_32[2]);
> +
> +	/* The delta as calculated via the PIPE_CONTROL timestamp or
> +	 * the OA report timestamps should be almost identical but
> +	 * allow a 500 nanoseconds margin.
> +	 */
> +	timestamp0_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET0);
> +	timestamp1_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET1);
> +
> +	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
> +	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
> +
> +	delta_ts64 = timestamp1_64 - timestamp0_64;
> +	delta_oa32 = report1_32[1] - report0_32[1];
> +
> +	/* Sanity check that we can pass the delta to timebase_scale */
> +	igt_assert(delta_ts64 < UINT32_MAX);
> +	delta_oa32_ns = timebase_scale(delta_oa32);
> +	delta_ts64_ns = timebase_scale(delta_ts64);
> +
> +	igt_debug("oa32 delta = %u, = %uns\n",
> +			delta_oa32, (unsigned)delta_oa32_ns);
> +	igt_debug("ts64 delta = %u, = %uns\n",
> +			delta_ts64, (unsigned)delta_ts64_ns);
> +
> +	delta_delta = delta_ts64_ns > delta_oa32_ns ?
> +		      (delta_ts64_ns - delta_oa32_ns) :
> +		      (delta_oa32_ns - delta_ts64_ns);
> +	if (delta_delta > 500) {
> +		igt_debug("delta_delta exceeds margin, skipping..\n");
> +		exit(EAGAIN);
> +	}
> +
> +	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
> +		  accumulator.deltas[2 + 21],
> +		  accumulator.deltas[2 + 26],
> +		  width, height);
> +	accumulator_print(&accumulator, "filtered");
> +
> +	/* Verify that the work actually happened by comparing the src
> +	 * and dst buffers
> +	 */
> +	ret = drm_intel_bo_map(src[0].bo, false);
> +	igt_assert_eq(ret, 0);
> +	ret = drm_intel_bo_map(dst[0].bo, false);
> +	igt_assert_eq(ret, 0);
> +
> +	ret = memcmp(src[0].bo->virtual, dst[0].bo->virtual, 4 * width * height);
> +	if (ret != 0) {
> +		accumulator_print(&accumulator, "total");
> +		exit(EAGAIN);
> +	}
> +
> +	drm_intel_bo_unmap(src[0].bo);
> +	drm_intel_bo_unmap(dst[0].bo);
> +
> +	/* Check that this test passed. The test measures the number of 2x2
> +	 * samples written to the render target using the counter A26. For
> +	 * OAR, this counter will only have increments relevant to this specific
> +	 * context. The value equals the width * height of the rendered work.
> +	 */
> +	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
> +
> +	/* Clean up */
> +	for (int i = 0; i < ARRAY_SIZE(src); i++) {
> +		drm_intel_bo_unreference(src[i].bo);
> +		drm_intel_bo_unreference(dst[i].bo);
> +	}
> +
> +	drm_intel_bo_unmap(bo);
> +	drm_intel_bo_unreference(bo);
> +	intel_batchbuffer_free(batch);
> +	drm_intel_gem_context_destroy(context0);
> +	drm_intel_gem_context_destroy(context1);
> +	drm_intel_bufmgr_destroy(bufmgr);
> +	__perf_close(stream_fd);
> +}
> +
> +static void
> +gen12_test_single_ctx_render_target_writes_a_counter(void)
> +{
> +	int child_ret;
> +	struct igt_helper_process child = {};
> +
> +	/* Ensure perf_stream_paranoid is set to 1 by default */
> +	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
> +
> +	do {
> +		igt_fork_helper(&child) {
> +			igt_drop_root();
> +			gen12_single_ctx_helper();
> +		}
> +		child_ret = igt_wait_helper(&child);
> +		igt_assert(WEXITSTATUS(child_ret) == EAGAIN ||
> +			   WEXITSTATUS(child_ret) == 0);
> +	} while (WEXITSTATUS(child_ret) == EAGAIN);
> +}
> +
>   static unsigned long rc6_residency_ms(void)
>   {
>   	return sysfs_read("power/rc6_residency_ms");
> @@ -4225,6 +4553,12 @@ igt_main
>   		gen8_test_single_ctx_render_target_writes_a_counter();
>   	}
>   
> +	igt_describe("Measure performance for a specific context using OAR in Gen 12");
> +	igt_subtest("gen12-unprivileged-single-ctx-counters") {
> +		igt_require(intel_gen(devid) >= 12);
> +		gen12_test_single_ctx_render_target_writes_a_counter();
> +	}
> +
>   	igt_subtest("rc6-disable")
>   		test_rc6_disable();
>   


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Re: [igt-dev] [PATCH i-g-t v4 3/4] test/perf: Add test for TGL OAR unit

[Umesh Nerlige Ramappa]

On Thu, Nov 21, 2019 at 03:26:58PM +0200, Lionel Landwerlin wrote:
>On 20/11/2019 02:07, Umesh Nerlige Ramappa wrote:
>>Add a test that measures work using MI-RPC for the specific context
>>without using reports from the OA buffer.
>>
>>Tigerlake introduces an OA unit that measures work specific to render
>>workloads. This means we do not have to rely on reports from the OA
>>buffer to normalize the reports obtained from MI REPORT PERF COUNT
>>anymore.
>>
>>v2:
>>- Add igt_drop_root to make the test run in non-privileged mode (Lionel)
>>- Move parameter to __perf_open inside the same function (Lionel)
>>
>>v3, v4:
>>- Add igt test description
>>
>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>>  tests/perf.c | 334 +++++++++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 334 insertions(+)
>>
>>diff --git a/tests/perf.c b/tests/perf.c
>>index 506b64ec..b80a95c7 100644
>>--- a/tests/perf.c
>>+++ b/tests/perf.c
>>@@ -3600,6 +3600,334 @@ gen8_test_single_ctx_render_target_writes_a_counter(void)
>>  	} while (WEXITSTATUS(child_ret) == EAGAIN);
>>  }
>>+static void gen12_single_ctx_helper(void)
>>+{
>>+	uint64_t properties[] = {
>>+		/* Have a random value here for the context id, but initialize
>>+		 * it once you figure out the context ID for the work to be
>>+		 * measured
>>+		 */
>>+		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
>>+
>>+		/* OA unit configuration:
>>+		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
>>+		 * because the OAR unit increments counters only for the
>>+		 * relevant context. No other parameters are needed since we do
>>+		 * not rely on the OA buffer anymore to normalize the counter
>>+		 * values.
>>+		 */
>>+		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
>>+		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
>>+	};
>>+	struct drm_i915_perf_open_param param = {
>>+		.flags = I915_PERF_FLAG_FD_CLOEXEC,
>>+		.num_properties = ARRAY_SIZE(properties) / 2,
>>+		.properties_ptr = to_user_pointer(properties),
>>+	};
>>+	drm_intel_bufmgr *bufmgr;
>>+	drm_intel_context *context0, *context1;
>>+	struct intel_batchbuffer *batch;
>>+	struct igt_buf src[3], dst[3];
>>+	drm_intel_bo *bo;
>>+	uint32_t *report0_32, *report1_32, *report2_32, *report3_32;
>>+	uint64_t timestamp0_64, timestamp1_64;
>>+	uint32_t delta_ts64, delta_oa32;
>>+	uint64_t delta_ts64_ns, delta_oa32_ns;
>>+	uint32_t delta_delta;
>>+	int width = 800;
>>+	int height = 600;
>>+#define INVALID_CTX_ID 0xffffffff
>>+	uint32_t ctx0_id = INVALID_CTX_ID;
>>+	uint32_t ctx1_id = INVALID_CTX_ID;
>>+	int ret;
>>+	struct accumulator accumulator = {
>>+		.format = test_oa_format
>>+	};
>>+
>>+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
>>+	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
>>+
>>+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
>>+		scratch_buf_init(bufmgr, &src[i], width, height, 0xff0000ff);
>>+		scratch_buf_init(bufmgr, &dst[i], width, height, 0x00ff00ff);
>>+	}
>>+
>>+	batch = intel_batchbuffer_alloc(bufmgr, devid);
>>+
>>+	context0 = drm_intel_gem_context_create(bufmgr);
>>+	igt_assert(context0);
>>+
>>+	context1 = drm_intel_gem_context_create(bufmgr);
>>+	igt_assert(context1);
>>+
>>+	igt_debug("submitting warm up render_copy\n");
>>+
>>+	/* Submit some early, unmeasured, work to the context we want
>>+	 * to measure to try and catch issues with i915-perf
>>+	 * initializing the HW context ID for filtering.
>>+	 *
>>+	 * We do this because i915-perf single context filtering had
>>+	 * previously only relied on a hook into context pinning to
>>+	 * initialize the HW context ID, instead of also trying to
>>+	 * determine the HW ID while opening the stream, in case it
>>+	 * has already been pinned.
>>+	 *
>>+	 * This wasn't noticed by the previous unit test because we
>>+	 * were opening the stream while the context hadn't been
>>+	 * touched or pinned yet and so it worked out correctly to wait
>>+	 * for the pinning hook.
>>+	 *
>>+	 * Now a buggy version of i915-perf will fail to measure
>>+	 * anything for context0 once this initial render_copy() ends
>>+	 * up pinning the context since there won't ever be a pinning
>>+	 * hook callback.
>>+	 */
>>+	render_copy(batch, context0,
>>+		    &src[0], 0, 0, width, height,
>>+		    &dst[0], 0, 0);
>>+
>>+	/* Initialize the context parameter to the perf open ioctl here */
>>+	ret = drm_intel_gem_context_get_id(context0, &ctx0_id);
>>+	igt_assert_eq(ret, 0);
>>+	igt_assert_neq(ctx0_id, 0xffffffff);
>>+	properties[1] = ctx0_id;
>>+
>>+	igt_debug("opening i915-perf stream\n");
>>+	stream_fd = __perf_open(drm_fd, &param, false);
>>+
>>+	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
>>+
>>+	/* Set write domain to cpu briefly to fill the buffer with 80s */
>>+	ret = drm_intel_bo_map(bo, true);
>>+	igt_assert_eq(ret, 0);
>>+	memset(bo->virtual, 0x80, 2048);
>>+	memset(bo->virtual + 2048, 0, 2048);
>>+	drm_intel_bo_unmap(bo);
>>+
>>+	/* Submit an mi-rpc to context0 before measurable work */
>>+#define BO_TIMESTAMP_OFFSET0 1024
>>+#define BO_REPORT_OFFSET0 0
>>+#define BO_REPORT_ID0 0xdeadbeef
>>+	emit_stall_timestamp_and_rpc(batch,
>>+				     bo,
>>+				     BO_TIMESTAMP_OFFSET0,
>>+				     BO_REPORT_OFFSET0,
>>+				     BO_REPORT_ID0);
>>+	intel_batchbuffer_flush_with_context(batch, context0);
>>+
>>+	/* This is the work/context that is measured for counter increments */
>>+	render_copy(batch, context0,
>>+		    &src[0], 0, 0, width, height,
>>+		    &dst[0], 0, 0);
>>+	intel_batchbuffer_flush_with_context(batch, context0);
>>+
>>+	/* Submit an mi-rpc to context1 before work
>>+	 *
>>+	 * On gen12, this measurement should just yield counters that are
>>+	 * all zeroes, since the counters will only increment for the
>>+	 * context passed to perf open ioctl
>>+	 */
>>+#define BO_TIMESTAMP_OFFSET2 1040
>>+#define BO_REPORT_OFFSET2 512
>>+#define BO_REPORT_ID2 0x00c0ffee
>>+	emit_stall_timestamp_and_rpc(batch,
>>+				     bo,
>>+				     BO_TIMESTAMP_OFFSET2,
>>+				     BO_REPORT_OFFSET2,
>>+				     BO_REPORT_ID2);
>>+	intel_batchbuffer_flush_with_context(batch, context1);
>>+
>>+	/* Submit two copies on the other context to avoid a false
>>+	 * positive in case the driver somehow ended up filtering for
>>+	 * context1
>>+	 */
>>+	render_copy(batch, context1,
>>+		    &src[1], 0, 0, width, height,
>>+		    &dst[1], 0, 0);
>>+	ret = drm_intel_gem_context_get_id(context1, &ctx1_id);
>>+	igt_assert_eq(ret, 0);
>>+	igt_assert_neq(ctx1_id, 0xffffffff);
>>+
>>+	render_copy(batch, context1,
>>+		    &src[2], 0, 0, width, height,
>>+		    &dst[2], 0, 0);
>>+	intel_batchbuffer_flush_with_context(batch, context1);
>>+
>>+	/* Submit an mi-rpc to context1 after all work */
>>+#define BO_TIMESTAMP_OFFSET3 1048
>>+#define BO_REPORT_OFFSET3 768
>>+#define BO_REPORT_ID3 0x01c0ffee
>>+	emit_stall_timestamp_and_rpc(batch,
>>+				     bo,
>>+				     BO_TIMESTAMP_OFFSET3,
>>+				     BO_REPORT_OFFSET3,
>>+				     BO_REPORT_ID3);
>>+	intel_batchbuffer_flush_with_context(batch, context1);
>>+
>>+	/* Submit an mi-rpc to context0 after all measurable work */
>>+#define BO_TIMESTAMP_OFFSET1 1032
>>+#define BO_REPORT_OFFSET1 256
>>+#define BO_REPORT_ID1 0xbeefbeef
>>+	emit_stall_timestamp_and_rpc(batch,
>>+				     bo,
>>+				     BO_TIMESTAMP_OFFSET1,
>>+				     BO_REPORT_OFFSET1,
>>+				     BO_REPORT_ID1);
>>+	intel_batchbuffer_flush_with_context(batch, context0);
>>+
>>+	/* Set write domain to none */
>>+	ret = drm_intel_bo_map(bo, false);
>>+	igt_assert_eq(ret, 0);
>>+
>>+	/* Sanity check reports
>>+	 * reportX_32[0]: report id passed with mi-rpc
>>+	 * reportX_32[1]: timestamp
>>+	 * reportX_32[2]: context id
>>+	 *
>>+	 * report0_32: start of measurable work
>>+	 * report1_32: end of measurable work
>>+	 * report2_32: start of other work
>>+	 * report3_32: end of other work
>>+	 */
>>+	report0_32 = bo->virtual;
>>+	igt_assert_eq(report0_32[0], 0xdeadbeef);
>>+	igt_assert_neq(report0_32[1], 0);
>>+	ctx0_id = report0_32[2];
>>+	igt_debug("MI_RPC(start) CTX ID: %u\n", ctx0_id);
>>+	dump_report(report0_32, 64, "report0_32");
>>+
>>+	report1_32 = report0_32 + 64;
>>+	igt_assert_eq(report1_32[0], 0xbeefbeef);
>>+	igt_assert_neq(report1_32[1], 0);
>>+	ctx1_id = report1_32[2];
>>+	dump_report(report1_32, 64, "report1_32");
>>+
>>+	/* Verify that counters in context1 are all zeroes */
>>+	report2_32 = report0_32 + 128;
>>+	igt_assert_eq(report2_32[0], 0x00c0ffee);
>>+	igt_assert_neq(report2_32[1], 0);
>>+	dump_report(report2_32, 64, "report2_32");
>>+	igt_assert_eq(0, memcmp(&report2_32[4],
>>+				bo->virtual + 2048,
>>+				240));

memcmp here ^

>>+
>>+	report3_32 = report0_32 + 192;
>>+	igt_assert_eq(report3_32[0], 0x01c0ffee);
>>+	igt_assert_neq(report3_32[1], 0);
>>+	dump_report(report3_32, 64, "report3_32");
>>+	igt_assert_eq(0, memcmp(&report3_32[4],
>>+				bo->virtual + 2048,
>>+				240));

memcmp here ^

>>+
>>+	/* Accumulate deltas for counters - A0, A21 and A26 */
>>+	memset(accumulator.deltas, 0, sizeof(accumulator.deltas));
>>+	accumulate_reports(&accumulator, report0_32, report1_32);
>>+	igt_debug("total: A0 = %"PRIu64", A21 = %"PRIu64", A26 = %"PRIu64"\n",
>>+			accumulator.deltas[2 + 0],
>>+			accumulator.deltas[2 + 21],
>>+			accumulator.deltas[2 + 26]);
>
>
>What delta do you see for the context that is not given to i915-perf?

no delta and also all counters are zeroes. The above 2 memcmp check that 
all counters are zeroes.

Thanks,
Umesh

>
>Asking because I want to verify that we can actually allow non 
>privileged context to open without other context seeing global values 
>(i.e. non saved/restored) in OAR.
>
>
>-Lionel
>
>>+
>>+	igt_debug("oa_timestamp32 0 = %u\n", report0_32[1]);
>>+	igt_debug("oa_timestamp32 1 = %u\n", report1_32[1]);
>>+	igt_debug("ctx_id 0 = %u\n", report0_32[2]);
>>+	igt_debug("ctx_id 1 = %u\n", report1_32[2]);
>>+
>>+	/* The delta as calculated via the PIPE_CONTROL timestamp or
>>+	 * the OA report timestamps should be almost identical but
>>+	 * allow a 500 nanoseconds margin.
>>+	 */
>>+	timestamp0_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET0);
>>+	timestamp1_64 = *(uint64_t *)(((uint8_t *)bo->virtual) + BO_TIMESTAMP_OFFSET1);
>>+
>>+	igt_debug("ts_timestamp64 0 = %"PRIu64"\n", timestamp0_64);
>>+	igt_debug("ts_timestamp64 1 = %"PRIu64"\n", timestamp1_64);
>>+
>>+	delta_ts64 = timestamp1_64 - timestamp0_64;
>>+	delta_oa32 = report1_32[1] - report0_32[1];
>>+
>>+	/* Sanity check that we can pass the delta to timebase_scale */
>>+	igt_assert(delta_ts64 < UINT32_MAX);
>>+	delta_oa32_ns = timebase_scale(delta_oa32);
>>+	delta_ts64_ns = timebase_scale(delta_ts64);
>>+
>>+	igt_debug("oa32 delta = %u, = %uns\n",
>>+			delta_oa32, (unsigned)delta_oa32_ns);
>>+	igt_debug("ts64 delta = %u, = %uns\n",
>>+			delta_ts64, (unsigned)delta_ts64_ns);
>>+
>>+	delta_delta = delta_ts64_ns > delta_oa32_ns ?
>>+		      (delta_ts64_ns - delta_oa32_ns) :
>>+		      (delta_oa32_ns - delta_ts64_ns);
>>+	if (delta_delta > 500) {
>>+		igt_debug("delta_delta exceeds margin, skipping..\n");
>>+		exit(EAGAIN);
>>+	}
>>+
>>+	igt_debug("n samples written = %"PRIu64"/%"PRIu64" (%ix%i)\n",
>>+		  accumulator.deltas[2 + 21],
>>+		  accumulator.deltas[2 + 26],
>>+		  width, height);
>>+	accumulator_print(&accumulator, "filtered");
>>+
>>+	/* Verify that the work actually happened by comparing the src
>>+	 * and dst buffers
>>+	 */
>>+	ret = drm_intel_bo_map(src[0].bo, false);
>>+	igt_assert_eq(ret, 0);
>>+	ret = drm_intel_bo_map(dst[0].bo, false);
>>+	igt_assert_eq(ret, 0);
>>+
>>+	ret = memcmp(src[0].bo->virtual, dst[0].bo->virtual, 4 * width * height);
>>+	if (ret != 0) {
>>+		accumulator_print(&accumulator, "total");
>>+		exit(EAGAIN);
>>+	}
>>+
>>+	drm_intel_bo_unmap(src[0].bo);
>>+	drm_intel_bo_unmap(dst[0].bo);
>>+
>>+	/* Check that this test passed. The test measures the number of 2x2
>>+	 * samples written to the render target using the counter A26. For
>>+	 * OAR, this counter will only have increments relevant to this specific
>>+	 * context. The value equals the width * height of the rendered work.
>>+	 */
>>+	igt_assert_eq(accumulator.deltas[2 + 26], width * height);
>>+
>>+	/* Clean up */
>>+	for (int i = 0; i < ARRAY_SIZE(src); i++) {
>>+		drm_intel_bo_unreference(src[i].bo);
>>+		drm_intel_bo_unreference(dst[i].bo);
>>+	}
>>+
>>+	drm_intel_bo_unmap(bo);
>>+	drm_intel_bo_unreference(bo);
>>+	intel_batchbuffer_free(batch);
>>+	drm_intel_gem_context_destroy(context0);
>>+	drm_intel_gem_context_destroy(context1);
>>+	drm_intel_bufmgr_destroy(bufmgr);
>>+	__perf_close(stream_fd);
>>+}
>>+
>>+static void
>>+gen12_test_single_ctx_render_target_writes_a_counter(void)
>>+{
>>+	int child_ret;
>>+	struct igt_helper_process child = {};
>>+
>>+	/* Ensure perf_stream_paranoid is set to 1 by default */
>>+	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
>>+
>>+	do {
>>+		igt_fork_helper(&child) {
>>+			igt_drop_root();
>>+			gen12_single_ctx_helper();
>>+		}
>>+		child_ret = igt_wait_helper(&child);
>>+		igt_assert(WEXITSTATUS(child_ret) == EAGAIN ||
>>+			   WEXITSTATUS(child_ret) == 0);
>>+	} while (WEXITSTATUS(child_ret) == EAGAIN);
>>+}
>>+
>>  static unsigned long rc6_residency_ms(void)
>>  {
>>  	return sysfs_read("power/rc6_residency_ms");
>>@@ -4225,6 +4553,12 @@ igt_main
>>  		gen8_test_single_ctx_render_target_writes_a_counter();
>>  	}
>>+	igt_describe("Measure performance for a specific context using OAR in Gen 12");
>>+	igt_subtest("gen12-unprivileged-single-ctx-counters") {
>>+		igt_require(intel_gen(devid) >= 12);
>>+		gen12_test_single_ctx_render_target_writes_a_counter();
>>+	}
>>+
>>  	igt_subtest("rc6-disable")
>>  		test_rc6_disable();
>
>
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Re: [igt-dev] [PATCH i-g-t v4 3/4] test/perf: Add test for TGL OAR unit

[Lionel Landwerlin]

[-- Attachment #1.1: Type: text/plain, Size: 352 bytes --]

On 21/11/2019 19:26, Umesh Nerlige Ramappa wrote:
>>
>>
>> What delta do you see for the context that is not given to i915-perf?
>
> no delta and also all counters are zeroes. The above 2 memcmp check 
> that all counters are zeroes.
>
> Thanks,
> Umesh
>
Thanks for pointing this out : Reviewed-by: Lionel Landwerlin 
<lionel.g.landwerlin@intel.com>


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[igt-dev] [PATCH i-g-t v4 4/4] test/perf: Pass context id for gen12 mi rpc test

[Umesh Nerlige Ramappa]

On Gen12, MI RPC uses OAR. OAR is configured only for the render context
that wants to measure the performance. Hence a context must be passed to
perf in the gen12 MI RPC when compared to previous gens.

v2:
- Add a note on report timestamp rolling over in ~6 mins (Lionel)
- Validate B0 counter to check if the report filled completely (Lionel)

v3, v4:
- Add igt test description

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/perf.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 117 insertions(+), 1 deletion(-)

diff --git a/tests/perf.c b/tests/perf.c
index b80a95c7..0bc7b757 100644
--- a/tests/perf.c
+++ b/tests/perf.c
@@ -2816,6 +2816,114 @@ test_disabled_read_error(void)
 	__perf_close(stream_fd);
 }
 
+static void
+gen12_test_mi_rpc(void)
+{
+	uint64_t properties[] = {
+		/* On Gen12, MI RPC uses OAR. OAR is configured only for the
+		 * render context that wants to measure the performance. Hence a
+		 * context must be specified in the gen12 MI RPC when compared
+		 * to previous gens.
+		 *
+		 * Have a random value here for the context id, but initialize
+		 * it once you figure out the context ID for the work to be
+		 * measured
+		 */
+		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
+
+		/* OA unit configuration:
+		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
+		 * because the OAR unit increments counters only for the
+		 * relevant context. No other parameters are needed since we do
+		 * not rely on the OA buffer anymore to normalize the counter
+		 * values.
+		 */
+		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
+		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
+	};
+	struct drm_i915_perf_open_param param = {
+		.flags = I915_PERF_FLAG_FD_CLOEXEC,
+		.num_properties = ARRAY_SIZE(properties) / 2,
+		.properties_ptr = to_user_pointer(properties),
+	};
+	drm_intel_bo *bo;
+	drm_intel_bufmgr *bufmgr;
+	drm_intel_context *context;
+	struct intel_batchbuffer *batch;
+#define INVALID_CTX_ID 0xffffffff
+	uint32_t ctx_id = INVALID_CTX_ID;
+	uint32_t *report32;
+	int ret;
+	size_t format_size_32;
+	struct oa_format format = get_oa_format(test_oa_format);
+
+	/* Ensure perf_stream_paranoid is set to 1 by default */
+	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
+
+	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
+	igt_assert(bufmgr);
+
+	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+	context = drm_intel_gem_context_create(bufmgr);
+	igt_assert(context);
+
+	ret = drm_intel_gem_context_get_id(context, &ctx_id);
+	igt_assert_eq(ret, 0);
+	igt_assert_neq(ctx_id, INVALID_CTX_ID);
+	properties[1] = ctx_id;
+
+	batch = intel_batchbuffer_alloc(bufmgr, devid);
+	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
+
+	ret = drm_intel_bo_map(bo, true);
+	igt_assert_eq(ret, 0);
+	memset(bo->virtual, 0x80, 4096);
+	drm_intel_bo_unmap(bo);
+
+	stream_fd = __perf_open(drm_fd, &param, false);
+
+#define REPORT_ID 0xdeadbeef
+#define REPORT_OFFSET 0
+	emit_report_perf_count(batch,
+			       bo,
+			       REPORT_OFFSET,
+			       REPORT_ID);
+	intel_batchbuffer_flush_with_context(batch, context);
+
+	ret = drm_intel_bo_map(bo, false);
+	igt_assert_eq(ret, 0);
+
+	report32 = bo->virtual;
+	format_size_32 = format.size >> 2;
+	dump_report(report32, format_size_32, "mi-rpc");
+
+	/* Sanity check reports
+	 * reportX_32[0]: report id passed with mi-rpc
+	 * reportX_32[1]: timestamp. NOTE: wraps around in ~6 minutes.
+	 *
+	 * reportX_32[format.b_off]: check if the entire report was filled.
+	 * B0 counter falls in the last 64 bytes of this report format.
+	 * Since reports are filled in 64 byte blocks, we should be able to
+	 * assure that the report was filled by checking the B0 counter. B0
+	 * counter is defined to be zero, so we can easily validate it.
+	 *
+	 * reportX_32[format_size_32]: outside report, make sure only the report
+	 * size amount of data was written.
+	 */
+	igt_assert_eq(report32[0], REPORT_ID);
+	igt_assert_neq(report32[1], 0);
+	igt_assert_neq(report32[format.b_off >> 2], 0x80808080);
+	igt_assert_eq(report32[format_size_32], 0x80808080);
+
+	drm_intel_bo_unmap(bo);
+	drm_intel_bo_unreference(bo);
+	intel_batchbuffer_free(batch);
+	drm_intel_gem_context_destroy(context);
+	drm_intel_bufmgr_destroy(bufmgr);
+	__perf_close(stream_fd);
+}
+
 static void
 test_mi_rpc(void)
 {
@@ -4532,8 +4640,16 @@ igt_main
 	igt_subtest("short-reads")
 		test_short_reads();
 
-	igt_subtest("mi-rpc")
+	igt_subtest("mi-rpc") {
+		igt_require(intel_gen(devid) < 12);
 		test_mi_rpc();
+	}
+
+	igt_describe("Test MI REPORT PERF COUNT for Gen 12");
+	igt_subtest("gen12-mi-rpc") {
+		igt_require(intel_gen(devid) >= 12);
+		gen12_test_mi_rpc();
+	}
 
 	igt_subtest("unprivileged-single-ctx-counters") {
 		igt_require(IS_HASWELL(devid));
-- 
2.20.1

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Re: [igt-dev] [PATCH i-g-t v4 4/4] test/perf: Pass context id for gen12 mi rpc test

[Lionel Landwerlin]

On 20/11/2019 02:08, Umesh Nerlige Ramappa wrote:
> On Gen12, MI RPC uses OAR. OAR is configured only for the render context
> that wants to measure the performance. Hence a context must be passed to
> perf in the gen12 MI RPC when compared to previous gens.
>
> v2:
> - Add a note on report timestamp rolling over in ~6 mins (Lionel)
> - Validate B0 counter to check if the report filled completely (Lionel)
>
> v3, v4:
> - Add igt test description
>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Apart from a small change below : Reviewed-by: Lionel Landwerlin 
<lionel.g.landwerlin@intel.com>

> ---
>   tests/perf.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++-
>   1 file changed, 117 insertions(+), 1 deletion(-)
>
> diff --git a/tests/perf.c b/tests/perf.c
> index b80a95c7..0bc7b757 100644
> --- a/tests/perf.c
> +++ b/tests/perf.c
> @@ -2816,6 +2816,114 @@ test_disabled_read_error(void)
>   	__perf_close(stream_fd);
>   }
>   
> +static void
> +gen12_test_mi_rpc(void)
> +{
> +	uint64_t properties[] = {
> +		/* On Gen12, MI RPC uses OAR. OAR is configured only for the
> +		 * render context that wants to measure the performance. Hence a
> +		 * context must be specified in the gen12 MI RPC when compared
> +		 * to previous gens.
> +		 *
> +		 * Have a random value here for the context id, but initialize
> +		 * it once you figure out the context ID for the work to be
> +		 * measured
> +		 */
> +		DRM_I915_PERF_PROP_CTX_HANDLE, UINT64_MAX,
> +
> +		/* OA unit configuration:
> +		 * DRM_I915_PERF_PROP_SAMPLE_OA is no longer required for Gen12
> +		 * because the OAR unit increments counters only for the
> +		 * relevant context. No other parameters are needed since we do
> +		 * not rely on the OA buffer anymore to normalize the counter
> +		 * values.
> +		 */
> +		DRM_I915_PERF_PROP_OA_METRICS_SET, test_metric_set_id,
> +		DRM_I915_PERF_PROP_OA_FORMAT, test_oa_format,
> +	};
> +	struct drm_i915_perf_open_param param = {
> +		.flags = I915_PERF_FLAG_FD_CLOEXEC,
> +		.num_properties = ARRAY_SIZE(properties) / 2,
> +		.properties_ptr = to_user_pointer(properties),
> +	};
> +	drm_intel_bo *bo;
> +	drm_intel_bufmgr *bufmgr;
> +	drm_intel_context *context;
> +	struct intel_batchbuffer *batch;
> +#define INVALID_CTX_ID 0xffffffff
> +	uint32_t ctx_id = INVALID_CTX_ID;
> +	uint32_t *report32;
> +	int ret;
> +	size_t format_size_32;
> +	struct oa_format format = get_oa_format(test_oa_format);
> +
> +	/* Ensure perf_stream_paranoid is set to 1 by default */
> +	write_u64_file("/proc/sys/dev/i915/perf_stream_paranoid", 1);
> +
> +	bufmgr = drm_intel_bufmgr_gem_init(drm_fd, 4096);
> +	igt_assert(bufmgr);
> +
> +	drm_intel_bufmgr_gem_enable_reuse(bufmgr);
> +
> +	context = drm_intel_gem_context_create(bufmgr);
> +	igt_assert(context);
> +
> +	ret = drm_intel_gem_context_get_id(context, &ctx_id);
> +	igt_assert_eq(ret, 0);
> +	igt_assert_neq(ctx_id, INVALID_CTX_ID);
> +	properties[1] = ctx_id;
> +
> +	batch = intel_batchbuffer_alloc(bufmgr, devid);
> +	bo = drm_intel_bo_alloc(bufmgr, "mi_rpc dest bo", 4096, 64);
> +
> +	ret = drm_intel_bo_map(bo, true);
> +	igt_assert_eq(ret, 0);
> +	memset(bo->virtual, 0x80, 4096);
> +	drm_intel_bo_unmap(bo);
> +
> +	stream_fd = __perf_open(drm_fd, &param, false);
> +
> +#define REPORT_ID 0xdeadbeef
> +#define REPORT_OFFSET 0
> +	emit_report_perf_count(batch,
> +			       bo,
> +			       REPORT_OFFSET,
> +			       REPORT_ID);
> +	intel_batchbuffer_flush_with_context(batch, context);
> +
> +	ret = drm_intel_bo_map(bo, false);
> +	igt_assert_eq(ret, 0);
> +
> +	report32 = bo->virtual;
> +	format_size_32 = format.size >> 2;
> +	dump_report(report32, format_size_32, "mi-rpc");
> +
> +	/* Sanity check reports
> +	 * reportX_32[0]: report id passed with mi-rpc
> +	 * reportX_32[1]: timestamp. NOTE: wraps around in ~6 minutes.
> +	 *
> +	 * reportX_32[format.b_off]: check if the entire report was filled.
> +	 * B0 counter falls in the last 64 bytes of this report format.
> +	 * Since reports are filled in 64 byte blocks, we should be able to
> +	 * assure that the report was filled by checking the B0 counter. B0
> +	 * counter is defined to be zero, so we can easily validate it.
> +	 *
> +	 * reportX_32[format_size_32]: outside report, make sure only the report
> +	 * size amount of data was written.
> +	 */
> +	igt_assert_eq(report32[0], REPORT_ID);
> +	igt_assert_neq(report32[1], 0);
> +	igt_assert_neq(report32[format.b_off >> 2], 0x80808080);

You can actually verify a 0 value for B0.


-Lionel

> +	igt_assert_eq(report32[format_size_32], 0x80808080);
> +
> +	drm_intel_bo_unmap(bo);
> +	drm_intel_bo_unreference(bo);
> +	intel_batchbuffer_free(batch);
> +	drm_intel_gem_context_destroy(context);
> +	drm_intel_bufmgr_destroy(bufmgr);
> +	__perf_close(stream_fd);
> +}
> +
>   static void
>   test_mi_rpc(void)
>   {
> @@ -4532,8 +4640,16 @@ igt_main
>   	igt_subtest("short-reads")
>   		test_short_reads();
>   
> -	igt_subtest("mi-rpc")
> +	igt_subtest("mi-rpc") {
> +		igt_require(intel_gen(devid) < 12);
>   		test_mi_rpc();
> +	}
> +
> +	igt_describe("Test MI REPORT PERF COUNT for Gen 12");
> +	igt_subtest("gen12-mi-rpc") {
> +		igt_require(intel_gen(devid) >= 12);
> +		gen12_test_mi_rpc();
> +	}
>   
>   	igt_subtest("unprivileged-single-ctx-counters") {
>   		igt_require(IS_HASWELL(devid));


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[igt-dev] ✗ Fi.CI.BAT: failure for series starting with [i-g-t,v4,1/4] test/perf: Add support for TGL in perf tests

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,v4,1/4] test/perf: Add support for TGL in perf tests
URL   : https://patchwork.freedesktop.org/series/69711/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7380 -> IGTPW_3731
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3731 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3731, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3731/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3731:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-skl-lmem:        [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7380/fi-skl-lmem/igt@gem_exec_suspend@basic-s0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3731/fi-skl-lmem/igt@gem_exec_suspend@basic-s0.html

  
Known issues
------------

  Here are the changes found in IGTPW_3731 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-bsw-nick:        [INCOMPLETE][3] ([fdo#105876]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7380/fi-bsw-nick/igt@i915_module_load@reload-with-fault-injection.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3731/fi-bsw-nick/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][5] ([fdo#108511]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7380/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3731/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-bsw-n3050:       [DMESG-FAIL][7] ([fdo#112176]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7380/fi-bsw-n3050/igt@i915_selftest@live_blt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3731/fi-bsw-n3050/igt@i915_selftest@live_blt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
  [fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (49 -> 42)
------------------------------

  Missing    (7): fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5295 -> IGTPW_3731

  CI-20190529: 20190529
  CI_DRM_7380: 7b0a3189ead776ce02426186e8d63cff190a453e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3731: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3731/index.html
  IGT_5295: 9211e4794e40135d797e6d056d6d8d40076acb92 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@perf@gen12-mi-rpc
+igt@perf@gen12-unprivileged-single-ctx-counters

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3731/index.html
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