[PATCH] drm/i915: Be optimistic about future display engines having 7 WM levels

[PATCH] drm/i915: Be optimistic about future display engines having 7 WM levels

[Damien Lespiau]

As we're doing throughout the code, being optimistic that platform n + 1
will mostly reuse the same things as platform n allows us to minimize
the enabling work needed.

This time, it's about the number of WM levels.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7006f94..3271e4a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1946,7 +1946,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
 int ilk_wm_max_level(const struct drm_device *dev)
 {
 	/* how many WM levels are we expecting */
-	if (IS_GEN9(dev))
+	if (INTEL_INFO(dev)->gen >= 9)
 		return 7;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		return 4;
-- 
2.1.0

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Re: [PATCH] drm/i915: Be optimistic about future display engines having 7 WM levels

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6368
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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Re: [PATCH] drm/i915: Be optimistic about future display engines having 7 WM levels

[Daniel Vetter]

On Sat, May 09, 2015 at 02:05:55AM +0100, Damien Lespiau wrote:
> As we're doing throughout the code, being optimistic that platform n + 1
> will mostly reuse the same things as platform n allows us to minimize
> the enabling work needed.
> 
> This time, it's about the number of WM levels.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7006f94..3271e4a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1946,7 +1946,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
>  int ilk_wm_max_level(const struct drm_device *dev)
>  {
>  	/* how many WM levels are we expecting */
> -	if (IS_GEN9(dev))
> +	if (INTEL_INFO(dev)->gen >= 9)
>  		return 7;
>  	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
>  		return 4;
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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