[PATCH 0/3] phy: mediatek: add MIPI DSI PHY driver

[PATCH 0/3] phy: mediatek: add MIPI DSI PHY driver

[Julien Stephan]

This series adds a mipi-dsi PHY driver MR8183 compatible SoC such as the
Genio-350 EVK.  The driver is ported from the kernel driver.

Patches 1 and 2 are preparatory patches: drivers/phy/ already carries 4
MediaTek PHY drivers and this series adds another one, so collect them
under drivers/phy/mediatek/ like the other vendors do. Kconfig symbol
names are unchanged, so no defconfig is affected. Also sort entries in
Makefiles and Kconfig.

Patch 3 adds the MIPI DSI PHY driver itself, supporting MT8183-compatible
SoCs, based on kernel commit 2ec9c210c1f9 ("phy: mediatek: Add support
for MT8196 MIPI DSI PHY").

Two deliberate deviations from the kernel driver:

- The kernel registers the MIPI TX PLL as a clock provider and hands it
  to the DSI host as its "hs" clock. U-Boot has no consumer for that
  clock, so the PLL clk_ops are folded into the PHY ops:
  determine_rate + set_rate become .configure(), and prepare_enable
  becomes .power_on().

- The kernel reads per-lane impedance trim codes from the
  "calibration-data" nvmem cell. MT8365 doe snot have that cell in DT yet,
  so rt_code[] stays zeroed and the SoC layer falls back to the same
  0x210 mid-scale default the kernel uses when the cell is absent. This
  can be wired up later.

Tested on Genio 350 (MT8365). The DSI host side that consumes this PHY
is sent separately to ease review

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
Julien Stephan (3):
      phy: sort vendor subdirectory lists alphabetically
      phy: mediatek: move MediaTek PHY drivers to their own subdirectory
      phy: phy-mtk-mipi-dsi: add new driver

 drivers/phy/Kconfig                              |  50 +------
 drivers/phy/Makefile                             |  15 +-
 drivers/phy/mediatek/Kconfig                     |  57 ++++++++
 drivers/phy/mediatek/Makefile                    |   7 +
 drivers/phy/{ => mediatek}/phy-mtk-hdmi-mt8195.c |   0
 drivers/phy/{ => mediatek}/phy-mtk-hdmi-mt8195.h |   0
 drivers/phy/{ => mediatek}/phy-mtk-hdmi.c        |   0
 drivers/phy/{ => mediatek}/phy-mtk-hdmi.h        |   0
 drivers/phy/{ => mediatek}/phy-mtk-io.h          |   0
 drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c   | 175 +++++++++++++++++++++++
 drivers/phy/mediatek/phy-mtk-mipi-dsi.c          | 144 +++++++++++++++++++
 drivers/phy/mediatek/phy-mtk-mipi-dsi.h          |  45 ++++++
 drivers/phy/{ => mediatek}/phy-mtk-tphy.c        |   0
 drivers/phy/{ => mediatek}/phy-mtk-ufs.c         |   0
 drivers/phy/{ => mediatek}/phy-mtk-xsphy.c       |   0
 15 files changed, 437 insertions(+), 56 deletions(-)
---
base-commit: 5437f0d7943e352ebe126f66275edf4f8206b545
change-id: 20260915-mt8365-add-phy-mtk-mipi-dsi-driver-22d184f03e95

Best regards,
--  
Julien Stephan <jstephan@baylibre.com>

[PATCH 1/3] phy: sort vendor subdirectory lists alphabetically

[Julien Stephan]

drivers/phy/Makefile has two separate blocks of "obj-y += <vendor>/"
lines, neither of them sorted, and the list of "source" statements in
drivers/phy/Kconfig is not sorted either. New vendor directories end up
appended wherever there is room, which makes the lists harder to read
and to extend.

Merge the two Makefile blocks into a single alphabetically sorted list
and sort the Kconfig source statements the same way, so subsequent
additions have an obvious place to go.

No functional change.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
 drivers/phy/Kconfig  |  4 ++--
 drivers/phy/Makefile | 10 +++++-----
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 6262380a60a..97133304cb6 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -363,12 +363,12 @@ config PHY_XILINX_ZYNQMP
 	  Enable this to support ZynqMP High Speed Gigabit Transceiver
 	  that is part of ZynqMP SoC.
 
-source "drivers/phy/rockchip/Kconfig"
 source "drivers/phy/cadence/Kconfig"
-source "drivers/phy/ti/Kconfig"
 source "drivers/phy/qcom/Kconfig"
 source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/rockchip/Kconfig"
 source "drivers/phy/starfive/Kconfig"
+source "drivers/phy/ti/Kconfig"
 
 config PHY_COMMON_PROPS
 	bool "Common PHY properties support"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 19cf95759e5..02f8b495ea0 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -4,9 +4,14 @@
 # Written by Jean-Jacques Hiblot  <jjhiblot@ti.com>
 
 obj-y += allwinner/
+obj-y += cadence/
 obj-y += marvell/
+obj-y += qcom/
+obj-y += renesas/
 obj-y += rockchip/
 obj-y += socionext/
+obj-y += starfive/
+obj-y += ti/
 
 obj-$(CONFIG_$(PHASE_)PHY) += phy-uclass.o
 obj-$(CONFIG_$(PHASE_)NOP_PHY) += nop-phy.o
@@ -46,8 +51,3 @@ obj-$(CONFIG_$(PHASE_)PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
 obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o
 obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
 obj-$(CONFIG_PHY_COMMON_PROPS) += phy-common-props.o
-obj-y += cadence/
-obj-y += ti/
-obj-y += qcom/
-obj-y += renesas/
-obj-y += starfive/

-- 
2.55.0

[PATCH 2/3] phy: mediatek: move MediaTek PHY drivers to their own subdirectory

[Julien Stephan]

drivers/phy/ hosts a growing number of MediaTek PHY drivers (T-PHY,
XS-PHY, UFS, HDMI). Other vendors already keep their PHY drivers in a
per-vendor subdirectory, so follow the same layout and move the MediaTek
ARM SoC drivers to drivers/phy/mediatek/, together with their Kconfig
symbols and Makefile rules.

The MIPS SoC drivers, mt7620-usb-phy.c and mt76x8-usb-phy.c, are left
where they are: MIPS MediaTek support is kept separate from the ARM one
elsewhere in the tree (drivers/clk/mtmips/, drivers/pinctrl/mtmips/),
and Linux does the same, keeping its drivers/phy/mediatek/ for the ARM
SoCs only.

No functional change: the files are moved verbatim and the Kconfig
symbols keep their names, so existing defconfigs are unaffected.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
 drivers/phy/Kconfig                              | 46 +-----------------------
 drivers/phy/Makefile                             |  5 +--
 drivers/phy/mediatek/Kconfig                     | 46 ++++++++++++++++++++++++
 drivers/phy/mediatek/Makefile                    |  6 ++++
 drivers/phy/{ => mediatek}/phy-mtk-hdmi-mt8195.c |  0
 drivers/phy/{ => mediatek}/phy-mtk-hdmi-mt8195.h |  0
 drivers/phy/{ => mediatek}/phy-mtk-hdmi.c        |  0
 drivers/phy/{ => mediatek}/phy-mtk-hdmi.h        |  0
 drivers/phy/{ => mediatek}/phy-mtk-io.h          |  0
 drivers/phy/{ => mediatek}/phy-mtk-tphy.c        |  0
 drivers/phy/{ => mediatek}/phy-mtk-ufs.c         |  0
 drivers/phy/{ => mediatek}/phy-mtk-xsphy.c       |  0
 12 files changed, 54 insertions(+), 49 deletions(-)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 97133304cb6..112c5aee786 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -278,51 +278,6 @@ config PHY_EXYNOS_USBDRD
 	help
 	  Enable USB DRD PHY support for Exynos SoC series.
 
-config PHY_MTK_HDMI
-	bool "MediaTek HDMI-PHY Driver"
-	depends on PHY
-	depends on ARCH_MEDIATEK
-	depends on ARM64
-	depends on CLK
-	help
-	  Support for the HDMI TX PHY found on MediaTek SoCs such as the
-	  MT8188 and MT8195. The PHY provides the TMDS links and the pixel
-	  clock PLL to the HDMI TX controller.
-
-config PHY_MTK_TPHY
-	bool "MediaTek T-PHY Driver"
-	depends on PHY
-	depends on ARCH_MEDIATEK || SOC_MT7621
-	select REGMAP
-	select SYSCON
-	help
-	  MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and
-	  SATA, and meanwhile supports two version T-PHY which have
-	  different banks layout, the T-PHY with shared banks between
-	  multi-ports is first version, otherwise is second veriosn,
-	  so you can easily distinguish them by banks layout.
-
-config PHY_MTK_UFS
-	bool "MediaTek UFS M-PHY driver"
-	depends on ARCH_MEDIATEK
-	depends on PHY
-	help
-	  Support for UFS M-PHY on MediaTek chipsets.
-	  Enable this to provide vendor-specific probing,
-	  initialization, power on and power off flow of
-	  specified M-PHYs.
-
-config PHY_MTK_XSPHY
-	bool "MediaTek XS-PHY Driver"
-	depends on PHY
-	depends on ARCH_MEDIATEK
-	select REGMAP
-	select SYSCON
-	help
-	  Enable this to support the SuperSpeedPlus XS-PHY transceiver for
-	  USB3.1 GEN2 controllers on MediaTek chips. The driver supports
-	  multiple USB2.0, USB3.1 GEN2 ports.
-
 config PHY_NPCM_USB
 	bool "Nuvoton NPCM USB PHY support"
 	depends on PHY
@@ -364,6 +319,7 @@ config PHY_XILINX_ZYNQMP
 	  that is part of ZynqMP SoC.
 
 source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/mediatek/Kconfig"
 source "drivers/phy/qcom/Kconfig"
 source "drivers/phy/renesas/Kconfig"
 source "drivers/phy/rockchip/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 02f8b495ea0..ed0279e47f2 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -6,6 +6,7 @@
 obj-y += allwinner/
 obj-y += cadence/
 obj-y += marvell/
+obj-y += mediatek/
 obj-y += qcom/
 obj-y += renesas/
 obj-y += rockchip/
@@ -42,10 +43,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
 obj-$(CONFIG_PHY_AXIADO_EMMC) += phy-axiado-emmc.o
 obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
 obj-$(CONFIG_PHY_EXYNOS_USBDRD) += phy-exynos-usbdrd.o
-obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi.o phy-mtk-hdmi-mt8195.o
-obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
-obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
-obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
 obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
 obj-$(CONFIG_$(PHASE_)PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
 obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o
diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
new file mode 100644
index 00000000000..29a46ea9350
--- /dev/null
+++ b/drivers/phy/mediatek/Kconfig
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config PHY_MTK_HDMI
+	bool "MediaTek HDMI-PHY Driver"
+	depends on PHY
+	depends on ARCH_MEDIATEK
+	depends on ARM64
+	depends on CLK
+	help
+	  Support for the HDMI TX PHY found on MediaTek SoCs such as the
+	  MT8188 and MT8195. The PHY provides the TMDS links and the pixel
+	  clock PLL to the HDMI TX controller.
+
+config PHY_MTK_TPHY
+	bool "MediaTek T-PHY Driver"
+	depends on PHY
+	depends on ARCH_MEDIATEK || SOC_MT7621
+	select REGMAP
+	select SYSCON
+	help
+	  MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and
+	  SATA, and meanwhile supports two version T-PHY which have
+	  different banks layout, the T-PHY with shared banks between
+	  multi-ports is first version, otherwise is second veriosn,
+	  so you can easily distinguish them by banks layout.
+
+config PHY_MTK_UFS
+	bool "MediaTek UFS M-PHY driver"
+	depends on ARCH_MEDIATEK
+	depends on PHY
+	help
+	  Support for UFS M-PHY on MediaTek chipsets.
+	  Enable this to provide vendor-specific probing,
+	  initialization, power on and power off flow of
+	  specified M-PHYs.
+
+config PHY_MTK_XSPHY
+	bool "MediaTek XS-PHY Driver"
+	depends on PHY
+	depends on ARCH_MEDIATEK
+	select REGMAP
+	select SYSCON
+	help
+	  Enable this to support the SuperSpeedPlus XS-PHY transceiver for
+	  USB3.1 GEN2 controllers on MediaTek chips. The driver supports
+	  multiple USB2.0, USB3.1 GEN2 ports.
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
new file mode 100644
index 00000000000..00ab10a238e
--- /dev/null
+++ b/drivers/phy/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi.o phy-mtk-hdmi-mt8195.o
+obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
+obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
+obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
diff --git a/drivers/phy/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
similarity index 100%
rename from drivers/phy/phy-mtk-hdmi-mt8195.c
rename to drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
diff --git a/drivers/phy/phy-mtk-hdmi-mt8195.h b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h
similarity index 100%
rename from drivers/phy/phy-mtk-hdmi-mt8195.h
rename to drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h
diff --git a/drivers/phy/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c
similarity index 100%
rename from drivers/phy/phy-mtk-hdmi.c
rename to drivers/phy/mediatek/phy-mtk-hdmi.c
diff --git a/drivers/phy/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h
similarity index 100%
rename from drivers/phy/phy-mtk-hdmi.h
rename to drivers/phy/mediatek/phy-mtk-hdmi.h
diff --git a/drivers/phy/phy-mtk-io.h b/drivers/phy/mediatek/phy-mtk-io.h
similarity index 100%
rename from drivers/phy/phy-mtk-io.h
rename to drivers/phy/mediatek/phy-mtk-io.h
diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
similarity index 100%
rename from drivers/phy/phy-mtk-tphy.c
rename to drivers/phy/mediatek/phy-mtk-tphy.c
diff --git a/drivers/phy/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c
similarity index 100%
rename from drivers/phy/phy-mtk-ufs.c
rename to drivers/phy/mediatek/phy-mtk-ufs.c
diff --git a/drivers/phy/phy-mtk-xsphy.c b/drivers/phy/mediatek/phy-mtk-xsphy.c
similarity index 100%
rename from drivers/phy/phy-mtk-xsphy.c
rename to drivers/phy/mediatek/phy-mtk-xsphy.c

-- 
2.55.0

[PATCH 3/3] phy: phy-mtk-mipi-dsi: add new driver

[Julien Stephan]

Add a new driver for the MIPI DSI PHY. The driver supports MT8183
compatible SoCs. The driver is base on the corresponding kernel driver
commit 2ec9c210c1f9 ("phy: mediatek: Add support for MT8196 MIPI DSI PHY")

Few notes about the port from kernel:
- tested on Genio-350 which does not have nvmem-cells, so keep rt_code[]
  zeroed and fallback to 0x210 has kernel does when no cell available.
  Can be implemented later.
- PLL is not registered as a clock provider:
    - configure() = determine_rate+set_rate
    - power_on() = clk_prepare_enable
  configure() takes a struct phy_configure_opts_mipi_dphy and uses its
  hs_clk_rate member, which carries the per-lane data rate the kernel
  would have set on the "hs" clock.

Signed-off-by: Julien Stephan <jstephan@baylibre.com>
---
 drivers/phy/mediatek/Kconfig                   |  11 ++
 drivers/phy/mediatek/Makefile                  |   1 +
 drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 175 +++++++++++++++++++++++++
 drivers/phy/mediatek/phy-mtk-mipi-dsi.c        | 144 ++++++++++++++++++++
 drivers/phy/mediatek/phy-mtk-mipi-dsi.h        |  45 +++++++
 5 files changed, 376 insertions(+)

diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig
index 29a46ea9350..f4049afc43f 100644
--- a/drivers/phy/mediatek/Kconfig
+++ b/drivers/phy/mediatek/Kconfig
@@ -11,6 +11,17 @@ config PHY_MTK_HDMI
 	  MT8188 and MT8195. The PHY provides the TMDS links and the pixel
 	  clock PLL to the HDMI TX controller.
 
+config PHY_MTK_MIPI_DSI
+	bool "MediaTek MIPI-DSI PHY Driver"
+	depends on PHY
+	depends on ARCH_MEDIATEK
+	depends on ARM64
+	depends on CLK
+	help
+	  Support for the MIPI TX D-PHY found on MediaTek SoCs such as the
+	  MT8183 and MT8365. The PHY provides the D-PHY lanes and the byte
+	  clock PLL to the DSI host controller.
+
 config PHY_MTK_TPHY
 	bool "MediaTek T-PHY Driver"
 	depends on PHY
diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
index 00ab10a238e..6dedec70edc 100644
--- a/drivers/phy/mediatek/Makefile
+++ b/drivers/phy/mediatek/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi.o phy-mtk-hdmi-mt8195.o
+obj-$(CONFIG_PHY_MTK_MIPI_DSI) += phy-mtk-mipi-dsi.o phy-mtk-mipi-dsi-mt8183.o
 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
new file mode 100644
index 00000000000..1fce03fcf45
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Copyright (c) 2026 BayLibre, SAS
+ * Author: Jitao Shi <jitao.shi@mediatek.com>
+ */
+
+#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+
+#include "phy-mtk-io.h"
+#include "phy-mtk-mipi-dsi.h"
+
+#define MIPITX_LANE_CON		0x000c
+#define RG_DSI_BG_LPF_EN		BIT(6)
+#define RG_DSI_BG_CORE_EN		BIT(7)
+#define RG_DSI_PAD_TIEL_SEL		BIT(8)
+
+#define MIPITX_VOLTAGE_SEL	0x0010
+#define RG_DSI_HSTX_LDO_REF_SEL		GENMASK(9, 6)
+
+#define MIPITX_PLL_PWR		0x0028
+#define AD_DSI_PLL_SDM_PWR_ON		BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN		BIT(1)
+
+#define MIPITX_PLL_CON0		0x002c
+
+#define MIPITX_PLL_CON1		0x0030
+#define RG_DSI_PLL_EN			BIT(4)
+#define RG_DSI_PLL_POSDIV		GENMASK(10, 8)
+
+#define MIPITX_PLL_CON4		0x003c
+#define RG_DSI_PLL_IBIAS		GENMASK(11, 10)
+
+#define MIPITX_D2P_RTCODE	0x0100
+#define MIPITX_D2_SW_CTL_EN	0x0144
+#define MIPITX_D0_SW_CTL_EN	0x0244
+
+#define MIPITX_CK_CKMODE_EN	0x0328
+#define DSI_CK_CKMODE_EN		BIT(0)
+
+#define MIPITX_CK_SW_CTL_EN	0x0344
+#define MIPITX_D1_SW_CTL_EN	0x0444
+#define MIPITX_D3_SW_CTL_EN	0x0544
+#define DSI_SW_CTL_EN			BIT(0)
+
+/* Reference clock feeding the PLL, fixed at 26MHz on all supported SoCs. */
+#define MIPITX_PLL_REF_RATE	26000000
+
+#define MIPITX_DATA_RATE_MIN	125000000ULL
+#define MIPITX_DATA_RATE_MAX	1600000000ULL
+
+static u64 mtk_mipi_tx_pll_determine_rate(struct mtk_mipi_tx *mipi_tx, u64 rate)
+{
+	return clamp_val(rate, MIPITX_DATA_RATE_MIN, MIPITX_DATA_RATE_MAX);
+}
+
+static int mtk_mipi_tx_pll_enable(struct mtk_mipi_tx *mipi_tx)
+{
+	void __iomem *base = mipi_tx->regs;
+	unsigned int txdiv, txdiv0;
+	u64 pcw;
+
+	dev_dbg(mipi_tx->dev, "enable: %llu bps\n", mipi_tx->data_rate);
+
+	if (mipi_tx->data_rate >= 2000000000) {
+		txdiv = 1;
+		txdiv0 = 0;
+	} else if (mipi_tx->data_rate >= 1000000000) {
+		txdiv = 2;
+		txdiv0 = 1;
+	} else if (mipi_tx->data_rate >= 500000000) {
+		txdiv = 4;
+		txdiv0 = 2;
+	} else if (mipi_tx->data_rate > 250000000) {
+		txdiv = 8;
+		txdiv0 = 3;
+	} else if (mipi_tx->data_rate >= 125000000) {
+		txdiv = 16;
+		txdiv0 = 4;
+	} else {
+		return -EINVAL;
+	}
+
+	mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+
+	mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+	mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+	udelay(1);
+	mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+	pcw = div_u64(mipi_tx->data_rate * txdiv << 24, MIPITX_PLL_REF_RATE);
+	writel(pcw, base + MIPITX_PLL_CON0);
+	mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);
+	mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+
+	return 0;
+}
+
+static void mtk_mipi_tx_pll_disable(struct mtk_mipi_tx *mipi_tx)
+{
+	void __iomem *base = mipi_tx->regs;
+
+	mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+
+	mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+	mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+}
+
+static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
+{
+	int i, j;
+
+	for (i = 0; i < 5; i++) {
+		if ((mipi_tx->rt_code[i] & 0x1f) == 0)
+			mipi_tx->rt_code[i] |= 0x10;
+
+		if ((mipi_tx->rt_code[i] >> 5 & 0x1f) == 0)
+			mipi_tx->rt_code[i] |= 0x10 << 5;
+
+		for (j = 0; j < 10; j++)
+			mtk_phy_update_bits(mipi_tx->regs +
+				MIPITX_D2P_RTCODE * (i + 1) + j * 4,
+				1, mipi_tx->rt_code[i] >> j & 1);
+	}
+}
+
+static void mtk_mipi_tx_power_on_signal(struct mtk_mipi_tx *mipi_tx)
+{
+	void __iomem *base = mipi_tx->regs;
+
+	/* BG_LPF_EN / BG_CORE_EN */
+	writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
+	udelay(30);
+	writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
+
+	/* Switch OFF each Lane */
+	mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+
+	mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,
+			     (mipi_tx->mipitx_drive - 3000) / 200);
+
+	mtk_mipi_tx_config_calibration_data(mipi_tx);
+
+	mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
+}
+
+static void mtk_mipi_tx_power_off_signal(struct mtk_mipi_tx *mipi_tx)
+{
+	void __iomem *base = mipi_tx->regs;
+
+	/* Switch ON each Lane */
+	mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+	mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+
+	writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
+	writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON);
+}
+
+const struct mtk_mipitx_data mt8183_mipitx_data = {
+	.pll_determine_rate = mtk_mipi_tx_pll_determine_rate,
+	.pll_enable = mtk_mipi_tx_pll_enable,
+	.pll_disable = mtk_mipi_tx_pll_disable,
+	.mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
+	.mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
+};
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
new file mode 100644
index 00000000000..918636a8df1
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Copyright (c) 2026 BayLibre, SAS
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/kernel.h>
+#include <phy-mipi-dphy.h>
+
+#include "phy-mtk-mipi-dsi.h"
+
+#define MIPITX_DRIVE_DEFAULT_UA		4600
+#define MIPITX_DRIVE_MIN_UA		3000
+#define MIPITX_DRIVE_MAX_UA		6000
+
+static int mtk_mipi_tx_power_on(struct phy *phy)
+{
+	struct mtk_mipi_tx *mipi_tx = dev_get_priv(phy->dev);
+	int ret;
+
+	if (!mipi_tx->data_rate) {
+		dev_err(phy->dev, "No data rate set, configure the PHY first\n");
+		return -EINVAL;
+	}
+
+	/* Power up core and enable PLL */
+	ret = mipi_tx->driver_data->pll_enable(mipi_tx);
+	if (ret)
+		return ret;
+
+	/* Enable DSI Lane LDO outputs, disable pad tie low */
+	mipi_tx->driver_data->mipi_tx_enable_signal(mipi_tx);
+
+	return 0;
+}
+
+static int mtk_mipi_tx_power_off(struct phy *phy)
+{
+	struct mtk_mipi_tx *mipi_tx = dev_get_priv(phy->dev);
+
+	/* Enable pad tie low, disable DSI Lane LDO outputs */
+	mipi_tx->driver_data->mipi_tx_disable_signal(mipi_tx);
+
+	/* Disable PLL and power down core */
+	mipi_tx->driver_data->pll_disable(mipi_tx);
+
+	return 0;
+}
+
+/*
+ * Equivalent of the kernel PLL clock's determine_rate and set_rate ops: clamp
+ * the requested data rate to what the PLL can lock to and latch it, the
+ * hardware is programmed when the PHY is powered on.
+ */
+static int mtk_mipi_tx_configure(struct phy *phy, void *params)
+{
+	struct mtk_mipi_tx *mipi_tx = dev_get_priv(phy->dev);
+	struct phy_configure_opts_mipi_dphy *opts = params;
+
+	if (!opts)
+		return -EINVAL;
+
+	mipi_tx->data_rate =
+		mipi_tx->driver_data->pll_determine_rate(mipi_tx,
+							 opts->hs_clk_rate);
+
+	return 0;
+}
+
+static int mtk_mipi_tx_probe(struct udevice *dev)
+{
+	struct mtk_mipi_tx *mipi_tx = dev_get_priv(dev);
+	int ret;
+
+	mipi_tx->dev = dev;
+	mipi_tx->driver_data =
+		(const struct mtk_mipitx_data *)dev_get_driver_data(dev);
+	if (!mipi_tx->driver_data)
+		return -ENODEV;
+
+	mipi_tx->regs = dev_remap_addr(dev);
+	if (!mipi_tx->regs)
+		return -EINVAL;
+
+	ret = clk_get_by_index(dev, 0, &mipi_tx->ref_clk);
+	if (ret) {
+		dev_err(dev, "Failed to get reference clock: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_enable(&mipi_tx->ref_clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable reference clock: %d\n", ret);
+		return ret;
+	}
+
+	mipi_tx->mipitx_drive = dev_read_u32_default(dev, "drive-strength-microamp",
+						     MIPITX_DRIVE_DEFAULT_UA);
+	if (mipi_tx->mipitx_drive > MIPITX_DRIVE_MAX_UA ||
+	    mipi_tx->mipitx_drive < MIPITX_DRIVE_MIN_UA) {
+		dev_warn(dev, "drive-strength-microamp is invalid %u, not in %u ~ %u\n",
+			 mipi_tx->mipitx_drive, MIPITX_DRIVE_MIN_UA,
+			 MIPITX_DRIVE_MAX_UA);
+		mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive,
+						  MIPITX_DRIVE_MIN_UA,
+						  MIPITX_DRIVE_MAX_UA);
+	}
+
+	/*
+	 * The kernel reads the per-lane impedance trim codes from the
+	 * "calibration-data" nvmem cell. No MediaTek board describes that cell
+	 * in its device tree yet, so rt_code[] is left zeroed here and the
+	 * SoC layer substitutes the same mid-scale default the kernel uses
+	 * when the cell is absent.
+	 */
+
+	return 0;
+}
+
+static const struct phy_ops mtk_mipi_tx_phy_ops = {
+	.power_on	= mtk_mipi_tx_power_on,
+	.power_off	= mtk_mipi_tx_power_off,
+	.configure	= mtk_mipi_tx_configure,
+};
+
+static const struct udevice_id mtk_mipi_tx_ids[] = {
+	{ .compatible = "mediatek,mt8183-mipi-tx",
+	  .data = (ulong)&mt8183_mipitx_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mtk_mipi_tx) = {
+	.name		= "mtk-mipi-tx",
+	.id		= UCLASS_PHY,
+	.of_match	= mtk_mipi_tx_ids,
+	.ops		= &mtk_mipi_tx_phy_ops,
+	.probe		= mtk_mipi_tx_probe,
+	.priv_auto	= sizeof(struct mtk_mipi_tx),
+};
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
new file mode 100644
index 00000000000..96a93e5ba5f
--- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Copyright (c) 2026 BayLibre, SAS
+ * Author: Jitao Shi <jitao.shi@mediatek.com>
+ */
+
+#ifndef _PHY_MTK_MIPI_DSI_H
+#define _PHY_MTK_MIPI_DSI_H
+
+#include <clk.h>
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+struct mtk_mipi_tx;
+struct udevice;
+
+/*
+ * The Linux driver models the MIPI TX PLL as a clock provider (struct clk_hw /
+ * struct clk_ops) fed to the DSI host as its "hs" clock. U-Boot has no consumer
+ * for that clock, so the PLL clk_ops are folded into the callbacks below
+ * (keeping the kernel determine_rate/enable/disable naming) and are driven
+ * directly from the PHY ops.
+ */
+struct mtk_mipitx_data {
+	u64 (*pll_determine_rate)(struct mtk_mipi_tx *mipi_tx, u64 rate);
+	int (*pll_enable)(struct mtk_mipi_tx *mipi_tx);
+	void (*pll_disable)(struct mtk_mipi_tx *mipi_tx);
+	void (*mipi_tx_enable_signal)(struct mtk_mipi_tx *mipi_tx);
+	void (*mipi_tx_disable_signal)(struct mtk_mipi_tx *mipi_tx);
+};
+
+struct mtk_mipi_tx {
+	struct udevice *dev;
+	void __iomem *regs;
+	struct clk ref_clk;
+	u64 data_rate;
+	u32 mipitx_drive;
+	u32 rt_code[5];
+	const struct mtk_mipitx_data *driver_data;
+};
+
+extern const struct mtk_mipitx_data mt8183_mipitx_data;
+
+#endif /* _PHY_MTK_MIPI_DSI_H */

-- 
2.55.0

Re: [PATCH 3/3] phy: phy-mtk-mipi-dsi: add new driver

[David Lechner]

On 9/15/26 10:00 AM, Julien Stephan wrote:
> Add a new driver for the MIPI DSI PHY. The driver supports MT8183
> compatible SoCs. The driver is base on the corresponding kernel driver

s/base/based/

> commit 2ec9c210c1f9 ("phy: mediatek: Add support for MT8196 MIPI DSI PHY")
> 
> Few notes about the port from kernel:

s/Few/A few/

> - tested on Genio-350 which does not have nvmem-cells, so keep rt_code[]
>   zeroed and fallback to 0x210 has kernel does when no cell available.

s/has/as the/

>   Can be implemented later.
> - PLL is not registered as a clock provider:
>     - configure() = determine_rate+set_rate
>     - power_on() = clk_prepare_enable
>   configure() takes a struct phy_configure_opts_mipi_dphy and uses its
>   hs_clk_rate member, which carries the per-lane data rate the kernel
>   would have set on the "hs" clock.
> 

...

> +static int mtk_mipi_tx_pll_enable(struct mtk_mipi_tx *mipi_tx)
> +{
> +	void __iomem *base = mipi_tx->regs;
> +	unsigned int txdiv, txdiv0;
> +	u64 pcw;
> +
> +	dev_dbg(mipi_tx->dev, "enable: %llu bps\n", mipi_tx->data_rate);
> +
> +	if (mipi_tx->data_rate >= 2000000000) {
> +		txdiv = 1;
> +		txdiv0 = 0;
> +	} else if (mipi_tx->data_rate >= 1000000000) {
> +		txdiv = 2;
> +		txdiv0 = 1;
> +	} else if (mipi_tx->data_rate >= 500000000) {
> +		txdiv = 4;
> +		txdiv0 = 2;
> +	} else if (mipi_tx->data_rate > 250000000) {
> +		txdiv = 8;
> +		txdiv0 = 3;
> +	} else if (mipi_tx->data_rate >= 125000000) {
> +		txdiv = 16;
> +		txdiv0 = 4;
> +	} else {
> +		return -EINVAL;
> +	}
> +
> +	mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
> +
> +	mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
> +	mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
> +	udelay(1);
> +	mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
> +	pcw = div_u64(mipi_tx->data_rate * txdiv << 24, MIPITX_PLL_REF_RATE);

(mipi_tx->data_rate * txdiv) << 24

For those of us that can't remember order of operations.

> +	writel(pcw, base + MIPITX_PLL_CON0);
> +	mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);
> +	mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
> +
> +	return 0;
> +}
> +

...

> +static void mtk_mipi_tx_power_on_signal(struct mtk_mipi_tx *mipi_tx)
> +{
> +	void __iomem *base = mipi_tx->regs;
> +
> +	/* BG_LPF_EN / BG_CORE_EN */
> +	writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
> +	udelay(30);
> +	writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
> +
> +	/* Switch OFF each Lane */
> +	mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
> +	mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
> +	mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
> +	mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
> +	mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
> +
> +	mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,
> +			     (mipi_tx->mipitx_drive - 3000) / 200);

Is this 3000 supposed to be MIPITX_DRIVE_MIN_UA?

> +
> +	mtk_mipi_tx_config_calibration_data(mipi_tx);
> +
> +	mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
> +}
> +

...

> +	/*
> +	 * The kernel reads the per-lane impedance trim codes from the
> +	 * "calibration-data" nvmem cell. No MediaTek board describes that cell

Technically, mipi_tx0: dsi-phy@11e50000 does in mt8183.dtsi

Not saying we need to implement it right now though. Just the comment isn't
100% accurate.

> +	 * in its device tree yet, so rt_code[] is left zeroed here and the
> +	 * SoC layer substitutes the same mid-scale default the kernel uses
> +	 * when the cell is absent.
> +	 */
> +
> +	return 0;
> +}
> +

Re: [PATCH 2/3] phy: mediatek: move MediaTek PHY drivers to their own subdirectory

[David Lechner]

On 9/15/26 10:00 AM, Julien Stephan wrote:
> drivers/phy/ hosts a growing number of MediaTek PHY drivers (T-PHY,
> XS-PHY, UFS, HDMI). Other vendors already keep their PHY drivers in a
> per-vendor subdirectory, so follow the same layout and move the MediaTek
> ARM SoC drivers to drivers/phy/mediatek/, together with their Kconfig
> symbols and Makefile rules.
> 
> The MIPS SoC drivers, mt7620-usb-phy.c and mt76x8-usb-phy.c, are left
> where they are: MIPS MediaTek support is kept separate from the ARM one
> elsewhere in the tree (drivers/clk/mtmips/, drivers/pinctrl/mtmips/),
> and Linux does the same, keeping its drivers/phy/mediatek/ for the ARM
> SoCs only.
> 
> No functional change: the files are moved verbatim and the Kconfig
> symbols keep their names, so existing defconfigs are unaffected.
> 

...

> +config PHY_MTK_TPHY
> +	bool "MediaTek T-PHY Driver"
> +	depends on PHY
> +	depends on ARCH_MEDIATEK || SOC_MT7621
> +	select REGMAP
> +	select SYSCON
> +	help
> +	  MediaTek T-PHY driver supports usb2.0, usb3.0 ports, PCIe and
> +	  SATA, and meanwhile supports two version T-PHY which have
> +	  different banks layout, the T-PHY with shared banks between
> +	  multi-ports is first version, otherwise is second veriosn,

s/veriosn/version/

> +	  so you can easily distinguish them by banks layout.
> +

Re: [PATCH 0/3] phy: mediatek: add MIPI DSI PHY driver

[David Lechner]

On 9/15/26 10:00 AM, Julien Stephan wrote:
> This series adds a mipi-dsi PHY driver MR8183 compatible SoC such as the
> Genio-350 EVK.  The driver is ported from the kernel driver.
> 
> Patches 1 and 2 are preparatory patches: drivers/phy/ already carries 4
> MediaTek PHY drivers and this series adds another one, so collect them
> under drivers/phy/mediatek/ like the other vendors do. Kconfig symbol
> names are unchanged, so no defconfig is affected. Also sort entries in
> Makefiles and Kconfig.
> 
> Patch 3 adds the MIPI DSI PHY driver itself, supporting MT8183-compatible
> SoCs, based on kernel commit 2ec9c210c1f9 ("phy: mediatek: Add support
> for MT8196 MIPI DSI PHY").
> 
> Two deliberate deviations from the kernel driver:
> 
> - The kernel registers the MIPI TX PLL as a clock provider and hands it
>   to the DSI host as its "hs" clock. U-Boot has no consumer for that
>   clock, so the PLL clk_ops are folded into the PHY ops:
>   determine_rate + set_rate become .configure(), and prepare_enable
>   becomes .power_on().
> 
> - The kernel reads per-lane impedance trim codes from the
>   "calibration-data" nvmem cell. MT8365 doe snot have that cell in DT yet,

s/doe snot/does not/ (makes me imagine an AI generated image of a deer with
a runny nose)

>   so rt_code[] stays zeroed and the SoC layer falls back to the same
>   0x210 mid-scale default the kernel uses when the cell is absent. This
>   can be wired up later.
> 
> Tested on Genio 350 (MT8365). The DSI host side that consumes this PHY
> is sent separately to ease review
> 
Most of my comments were just for typos, so could fix up while applying if
nothing more serious comes up.

Re: [PATCH 3/3] phy: phy-mtk-mipi-dsi: add new driver

[Julien Stephan]

Le mer. 23 sept. 2026 à 17:50, David Lechner <dlechner@baylibre.com> a écrit :
>
> On 9/15/26 10:00 AM, Julien Stephan wrote:
> > Add a new driver for the MIPI DSI PHY. The driver supports MT8183
> > compatible SoCs. The driver is base on the corresponding kernel driver
>
> s/base/based/
>
> > commit 2ec9c210c1f9 ("phy: mediatek: Add support for MT8196 MIPI DSI PHY")
> >
> > Few notes about the port from kernel:
>
> s/Few/A few/
>
> > - tested on Genio-350 which does not have nvmem-cells, so keep rt_code[]
> >   zeroed and fallback to 0x210 has kernel does when no cell available.
>
> s/has/as the/
>
> >   Can be implemented later.
> > - PLL is not registered as a clock provider:
> >     - configure() = determine_rate+set_rate
> >     - power_on() = clk_prepare_enable
> >   configure() takes a struct phy_configure_opts_mipi_dphy and uses its
> >   hs_clk_rate member, which carries the per-lane data rate the kernel
> >   would have set on the "hs" clock.
> >
>
> ...
>
> > +static int mtk_mipi_tx_pll_enable(struct mtk_mipi_tx *mipi_tx)
> > +{
> > +     void __iomem *base = mipi_tx->regs;
> > +     unsigned int txdiv, txdiv0;
> > +     u64 pcw;
> > +
> > +     dev_dbg(mipi_tx->dev, "enable: %llu bps\n", mipi_tx->data_rate);
> > +
> > +     if (mipi_tx->data_rate >= 2000000000) {
> > +             txdiv = 1;
> > +             txdiv0 = 0;
> > +     } else if (mipi_tx->data_rate >= 1000000000) {
> > +             txdiv = 2;
> > +             txdiv0 = 1;
> > +     } else if (mipi_tx->data_rate >= 500000000) {
> > +             txdiv = 4;
> > +             txdiv0 = 2;
> > +     } else if (mipi_tx->data_rate > 250000000) {
> > +             txdiv = 8;
> > +             txdiv0 = 3;
> > +     } else if (mipi_tx->data_rate >= 125000000) {
> > +             txdiv = 16;
> > +             txdiv0 = 4;
> > +     } else {
> > +             return -EINVAL;
> > +     }
> > +
> > +     mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
> > +
> > +     mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
> > +     mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
> > +     udelay(1);
> > +     mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
> > +     pcw = div_u64(mipi_tx->data_rate * txdiv << 24, MIPITX_PLL_REF_RATE);
>
> (mipi_tx->data_rate * txdiv) << 24
>
> For those of us that can't remember order of operations.
>
> > +     writel(pcw, base + MIPITX_PLL_CON0);
> > +     mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);
> > +     mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
> > +
> > +     return 0;
> > +}
> > +
>
> ...
>
> > +static void mtk_mipi_tx_power_on_signal(struct mtk_mipi_tx *mipi_tx)
> > +{
> > +     void __iomem *base = mipi_tx->regs;
> > +
> > +     /* BG_LPF_EN / BG_CORE_EN */
> > +     writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
> > +     udelay(30);
> > +     writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
> > +
> > +     /* Switch OFF each Lane */
> > +     mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
> > +     mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
> > +     mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
> > +     mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
> > +     mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
> > +
> > +     mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,
> > +                          (mipi_tx->mipitx_drive - 3000) / 200);
>
> Is this 3000 supposed to be MIPITX_DRIVE_MIN_UA?

Hmm probably, but not sure. This is copied verbatim from kernel, so I
didn't change it in v2
>
> > +
> > +     mtk_mipi_tx_config_calibration_data(mipi_tx);
> > +
> > +     mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
> > +}
> > +
>
> ...
>
> > +     /*
> > +      * The kernel reads the per-lane impedance trim codes from the
> > +      * "calibration-data" nvmem cell. No MediaTek board describes that cell
>
> Technically, mipi_tx0: dsi-phy@11e50000 does in mt8183.dtsi
>
> Not saying we need to implement it right now though. Just the comment isn't
> 100% accurate.
>
> > +      * in its device tree yet, so rt_code[] is left zeroed here and the
> > +      * SoC layer substitutes the same mid-scale default the kernel uses
> > +      * when the cell is absent.
> > +      */
> > +
> > +     return 0;
> > +}
> > +