From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: "Duan, Zhenzhong" <zhenzhong.duan@intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"clg@redhat.com" <clg@redhat.com>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"mst@redhat.com" <mst@redhat.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"jasowang@redhat.com" <jasowang@redhat.com>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"Tian, Kevin" <kevin.tian@intel.com>,
"Liu, Yi L" <yi.l.liu@intel.com>,
"Peng, Chao P" <chao.p.peng@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode
Date: Mon, 27 May 2024 05:14:09 +0000 [thread overview]
Message-ID: <eeffbeca-33c3-4a88-9cb8-23c8aa234186@eviden.com> (raw)
In-Reply-To: <SJ0PR11MB6744454F40A7E7E56967E2F092F02@SJ0PR11MB6744.namprd11.prod.outlook.com>
On 27/05/2024 05:16, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
>
>
> Hi Clement,
>
>> -----Original Message-----
>> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
>> Sent: Friday, May 24, 2024 9:57 PM
>> To: Duan, Zhenzhong <zhenzhong.duan@intel.com>; qemu-
>> devel@nongnu.org
>> Cc: alex.williamson@redhat.com; clg@redhat.com; eric.auger@redhat.com;
>> mst@redhat.com; peterx@redhat.com; jasowang@redhat.com;
>> jgg@nvidia.com; nicolinc@nvidia.com; joao.m.martins@oracle.com; Tian,
>> Kevin <kevin.tian@intel.com>; Liu, Yi L <yi.l.liu@intel.com>; Peng, Chao P
>> <chao.p.peng@intel.com>; Paolo Bonzini <pbonzini@redhat.com>; Richard
>> Henderson <richard.henderson@linaro.org>; Eduardo Habkost
>> <eduardo@habkost.net>; Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
>> Subject: Re: [PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in
>> scalable modren mode
>>
>> Hi Zhenzhong
>>
>> On 22/05/2024 08:23, Zhenzhong Duan wrote:
>>> Caution: External email. Do not open attachments or click links, unless this
>> email comes from a known sender and you know the content is safe.
>>>
>>> According to VTD spec, stage-1 page table could support 4-level and
>>> 5-level paging.
>>>
>>> However, 5-level paging translation emulation is unsupported yet.
>>> That means the only supported value for aw_bits is 48.
>>>
>>> So default aw_bits to 48 in scalable modern mode. In other cases,
>>> it is still default to 39 for compatibility.
>>>
>>> Add a check to ensure user specified value is 48 in modern mode
>>> for now.
>>>
>>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
>>> ---
>>> hw/i386/intel_iommu.c | 16 +++++++++++++++-
>>> 1 file changed, 15 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>>> index e07daaba99..a4c241ea96 100644
>>> --- a/hw/i386/intel_iommu.c
>>> +++ b/hw/i386/intel_iommu.c
>>> @@ -3748,7 +3748,7 @@ static Property vtd_properties[] = {
>>> ON_OFF_AUTO_AUTO),
>>> DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim,
>> false),
>>> DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
>>> - VTD_HOST_ADDRESS_WIDTH),
>>> + 0xff),
>> you could define a constant for this invalid value
> Sure, maybe VTD_HOST_ADDRESS_WIDTH_UNDEFINED?
Yes, fine for me
>
> Thanks
> Zhenzhong
>
>>> DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode,
>> FALSE),
>>> DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState,
>> scalable_mode, FALSE),
>>> DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState,
>> snoop_control, false),
>>> @@ -4663,6 +4663,14 @@ static bool
>> vtd_decide_config(IntelIOMMUState *s, Error **errp)
>>> }
>>> }
>>>
>>> + if (s->aw_bits == 0xff) {
>>> + if (s->scalable_modern) {
>>> + s->aw_bits = VTD_HOST_AW_48BIT;
>>> + } else {
>>> + s->aw_bits = VTD_HOST_AW_39BIT;
>>> + }
>>> + }
>>> +
>>> if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
>>> (s->aw_bits != VTD_HOST_AW_48BIT) &&
>>> !s->scalable_modern) {
>>> @@ -4671,6 +4679,12 @@ static bool
>> vtd_decide_config(IntelIOMMUState *s, Error **errp)
>>> return false;
>>> }
>>>
>>> + if ((s->aw_bits != VTD_HOST_AW_48BIT) && s->scalable_modern) {
>>> + error_setg(errp, "Supported values for aw-bits are: %d",
>> specify 'in modern mode' in the message?
>>> + VTD_HOST_AW_48BIT);
>>> + return false;
>>> + }
>>> +
>>> if (s->scalable_mode && !s->dma_drain) {
>>> error_setg(errp, "Need to set dma_drain for scalable mode");
>>> return false;
>>> --
>>> 2.34.1
>>>
>> #cmd
next prev parent reply other threads:[~2024-05-27 5:15 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-22 6:22 [PATCH rfcv2 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-05-22 6:22 ` [PATCH rfcv2 01/17] intel_iommu: Update version to 3.0 and add the latest fault reasons Zhenzhong Duan
2024-05-22 6:22 ` [PATCH rfcv2 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-05-22 6:22 ` [PATCH rfcv2 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 04/17] intel_iommu: Flush stage-2 cache in PADID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-05-24 13:57 ` CLEMENT MATHIEU--DRIF
2024-05-27 3:17 ` Duan, Zhenzhong
2024-05-22 6:23 ` [PATCH rfcv2 07/17] intel_iommu: check if the input address is canonical Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 08/17] intel_iommu: set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-05-24 13:57 ` CLEMENT MATHIEU--DRIF
2024-05-27 3:17 ` Duan, Zhenzhong
2024-05-22 6:23 ` [PATCH rfcv2 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 11/17] intel_iommu: Extract device IOTLB invalidation logic Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 12/17] intel_iommu: add an internal API to find an address space with PASID Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 13/17] intel_iommu: add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 14/17] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 15/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode Zhenzhong Duan
2024-05-24 13:56 ` CLEMENT MATHIEU--DRIF
2024-05-27 3:16 ` Duan, Zhenzhong
2024-05-27 5:14 ` CLEMENT MATHIEU--DRIF [this message]
2024-05-22 6:23 ` [PATCH rfcv2 16/17] intel_iommu: Modify x-scalable-mode to be string option Zhenzhong Duan
2024-05-22 6:23 ` [PATCH rfcv2 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-05-22 12:46 ` Thomas Huth
2024-05-23 9:46 ` Duan, Zhenzhong
2024-05-22 8:10 ` [PATCH rfcv2 00/17] intel_iommu: Enable stage-1 translation for emulated device Jason Wang
2024-05-23 9:35 ` Duan, Zhenzhong
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