Re: [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd and helpers into header file

["Khatri, Sunil" <sukhatri@amd.com>]

On 24-06-2026 06:29 pm, Khatri, Sunil wrote:
>
> On 23-06-2026 02:34 pm, Christian König wrote:
>> On 6/22/26 21:57, Shahyan Soltani wrote:
>>> Move struct amdgpu_mqd_prop, struct amdgpu_mqd, and helpers from the 
>>> monolithic amdgpu.h
>>> into existing amdgpu_mes.h file.
>>>
>>> This is part of the ongoing effort to reduce the size of amdgpu.h 
>>> into their own respective
>>> separate headers.
>>>
>>> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com>
>> Reviewed-by: Christian König <christian.koenig@amd.com>
>>
>> @Sunil can you take a look at that as well? Just to keep you updated 
>> on all userqueue stuff.
> LGTM,
> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
>
> Regards
> Sunil Khatri
>>
>> Thanks,
>> Christian.
>>
>>> ---
>>> Following v2's feedback struct amdgpu_mqd and helpers were moved into
>>> the existing amdgpu_mes.h instead of creating a new amdgpu_mqh.h file
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 48 
>>> +------------------------
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 ++++++++++++++++++++++++
>>>   2 files changed, 47 insertions(+), 47 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 61608acc0393..ca86cef62f44 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -96,7 +96,6 @@
>>>   #include "amdgpu_doorbell.h"
>>>   #include "amdgpu_amdkfd.h"
>>>   #include "amdgpu_discovery.h"
>>> -#include "amdgpu_mes.h"
>>>   #include "amdgpu_umc.h"
>>>   #include "amdgpu_mmhub.h"
>>>   #include "amdgpu_gfxhub.h"
>>> @@ -115,6 +114,7 @@
>>>   #include "amdgpu_eviction_fence.h"
>>>   #include "amdgpu_wb.h"
>>>   #include "amdgpu_ip.h"
>>> +#include "amdgpu_mes.h"
I remember one thing, if you moved them from amdgpu.h and again added it 
via include "amdgpu_mes.h", there seems to be less benefit of it as its 
always there in amdgpu.h. Just check if there is a possibility if that 
include could be removed totally and include amdgpu_mes.h explicitly 
only where its needed.

Regards
Sunil khatri
>>>   #include "amdgpu_sa.h"
>>>   #include "amdgpu_uid.h"
>>>   #include "amdgpu_video_codecs.h"
>>> @@ -609,44 +609,6 @@ struct amd_powerplay {
>>>                         (rid == 0x01) || \
>>>                         (rid == 0x10))))
>>>   -enum amdgpu_mqd_update_flag {
>>> -       AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1,
>>> -       AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2,
>>> -       AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */
>>> -};
>>> -
>>> -struct amdgpu_mqd_prop {
>>> -    uint64_t mqd_gpu_addr;
>>> -    uint64_t hqd_base_gpu_addr;
>>> -    uint64_t rptr_gpu_addr;
>>> -    uint64_t wptr_gpu_addr;
>>> -    uint32_t queue_size;
>>> -    bool use_doorbell;
>>> -    uint32_t doorbell_index;
>>> -    uint64_t eop_gpu_addr;
>>> -    uint32_t hqd_pipe_priority;
>>> -    uint32_t hqd_queue_priority;
>>> -    uint32_t mqd_stride_size;
>>> -    bool allow_tunneling;
>>> -    bool hqd_active;
>>> -    uint64_t shadow_addr;
>>> -    uint64_t gds_bkup_addr;
>>> -    uint64_t csa_addr;
>>> -    uint64_t fence_address;
>>> -    bool tmz_queue;
>>> -    bool kernel_queue;
>>> -    uint32_t *cu_mask;
>>> -    uint32_t cu_mask_count;
>>> -    uint32_t cu_flags;
>>> -    bool is_user_cu_masked;
>>> -};
>>> -
>>> -struct amdgpu_mqd {
>>> -    unsigned mqd_size;
>>> -    int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
>>> -            struct amdgpu_mqd_prop *p);
>>> -};
>>> -
>>>   struct amdgpu_pcie_reset_ctx {
>>>       bool in_link_reset;
>>>       bool occurs_dpc;
>>> @@ -1034,14 +996,6 @@ struct amdgpu_device {
>>>       struct amdgpu_kfd_dev        kfd;
>>>   };
>>>   -/*
>>> - * MES FW uses address(mqd_addr + sizeof(struct mqd) + 
>>> 3*sizeof(uint32_t))
>>> - * as fence address and writes a 32 bit fence value to this address.
>>> - * Driver needs to allocate at least 4 DWs extra memory in addition to
>>> - * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE 
>>> for safety.
>>> - */
>>> -#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) 
>>> AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32))
>>> -
>>>   static inline uint32_t amdgpu_ip_version(const struct 
>>> amdgpu_device *adev,
>>>                        uint8_t ip, uint8_t inst)
>>>   {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h 
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
>>> index 5255360353f4..7b4cfb5c8f83 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
>>> @@ -438,6 +438,52 @@ struct amdgpu_mes_funcs {
>>>                     struct mes_inv_tlbs_pasid_input *input);
>>>   };
>>>   +enum amdgpu_mqd_update_flag {
>>> +    AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1,
>>> +    AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2,
>>> +    AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */
>>> +};
>>> +
>>> +struct amdgpu_mqd_prop {
>>> +    uint64_t mqd_gpu_addr;
>>> +    uint64_t hqd_base_gpu_addr;
>>> +    uint64_t rptr_gpu_addr;
>>> +    uint64_t wptr_gpu_addr;
>>> +    uint32_t queue_size;
>>> +    bool use_doorbell;
>>> +    uint32_t doorbell_index;
>>> +    uint64_t eop_gpu_addr;
>>> +    uint32_t hqd_pipe_priority;
>>> +    uint32_t hqd_queue_priority;
>>> +    uint32_t mqd_stride_size;
>>> +    bool allow_tunneling;
>>> +    bool hqd_active;
>>> +    uint64_t shadow_addr;
>>> +    uint64_t gds_bkup_addr;
>>> +    uint64_t csa_addr;
>>> +    uint64_t fence_address;
>>> +    bool tmz_queue;
>>> +    bool kernel_queue;
>>> +    uint32_t *cu_mask;
>>> +    uint32_t cu_mask_count;
>>> +    uint32_t cu_flags;
>>> +    bool is_user_cu_masked;
>>> +};
>>> +
>>> +struct amdgpu_mqd {
>>> +    unsigned mqd_size;
>>> +    int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
>>> +            struct amdgpu_mqd_prop *p);
>>> +};
>>> +
>>> +/*
>>> + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 
>>> 3*sizeof(uint32_t))
>>> + * as fence address and writes a 32 bit fence value to this address.
>>> + * Driver needs to allocate at least 4 DWs extra memory in addition to
>>> + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE 
>>> for safety.
>>> + */
>>> +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) 
>>> AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32))
>>> +
>>>   #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \
>>>       (adev)->mes.kiq_hw_init((adev), (xcc_id))
>>>   #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \