* [PATCH v3 0/8] refactor monolithic amdgpu.h
@ 2026-06-22 19:57 Shahyan Soltani
2026-06-22 19:57 ` [PATCH v3 1/8] drm/amdgpu: move struct amdgpu_wb and helpers into separate files Shahyan Soltani
` (7 more replies)
0 siblings, 8 replies; 17+ messages in thread
From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, christian.koenig
This patch series refactors amdgpu.h by moving several structures and their
associated helpers into dedicated or existing header files. This improves
code organization and makes the structure easier to parse.
v3:
- Dropped patch "Move struct amdgpu_sa_manager out of the monolithic header
amdgpu.h into its own dedicated header amdgpu_sa.h" addressing v2's feedback
- Removed the "_device_" part for amdgpu_wb functions addressing v2's feedback
- Patches 2 and 7 are unchanged but can be dropped if amdgpu_uid is not
desired to be removed from amdgpu.h
- Removed amdgpu_mqd.h and moved the relevant structs and helpers into
amdgpu_mes.h addressing v2's feedback
- Dropped patch "Move struct amdgpu_init_level and helpers from the monolithic amdgpu.h
file into a new amdgpu_init_level.h file." addressing v2's feedback
- Dropped patch "Remove #include "amdgpu_init_level.h" from amdgpu.h and add forward
declaration of struct amdgpu_init_level."
v2:
- Moved amdgpu_device_wb_get()/free() into new amdgpu_wb.c file and
amdgpu_device_set_uid()/get_uid() into new amdgpu_uid.c file
(addressing v1 review feedback)
- Removed v1 patches 8, 10, and 11 (addressing v1 review feedback)
- Moved the includes of headers amdgpu_uid.h, amdgpu_init_level.h
and amdgpu_video_codecs.h out of amdgpu.h into files where they are
actually used (addressing v1 review feedback)
Notes from v2:
- Moving the includes out of amdgpu.h into where they are actually used
caused the commits to go into different subsystems like /pm.
- Dropping patches 9, 10, and 11 is advised if this isn't desirable.
Shahyan Soltani (8):
drm/amdgpu: move struct amdgpu_wb and helpers into separate files
drm/amdgpu: move struct amdgpu_uid and helpers into separate files
drm/amdgpu: move struct amdgpu_video_codecs and helpers into header
file
drm/amdgpu: move struct amdgpu_mqd and helpers into header file
drm/amdgpu: move amdgpu_acpi helpers into new header
drm/amdgpu: move amdgpu_allowed_register_entry into
amdgpu_reg_access.h
drm/amdgpu: include amdgpu_uid.h only where needed
drm/amdgpu: include amdgpu_video_codecs.h only where needed
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 289 +-----------------
drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h | 151 +++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 96 +-----
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 14 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 +++
.../gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 8 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 18 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c | 75 +++++
drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h | 50 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 6 +-
.../gpu/drm/amd/amdgpu/amdgpu_video_codecs.h | 47 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 8 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_wb.c | 71 +++++
drivers/gpu/drm/amd/amdgpu/amdgpu_wb.h | 100 ++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik.c | 1 +
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 +-
drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 4 +-
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 6 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 8 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +-
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 10 +-
drivers/gpu/drm/amd/amdgpu/si.c | 1 +
drivers/gpu/drm/amd/amdgpu/si_dma.c | 8 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc24.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/vi.c | 1 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 1 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 1 +
.../drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 1 +
53 files changed, 679 insertions(+), 491 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_video_codecs.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_wb.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_wb.h
--
2.54.0
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 1/8] drm/amdgpu: move struct amdgpu_wb and helpers into separate files 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 2026-06-23 8:52 ` Christian König 2026-06-22 19:57 ` [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid " Shahyan Soltani ` (6 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Move struct amdgpu_wb and helpers out of the monolithic header amdgpu.h into its own dedicated header amdgpu_wb.h. Move functions amdgpu_device_wb_get() and amdgpu_device_wb_free out of amdgpu_device.c into new dedicated amdgpu_wb.c file. Rename amdgpu_device_wb_get() and amdgpu_device_wb_free() into amdgpu_wb_get() and amdgpu_wb_free(). Update amdgpu/Makefile to build amdgpu_wb.o. This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> --- Following v2's feedback functions amdgpu_device_wb* was renamed to amdgpu_wb* --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 68 +------------ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 14 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 16 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 18 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_wb.c | 71 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_wb.h | 100 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 +- drivers/gpu/drm/amd/amdgpu/mes_userqueue.c | 4 +- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 6 +- drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 6 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 8 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 10 +- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 10 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 8 +- 33 files changed, 283 insertions(+), 224 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_wb.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_wb.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index ba80542ead9d..10dc7cfd607e 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -71,7 +71,8 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms amdgpu_fw_attestation.o amdgpu_securedisplay.o \ amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o amdgpu_lockdep.o \ amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \ - amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o + amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o \ + amdgpu_wb.o amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b68aea97c166..4ffcc0cc6404 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -113,6 +113,7 @@ #include "amdgpu_reg_state.h" #include "amdgpu_userq.h" #include "amdgpu_eviction_fence.h" +#include "amdgpu_wb.h" #include "amdgpu_ip.h" #include "amdgpu_sa.h" #if defined(CONFIG_DRM_AMD_ISP) @@ -429,73 +430,6 @@ struct amdgpu_fpriv { int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); -/* - * Writeback - */ -#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ - -/** - * struct amdgpu_wb - This struct is used for small GPU memory allocation. - * - * This struct is used to allocate a small amount of GPU memory that can be - * used to shadow certain states into the memory. This is especially useful for - * providing easy CPU access to some states without requiring register access - * (e.g., if some block is power gated, reading register may be problematic). - * - * Note: the term writeback was initially used because many of the amdgpu - * components had some level of writeback memory, and this struct initially - * described those components. - */ -struct amdgpu_wb { - - /** - * @wb_obj: - * - * Buffer Object used for the writeback memory. - */ - struct amdgpu_bo *wb_obj; - - /** - * @wb: - * - * Pointer to the first writeback slot. In terms of CPU address - * this value can be accessed directly by using the offset as an index. - * For the GPU address, it is necessary to use gpu_addr and the offset. - */ - uint32_t *wb; - - /** - * @gpu_addr: - * - * Writeback base address in the GPU. - */ - uint64_t gpu_addr; - - /** - * @num_wb: - * - * Number of writeback slots reserved for amdgpu. - */ - u32 num_wb; - - /** - * @used: - * - * Track the writeback slot already used. - */ - unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; - - /** - * @lock: - * - * Protects read and write of the used field array. - */ - spinlock_t lock; -}; - -int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); -void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); - /* * Benchmarking */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5442a1fc1c37..d6931e1184d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1063,51 +1063,6 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev) return 0; } -/** - * amdgpu_device_wb_get - Allocate a wb entry - * - * @adev: amdgpu_device pointer - * @wb: wb index - * - * Allocate a wb slot for use by the driver (all asics). - * Returns 0 on success or -EINVAL on failure. - */ -int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb) -{ - unsigned long flags, offset; - - spin_lock_irqsave(&adev->wb.lock, flags); - offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); - if (offset < adev->wb.num_wb) { - __set_bit(offset, adev->wb.used); - spin_unlock_irqrestore(&adev->wb.lock, flags); - *wb = offset << 3; /* convert to dw offset */ - return 0; - } else { - spin_unlock_irqrestore(&adev->wb.lock, flags); - return -EINVAL; - } -} - -/** - * amdgpu_device_wb_free - Free a wb entry - * - * @adev: amdgpu_device pointer - * @wb: wb index - * - * Free a wb slot allocated for use by the driver (all asics) - */ -void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) -{ - unsigned long flags; - - wb >>= 3; - spin_lock_irqsave(&adev->wb.lock, flags); - if (wb < adev->wb.num_wb) - __clear_bit(wb, adev->wb.used); - spin_unlock_irqrestore(&adev->wb.lock, flags); -} - /** * amdgpu_device_resize_fb_bar - try to resize FB BAR * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 982b41606d48..4dffbc95c89c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1170,7 +1170,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_ BUG_ON(!ring->funcs->emit_rreg); spin_lock_irqsave(&kiq->ring_lock, flags); - if (amdgpu_device_wb_get(adev, ®_val_offs)) { + if (amdgpu_wb_get(adev, ®_val_offs)) { pr_err("critical bug! too many kiq readers\n"); goto failed_unlock; } @@ -1213,7 +1213,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_ mb(); value = adev->wb.wb[reg_val_offs]; - amdgpu_device_wb_free(adev, reg_val_offs); + amdgpu_wb_free(adev, reg_val_offs); return value; failed_undo: @@ -1222,7 +1222,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_ spin_unlock_irqrestore(&kiq->ring_lock, flags); failed_kiq_read: if (reg_val_offs) - amdgpu_device_wb_free(adev, reg_val_offs); + amdgpu_wb_free(adev, reg_val_offs); dev_err(adev->dev, "failed to read reg:%x\n", reg); return ~0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c index a6419246e9c2..c2a10b41804a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c @@ -75,13 +75,13 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, } else { unsigned wptr_offs, rptr_offs; - r = amdgpu_device_wb_get(adev, &wptr_offs); + r = amdgpu_wb_get(adev, &wptr_offs); if (r) return r; - r = amdgpu_device_wb_get(adev, &rptr_offs); + r = amdgpu_wb_get(adev, &rptr_offs); if (r) { - amdgpu_device_wb_free(adev, wptr_offs); + amdgpu_wb_free(adev, wptr_offs); return r; } @@ -90,8 +90,8 @@ int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, &ih->ring_obj, &ih->gpu_addr, (void **)&ih->ring); if (r) { - amdgpu_device_wb_free(adev, rptr_offs); - amdgpu_device_wb_free(adev, wptr_offs); + amdgpu_wb_free(adev, rptr_offs); + amdgpu_wb_free(adev, wptr_offs); return r; } @@ -131,8 +131,8 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) } else { amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, (void **)&ih->ring); - amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); - amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); + amdgpu_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); + amdgpu_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 6c0dde3786e3..7fbb6677d5ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -183,7 +183,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.sdma_hqd_mask[0]); for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { - r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]); + r = amdgpu_wb_get(adev, &adev->mes.sch_ctx_offs[i]); if (r) { dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", @@ -195,7 +195,7 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.sch_ctx_ptr[i] = (uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]]; - r = amdgpu_device_wb_get(adev, + r = amdgpu_wb_get(adev, &adev->mes.query_status_fence_offs[i]); if (r) { dev_err(adev->dev, @@ -263,9 +263,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev) error: for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { if (adev->mes.sch_ctx_ptr[i]) - amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); + amdgpu_wb_free(adev, adev->mes.sch_ctx_offs[i]); if (adev->mes.query_status_fence_ptr[i]) - amdgpu_device_wb_free(adev, + amdgpu_wb_free(adev, adev->mes.query_status_fence_offs[i]); if (adev->mes.hung_queue_db_array_gpu_obj[i]) amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], @@ -295,9 +295,9 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) &adev->mes.hung_queue_db_array_gpu_addr[i], &adev->mes.hung_queue_db_array_cpu_addr[i]); if (adev->mes.sch_ctx_ptr[i]) - amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); + amdgpu_wb_free(adev, adev->mes.sch_ctx_offs[i]); if (adev->mes.query_status_fence_ptr[i]) - amdgpu_device_wb_free(adev, + amdgpu_wb_free(adev, adev->mes.query_status_fence_offs[i]); } @@ -567,7 +567,7 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, uint64_t read_val_gpu_addr; uint32_t *read_val_ptr; - if (amdgpu_device_wb_get(adev, &addr_offset)) { + if (amdgpu_wb_get(adev, &addr_offset)) { dev_err(adev->dev, "critical bug! too many mes readers\n"); goto error; } @@ -593,7 +593,7 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, error: if (addr_offset) - amdgpu_device_wb_free(adev, addr_offset); + amdgpu_wb_free(adev, addr_offset); return val; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 9fd41801abd2..2dec05f2f135 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -264,31 +264,31 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, return r; } - r = amdgpu_device_wb_get(adev, &ring->rptr_offs); + r = amdgpu_wb_get(adev, &ring->rptr_offs); if (r) { dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); return r; } - r = amdgpu_device_wb_get(adev, &ring->wptr_offs); + r = amdgpu_wb_get(adev, &ring->wptr_offs); if (r) { dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); return r; } - r = amdgpu_device_wb_get(adev, &ring->fence_offs); + r = amdgpu_wb_get(adev, &ring->fence_offs); if (r) { dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); return r; } - r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs); + r = amdgpu_wb_get(adev, &ring->trail_fence_offs); if (r) { dev_err(adev->dev, "(%d) ring trail_fence_offs wb alloc failed\n", r); return r; } - r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs); + r = amdgpu_wb_get(adev, &ring->cond_exe_offs); if (r) { dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); return r; @@ -401,11 +401,11 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) ring->sched.ready = false; - amdgpu_device_wb_free(ring->adev, ring->rptr_offs); - amdgpu_device_wb_free(ring->adev, ring->wptr_offs); + amdgpu_wb_free(ring->adev, ring->rptr_offs); + amdgpu_wb_free(ring->adev, ring->wptr_offs); - amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs); - amdgpu_device_wb_free(ring->adev, ring->fence_offs); + amdgpu_wb_free(ring->adev, ring->cond_exe_offs); + amdgpu_wb_free(ring->adev, ring->fence_offs); amdgpu_bo_free_kernel(&ring->ring_obj, &ring->gpu_addr, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index cd707d70a0bf..3985d56008cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -272,7 +272,7 @@ static int umsch_mm_init(struct amdgpu_device *adev) adev->umsch_mm.engine_mask = (1 << UMSCH_SWIP_ENGINE_TYPE_VPE); adev->umsch_mm.vpe_hqd_mask = 0xfe; - r = amdgpu_device_wb_get(adev, &adev->umsch_mm.wb_index); + r = amdgpu_wb_get(adev, &adev->umsch_mm.wb_index); if (r) { dev_err(adev->dev, "failed to alloc wb for umsch: %d\n", r); return r; @@ -288,7 +288,7 @@ static int umsch_mm_init(struct amdgpu_device *adev) (void **)&adev->umsch_mm.cmd_buf_ptr); if (r) { dev_err(adev->dev, "failed to allocate cmdbuf bo %d\n", r); - amdgpu_device_wb_free(adev, adev->umsch_mm.wb_index); + amdgpu_wb_free(adev, adev->umsch_mm.wb_index); return r; } @@ -380,7 +380,7 @@ static int umsch_mm_sw_fini(struct amdgpu_ip_block *ip_block) &adev->umsch_mm.log_gpu_addr, (void **)&adev->umsch_mm.log_cpu_addr); - amdgpu_device_wb_free(adev, adev->umsch_mm.wb_index); + amdgpu_wb_free(adev, adev->umsch_mm.wb_index); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 7bf74ff93fbd..2b45010b7ebe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -789,7 +789,7 @@ static int vpe_ring_test_ring(struct amdgpu_ring *ring) uint64_t wb_addr; int ret; - ret = amdgpu_device_wb_get(adev, &index); + ret = amdgpu_wb_get(adev, &index); if (ret) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); return ret; @@ -818,7 +818,7 @@ static int vpe_ring_test_ring(struct amdgpu_ring *ring) ret = -ETIMEDOUT; out: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return ret; } @@ -833,7 +833,7 @@ static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) uint64_t wb_addr; int ret; - ret = amdgpu_device_wb_get(adev, &index); + ret = amdgpu_wb_get(adev, &index); if (ret) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret); return ret; @@ -872,7 +872,7 @@ static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_wb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_wb.c new file mode 100644 index 000000000000..616339959813 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_wb.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include <linux/spinlock.h> + +#include "amdgpu.h" +#include "amdgpu_wb.h" + +/** + * amdgpu_wb_get - Allocate a wb entry + * + * @adev: amdgpu_device pointer + * @wb: wb index + * + * Allocate a wb slot for use by the driver (all asics). + * Returns 0 on success or -EINVAL on failure. + */ +int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb) +{ + unsigned long flags, offset; + + spin_lock_irqsave(&adev->wb.lock, flags); + offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb); + if (offset < adev->wb.num_wb) { + __set_bit(offset, adev->wb.used); + spin_unlock_irqrestore(&adev->wb.lock, flags); + *wb = offset << 3; /* convert to dw offset */ + return 0; + } else { + spin_unlock_irqrestore(&adev->wb.lock, flags); + return -EINVAL; + } +} + +/** + * amdgpu_wb_free - Free a wb entry + * + * @adev: amdgpu_device pointer + * @wb: wb index + * + * Free a wb slot allocated for use by the driver (all asics) + */ +void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb) +{ + unsigned long flags; + + wb >>= 3; + spin_lock_irqsave(&adev->wb.lock, flags); + if (wb < adev->wb.num_wb) + __clear_bit(wb, adev->wb.used); + spin_unlock_irqrestore(&adev->wb.lock, flags); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_wb.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_wb.h new file mode 100644 index 000000000000..21b82849ad07 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_wb.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT + * + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_WB_H__ +#define __AMDGPU_WB_H__ + +#include <linux/types.h> +#include <linux/spinlock_types.h> +#include <linux/math.h> + +/* + * Writeback + */ +#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ + +/** + * struct amdgpu_wb - This struct is used for small GPU memory allocation. + * + * This struct is used to allocate a small amount of GPU memory that can be + * used to shadow certain states into the memory. This is especially useful for + * providing easy CPU access to some states without requiring register access + * (e.g., if some block is power gated, reading register may be problematic). + * + * Note: the term writeback was initially used because many of the amdgpu + * components had some level of writeback memory, and this struct initially + * described those components. + */ + +struct amdgpu_bo; +struct amdgpu_device; + +struct amdgpu_wb { + + /** + * @wb_obj: + * + * Buffer Object used for the writeback memory. + */ + struct amdgpu_bo *wb_obj; + + /** + * @wb: + * + * Pointer to the first writeback slot. In terms of CPU address + * this value can be accessed directly by using the offset as an index. + * For the GPU address, it is necessary to use gpu_addr and the offset. + */ + uint32_t *wb; + + /** + * @gpu_addr: + * + * Writeback base address in the GPU. + */ + uint64_t gpu_addr; + + /** + * @num_wb: + * + * Number of writeback slots reserved for amdgpu. + */ + u32 num_wb; + + /** + * @used: + * + * Track the writeback slot already used. + */ + unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; + + /** + * @lock: + * + * Protects read and write of the used field array. + */ + spinlock_t lock; +}; + +int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); +void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 120da838ac28..b703ef1fe340 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -605,7 +605,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -635,7 +635,7 @@ static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) r = -ETIMEDOUT; error_free_wb: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -658,7 +658,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -699,7 +699,7 @@ static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 76d4c33a6e65..98e6cee19a16 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4080,7 +4080,7 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -4121,7 +4121,7 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 4315a6b6c1be..cc275d40d587 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -627,7 +627,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -668,7 +668,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index f8280cc81a66..e350582fff26 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -507,7 +507,7 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -548,7 +548,7 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c index 30a38190f98a..f99760ac653a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -320,7 +320,7 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -361,7 +361,7 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 59728dfd8a7b..dfcc3943bf65 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -876,7 +876,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) uint32_t tmp; long r; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -917,7 +917,7 @@ static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index f836621c46eb..3da5a17af1ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1232,7 +1232,7 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) uint32_t tmp; long r; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -1273,7 +1273,7 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -4267,7 +4267,7 @@ static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) BUG_ON(!ring->funcs->emit_rreg); spin_lock_irqsave(&kiq->ring_lock, flags); - if (amdgpu_device_wb_get(adev, ®_val_offs)) { + if (amdgpu_wb_get(adev, ®_val_offs)) { pr_err("critical bug! too many kiq readers\n"); goto failed_unlock; } @@ -4315,7 +4315,7 @@ static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) mb(); value = (uint64_t)adev->wb.wb[reg_val_offs] | (uint64_t)adev->wb.wb[reg_val_offs + 1 ] << 32ULL; - amdgpu_device_wb_free(adev, reg_val_offs); + amdgpu_wb_free(adev, reg_val_offs); return value; failed_undo: @@ -4324,7 +4324,7 @@ static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) spin_unlock_irqrestore(&kiq->ring_lock, flags); failed_kiq_read: if (reg_val_offs) - amdgpu_device_wb_free(adev, reg_val_offs); + amdgpu_wb_free(adev, reg_val_offs); pr_err("failed to read gpu clock\n"); return ~0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index e50a66e9ee96..0b1ea4c643a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -459,7 +459,7 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) uint32_t tmp; long r; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -500,7 +500,7 @@ static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err1: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 5ad8dd18dc67..77f159593b88 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -520,7 +520,7 @@ static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) if (queue->state != AMDGPU_USERQ_STATE_MAPPED) return 0; - r = amdgpu_device_wb_get(adev, &fence_offset); + r = amdgpu_wb_get(adev, &fence_offset); if (r) return r; @@ -548,7 +548,7 @@ static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) r = -ETIMEDOUT; out: - amdgpu_device_wb_free(adev, fence_offset); + amdgpu_wb_free(adev, fence_offset); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 9e27d01cbfa3..8b87422be24e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -194,7 +194,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, timeout = 15 * 600 * 1000; } - ret = amdgpu_device_wb_get(adev, &status_offset); + ret = amdgpu_wb_get(adev, &status_offset); if (ret) return ret; @@ -266,7 +266,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, goto error_wb_free; } - amdgpu_device_wb_free(adev, status_offset); + amdgpu_wb_free(adev, status_offset); return 0; error_undo: @@ -277,7 +277,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, spin_unlock_irqrestore(&mes->ring_lock[0], flags); error_wb_free: - amdgpu_device_wb_free(adev, status_offset); + amdgpu_wb_free(adev, status_offset); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index d80a983b1b6c..05633b98f4e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -175,7 +175,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, timeout = 15 * 600 * 1000; } - ret = amdgpu_device_wb_get(adev, &status_offset); + ret = amdgpu_wb_get(adev, &status_offset); if (ret) return ret; @@ -253,7 +253,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, goto error_wb_free; } - amdgpu_device_wb_free(adev, status_offset); + amdgpu_wb_free(adev, status_offset); return 0; error_undo: @@ -264,7 +264,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, spin_unlock_irqrestore(ring_lock, flags); error_wb_free: - amdgpu_device_wb_free(adev, status_offset); + amdgpu_wb_free(adev, status_offset); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index 8007a6e69305..e95b8bcaf00a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -178,7 +178,7 @@ static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, timeout = 15 * 600 * 1000; } - ret = amdgpu_device_wb_get(adev, &status_offset); + ret = amdgpu_wb_get(adev, &status_offset); if (ret) return ret; @@ -253,7 +253,7 @@ static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, goto error_wb_free; } - amdgpu_device_wb_free(adev, status_offset); + amdgpu_wb_free(adev, status_offset); return 0; error_undo: @@ -264,7 +264,7 @@ static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, spin_unlock_irqrestore(ring_lock, flags); error_wb_free: - amdgpu_device_wb_free(adev, status_offset); + amdgpu_wb_free(adev, status_offset); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 93ec52c1f367..397b08c7173a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -536,7 +536,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -567,7 +567,7 @@ static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) r = -ETIMEDOUT; error_free_wb: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -590,7 +590,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -635,7 +635,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index e77261a64cf8..8a8353c3a7c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -810,7 +810,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -841,7 +841,7 @@ static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) r = -ETIMEDOUT; error_free_wb: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -864,7 +864,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -908,7 +908,7 @@ static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index cb64d17000df..20c8ebf0e159 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1468,7 +1468,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -1499,7 +1499,7 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) r = -ETIMEDOUT; error_free_wb: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -1522,7 +1522,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) u32 tmp = 0; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -1567,7 +1567,7 @@ static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 777a70852883..34e762eaffb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1064,7 +1064,7 @@ static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -1095,7 +1095,7 @@ static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring) r = -ETIMEDOUT; error_free_wb: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -1118,7 +1118,7 @@ static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) u32 tmp = 0; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -1163,7 +1163,7 @@ static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index fa02907217e0..3847dc08334a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1019,7 +1019,7 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) tmp = 0xCAFEDEAD; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -1031,7 +1031,7 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 20); if (r) { drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -1056,7 +1056,7 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) if (i >= adev->usec_timeout) r = -ETIMEDOUT; - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -1083,7 +1083,7 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) tmp = 0xCAFEDEAD; memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -1135,7 +1135,7 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index f6ecbc524c9b..bb2189cc882e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -919,7 +919,7 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) tmp = 0xCAFEDEAD; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -931,7 +931,7 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 20); if (r) { drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -956,7 +956,7 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) if (i >= adev->usec_timeout) r = -ETIMEDOUT; - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -983,7 +983,7 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) tmp = 0xCAFEDEAD; memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -1034,7 +1034,7 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index c208c584f912..9776b2582ab5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -910,7 +910,7 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) tmp = 0xCAFEDEAD; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -922,7 +922,7 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -947,7 +947,7 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) if (i >= adev->usec_timeout) r = -ETIMEDOUT; - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -974,7 +974,7 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) tmp = 0xCAFEDEAD; memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -1025,7 +1025,7 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 9f232805cd76..cd9ff90626d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -925,7 +925,7 @@ static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) tmp = 0xCAFEDEAD; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -937,7 +937,7 @@ static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -962,7 +962,7 @@ static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) if (i >= adev->usec_timeout) r = -ETIMEDOUT; - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -989,7 +989,7 @@ static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) tmp = 0xCAFEDEAD; memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -1040,7 +1040,7 @@ static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c index 14186e0ddb2c..b881f77602d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -915,7 +915,7 @@ static int sdma_v7_1_ring_test_ring(struct amdgpu_ring *ring) tmp = 0xCAFEDEAD; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); return r; @@ -927,7 +927,7 @@ static int sdma_v7_1_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -952,7 +952,7 @@ static int sdma_v7_1_ring_test_ring(struct amdgpu_ring *ring) if (i >= adev->usec_timeout) r = -ETIMEDOUT; - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -979,7 +979,7 @@ static int sdma_v7_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) tmp = 0xCAFEDEAD; memset(&ib, 0, sizeof(ib)); - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) { dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); return r; @@ -1030,7 +1030,7 @@ static int sdma_v7_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 549708075eb4..47f1d325bd1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -213,7 +213,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring) u32 tmp; u64 gpu_addr; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -242,7 +242,7 @@ static int si_dma_ring_test_ring(struct amdgpu_ring *ring) r = -ETIMEDOUT; error_free_wb: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } @@ -265,7 +265,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) u64 gpu_addr; long r; - r = amdgpu_device_wb_get(adev, &index); + r = amdgpu_wb_get(adev, &index); if (r) return r; @@ -304,7 +304,7 @@ static int si_dma_ring_test_ib(struct amdgpu_ring *ring, long timeout) amdgpu_ib_free(&ib, NULL); dma_fence_put(f); err0: - amdgpu_device_wb_free(adev, index); + amdgpu_wb_free(adev, index); return r; } -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 1/8] drm/amdgpu: move struct amdgpu_wb and helpers into separate files 2026-06-22 19:57 ` [PATCH v3 1/8] drm/amdgpu: move struct amdgpu_wb and helpers into separate files Shahyan Soltani @ 2026-06-23 8:52 ` Christian König 0 siblings, 0 replies; 17+ messages in thread From: Christian König @ 2026-06-23 8:52 UTC (permalink / raw) To: Shahyan Soltani, amd-gfx; +Cc: alexander.deucher On 6/22/26 21:57, Shahyan Soltani wrote: ... > /* > * Benchmarking > */ > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 5442a1fc1c37..d6931e1184d0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1063,51 +1063,6 @@ static int amdgpu_device_wb_init(struct amdgpu_device *adev) > return 0; > } I think we should move amdgpu_device_wb_init() and amdgpu_device_wb_fini() into amdgpu_wb.c as well. Apart from that looks good to me. Regards, Christian. ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid and helpers into separate files 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 1/8] drm/amdgpu: move struct amdgpu_wb and helpers into separate files Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 2026-06-23 8:55 ` Christian König 2026-06-22 19:57 ` [PATCH v3 3/8] drm/amdgpu: move struct amdgpu_video_codecs and helpers into header file Shahyan Soltani ` (5 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Move struct amdgpu_uid and helpers from the monolithic amdgpu.h file into a new amdgpu_uid.h file. Move functions amdgpu_device_set_uid() and amdgpu_device_get_uid() out of amdgpu_device.c into new dedicated amdgpu_uid.c file. Update amdgpu/Makefile to build amdgpu_uid.o This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> --- This patch and patch 7 can be dropped if moving amdgpu_uid out of amdgpu.h is not desirable. --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 22 +------ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 --------------- drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c | 75 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h | 50 +++++++++++++++ 5 files changed, 127 insertions(+), 72 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 10dc7cfd607e..ab5fdbb5e4b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o amdgpu_lockdep.o \ amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \ amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o \ - amdgpu_wb.o + amdgpu_wb.o amdgpu_uid.o amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4ffcc0cc6404..fe951a901d20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -116,6 +116,7 @@ #include "amdgpu_wb.h" #include "amdgpu_ip.h" #include "amdgpu_sa.h" +#include "amdgpu_uid.h" #if defined(CONFIG_DRM_AMD_ISP) #include "amdgpu_isp.h" #endif @@ -551,21 +552,6 @@ struct amdgpu_mmio_remap { struct amdgpu_bo *bo; }; -enum amdgpu_uid_type { - AMDGPU_UID_TYPE_XCD, - AMDGPU_UID_TYPE_AID, - AMDGPU_UID_TYPE_SOC, - AMDGPU_UID_TYPE_MID, - AMDGPU_UID_TYPE_MAX -}; - -#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ - -struct amdgpu_uid { - uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; - struct amdgpu_device *adev; -}; - #define MAX_UMA_OPTION_NAME 28 #define MAX_UMA_OPTION_ENTRIES 19 @@ -1530,10 +1516,4 @@ static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) return 0; } - -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, - enum amdgpu_uid_type type, uint8_t inst, - uint64_t uid); -uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, - enum amdgpu_uid_type type, uint8_t inst); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d6931e1184d0..8d55658ecb31 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6717,53 +6717,3 @@ ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset) size += sysfs_emit_at(buf, size, "\n"); return size; } - -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, - enum amdgpu_uid_type type, uint8_t inst, - uint64_t uid) -{ - if (!uid_info) - return; - - if (type >= AMDGPU_UID_TYPE_MAX) { - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", - type); - return; - } - - if (inst >= AMDGPU_UID_INST_MAX) { - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", - inst); - return; - } - - if (uid_info->uid[type][inst] != 0) { - dev_warn_once( - uid_info->adev->dev, - "Overwriting existing UID %llu for type %d instance %d\n", - uid_info->uid[type][inst], type, inst); - } - - uid_info->uid[type][inst] = uid; -} - -u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, - enum amdgpu_uid_type type, uint8_t inst) -{ - if (!uid_info) - return 0; - - if (type >= AMDGPU_UID_TYPE_MAX) { - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", - type); - return 0; - } - - if (inst >= AMDGPU_UID_INST_MAX) { - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", - inst); - return 0; - } - - return uid_info->uid[type][inst]; -} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c new file mode 100644 index 000000000000..6cf6b3f12271 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "amdgpu_uid.h" +#include <linux/dev_printk.h> +#include "amdgpu.h" + +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst, + uint64_t uid) +{ + if (!uid_info) + return; + + if (type >= AMDGPU_UID_TYPE_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", + type); + return; + } + + if (inst >= AMDGPU_UID_INST_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", + inst); + return; + } + + if (uid_info->uid[type][inst] != 0) { + dev_warn_once( + uid_info->adev->dev, + "Overwriting existing UID %llu for type %d instance %d\n", + uid_info->uid[type][inst], type, inst); + } + + uid_info->uid[type][inst] = uid; +} + +u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst) +{ + if (!uid_info) + return 0; + + if (type >= AMDGPU_UID_TYPE_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", + type); + return 0; + } + + if (inst >= AMDGPU_UID_INST_MAX) { + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", + inst); + return 0; + } + + return uid_info->uid[type][inst]; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h new file mode 100644 index 000000000000..d92ddcce9f58 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT + * + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_UID_H__ +#define __AMDGPU_UID_H__ + +#include <linux/types.h> + +#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ + +struct amdgpu_device; + +enum amdgpu_uid_type { + AMDGPU_UID_TYPE_XCD, + AMDGPU_UID_TYPE_AID, + AMDGPU_UID_TYPE_SOC, + AMDGPU_UID_TYPE_MID, + AMDGPU_UID_TYPE_MAX +}; + +struct amdgpu_uid { + uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; + struct amdgpu_device *adev; +}; + +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst, + uint64_t uid); +uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, + enum amdgpu_uid_type type, uint8_t inst); +#endif -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid and helpers into separate files 2026-06-22 19:57 ` [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid " Shahyan Soltani @ 2026-06-23 8:55 ` Christian König 2026-06-24 15:04 ` Soltani, Shahyan 0 siblings, 1 reply; 17+ messages in thread From: Christian König @ 2026-06-23 8:55 UTC (permalink / raw) To: Shahyan Soltani, amd-gfx; +Cc: alexander.deucher On 6/22/26 21:57, Shahyan Soltani wrote: > Move struct amdgpu_uid and helpers from the monolithic amdgpu.h file into a new amdgpu_uid.h file. > > Move functions amdgpu_device_set_uid() and amdgpu_device_get_uid() out of > amdgpu_device.c into new dedicated amdgpu_uid.c file. > > Update amdgpu/Makefile to build amdgpu_uid.o > > This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective > separate headers. > > Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> > > --- > This patch and patch 7 can be dropped if moving amdgpu_uid out of > amdgpu.h is not desirable. I think we should really just move the defines in a new file called amdgpu_device.h. The uid is something device specific and it is a bit overkill to have a separate C file for it. Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 22 +------ > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 --------------- > drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c | 75 ++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h | 50 +++++++++++++++ > 5 files changed, 127 insertions(+), 72 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h > > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile > index 10dc7cfd607e..ab5fdbb5e4b4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms > amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o amdgpu_lockdep.o \ > amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \ > amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o \ > - amdgpu_wb.o > + amdgpu_wb.o amdgpu_uid.o > > amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 4ffcc0cc6404..fe951a901d20 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -116,6 +116,7 @@ > #include "amdgpu_wb.h" > #include "amdgpu_ip.h" > #include "amdgpu_sa.h" > +#include "amdgpu_uid.h" > #if defined(CONFIG_DRM_AMD_ISP) > #include "amdgpu_isp.h" > #endif > @@ -551,21 +552,6 @@ struct amdgpu_mmio_remap { > struct amdgpu_bo *bo; > }; > > -enum amdgpu_uid_type { > - AMDGPU_UID_TYPE_XCD, > - AMDGPU_UID_TYPE_AID, > - AMDGPU_UID_TYPE_SOC, > - AMDGPU_UID_TYPE_MID, > - AMDGPU_UID_TYPE_MAX > -}; > - > -#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ > - > -struct amdgpu_uid { > - uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; > - struct amdgpu_device *adev; > -}; > - > #define MAX_UMA_OPTION_NAME 28 > #define MAX_UMA_OPTION_ENTRIES 19 > > @@ -1530,10 +1516,4 @@ static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) > > return 0; > } > - > -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst, > - uint64_t uid); > -uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst); > #endif > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index d6931e1184d0..8d55658ecb31 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -6717,53 +6717,3 @@ ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset) > size += sysfs_emit_at(buf, size, "\n"); > return size; > } > - > -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst, > - uint64_t uid) > -{ > - if (!uid_info) > - return; > - > - if (type >= AMDGPU_UID_TYPE_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > - type); > - return; > - } > - > - if (inst >= AMDGPU_UID_INST_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > - inst); > - return; > - } > - > - if (uid_info->uid[type][inst] != 0) { > - dev_warn_once( > - uid_info->adev->dev, > - "Overwriting existing UID %llu for type %d instance %d\n", > - uid_info->uid[type][inst], type, inst); > - } > - > - uid_info->uid[type][inst] = uid; > -} > - > -u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst) > -{ > - if (!uid_info) > - return 0; > - > - if (type >= AMDGPU_UID_TYPE_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > - type); > - return 0; > - } > - > - if (inst >= AMDGPU_UID_INST_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > - inst); > - return 0; > - } > - > - return uid_info->uid[type][inst]; > -} > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c > new file mode 100644 > index 000000000000..6cf6b3f12271 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c > @@ -0,0 +1,75 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright 2026 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > +#include "amdgpu_uid.h" > +#include <linux/dev_printk.h> > +#include "amdgpu.h" > + > +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst, > + uint64_t uid) > +{ > + if (!uid_info) > + return; > + > + if (type >= AMDGPU_UID_TYPE_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > + type); > + return; > + } > + > + if (inst >= AMDGPU_UID_INST_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > + inst); > + return; > + } > + > + if (uid_info->uid[type][inst] != 0) { > + dev_warn_once( > + uid_info->adev->dev, > + "Overwriting existing UID %llu for type %d instance %d\n", > + uid_info->uid[type][inst], type, inst); > + } > + > + uid_info->uid[type][inst] = uid; > +} > + > +u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst) > +{ > + if (!uid_info) > + return 0; > + > + if (type >= AMDGPU_UID_TYPE_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > + type); > + return 0; > + } > + > + if (inst >= AMDGPU_UID_INST_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > + inst); > + return 0; > + } > + > + return uid_info->uid[type][inst]; > +} > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h > new file mode 100644 > index 000000000000..d92ddcce9f58 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h > @@ -0,0 +1,50 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR MIT > + * > + * Copyright 2026 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > +#ifndef __AMDGPU_UID_H__ > +#define __AMDGPU_UID_H__ > + > +#include <linux/types.h> > + > +#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ > + > +struct amdgpu_device; > + > +enum amdgpu_uid_type { > + AMDGPU_UID_TYPE_XCD, > + AMDGPU_UID_TYPE_AID, > + AMDGPU_UID_TYPE_SOC, > + AMDGPU_UID_TYPE_MID, > + AMDGPU_UID_TYPE_MAX > +}; > + > +struct amdgpu_uid { > + uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; > + struct amdgpu_device *adev; > +}; > + > +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst, > + uint64_t uid); > +uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst); > +#endif ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid and helpers into separate files 2026-06-23 8:55 ` Christian König @ 2026-06-24 15:04 ` Soltani, Shahyan 2026-06-24 15:24 ` Christian König 0 siblings, 1 reply; 17+ messages in thread From: Soltani, Shahyan @ 2026-06-24 15:04 UTC (permalink / raw) To: Koenig, Christian, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander [-- Attachment #1: Type: text/plain, Size: 12204 bytes --] AMD General On 6/23/2026 04:55, Christian Koenig wrote: > I think we should really just move the defines in a new file called amdgpu_device.h. > > The uid is something device specific and it is a bit overkill to have a separate C file for it. Hi Christian, I made a amdgpu_device.h file in v1 of the patch however I was asked by Alex to drop it to keep core structures within amdgpu.h. I'm not entirely sure if it would be better to create amdgpu_device.h file with only the uid struct and helpers or keep it within amdgpu.h (dropping this patch). Any clarification on the this matter will be greatly appreciated. Thanks, Shahyan. ________________________________ From: Koenig, Christian <Christian.Koenig@amd.com> Sent: Tuesday, June 23, 2026 4:55 AM To: Soltani, Shahyan <Shahyan.Soltani@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org> Cc: Deucher, Alexander <Alexander.Deucher@amd.com> Subject: Re: [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid and helpers into separate files On 6/22/26 21:57, Shahyan Soltani wrote: > Move struct amdgpu_uid and helpers from the monolithic amdgpu.h file into a new amdgpu_uid.h file. > > Move functions amdgpu_device_set_uid() and amdgpu_device_get_uid() out of > amdgpu_device.c into new dedicated amdgpu_uid.c file. > > Update amdgpu/Makefile to build amdgpu_uid.o > > This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective > separate headers. > > Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> > > --- > This patch and patch 7 can be dropped if moving amdgpu_uid out of > amdgpu.h is not desirable. I think we should really just move the defines in a new file called amdgpu_device.h. The uid is something device specific and it is a bit overkill to have a separate C file for it. Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 22 +------ > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 --------------- > drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c | 75 ++++++++++++++++++++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h | 50 +++++++++++++++ > 5 files changed, 127 insertions(+), 72 deletions(-) > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c > create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h > > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile > index 10dc7cfd607e..ab5fdbb5e4b4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms > amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o amdgpu_lockdep.o \ > amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \ > amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o \ > - amdgpu_wb.o > + amdgpu_wb.o amdgpu_uid.o > > amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 4ffcc0cc6404..fe951a901d20 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -116,6 +116,7 @@ > #include "amdgpu_wb.h" > #include "amdgpu_ip.h" > #include "amdgpu_sa.h" > +#include "amdgpu_uid.h" > #if defined(CONFIG_DRM_AMD_ISP) > #include "amdgpu_isp.h" > #endif > @@ -551,21 +552,6 @@ struct amdgpu_mmio_remap { > struct amdgpu_bo *bo; > }; > > -enum amdgpu_uid_type { > - AMDGPU_UID_TYPE_XCD, > - AMDGPU_UID_TYPE_AID, > - AMDGPU_UID_TYPE_SOC, > - AMDGPU_UID_TYPE_MID, > - AMDGPU_UID_TYPE_MAX > -}; > - > -#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ > - > -struct amdgpu_uid { > - uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; > - struct amdgpu_device *adev; > -}; > - > #define MAX_UMA_OPTION_NAME 28 > #define MAX_UMA_OPTION_ENTRIES 19 > > @@ -1530,10 +1516,4 @@ static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) > > return 0; > } > - > -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst, > - uint64_t uid); > -uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst); > #endif > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index d6931e1184d0..8d55658ecb31 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -6717,53 +6717,3 @@ ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset) > size += sysfs_emit_at(buf, size, "\n"); > return size; > } > - > -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst, > - uint64_t uid) > -{ > - if (!uid_info) > - return; > - > - if (type >= AMDGPU_UID_TYPE_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > - type); > - return; > - } > - > - if (inst >= AMDGPU_UID_INST_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > - inst); > - return; > - } > - > - if (uid_info->uid[type][inst] != 0) { > - dev_warn_once( > - uid_info->adev->dev, > - "Overwriting existing UID %llu for type %d instance %d\n", > - uid_info->uid[type][inst], type, inst); > - } > - > - uid_info->uid[type][inst] = uid; > -} > - > -u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > - enum amdgpu_uid_type type, uint8_t inst) > -{ > - if (!uid_info) > - return 0; > - > - if (type >= AMDGPU_UID_TYPE_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > - type); > - return 0; > - } > - > - if (inst >= AMDGPU_UID_INST_MAX) { > - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > - inst); > - return 0; > - } > - > - return uid_info->uid[type][inst]; > -} > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c > new file mode 100644 > index 000000000000..6cf6b3f12271 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c > @@ -0,0 +1,75 @@ > +// SPDX-License-Identifier: GPL-2.0 OR MIT > +/* > + * Copyright 2026 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > +#include "amdgpu_uid.h" > +#include <linux/dev_printk.h> > +#include "amdgpu.h" > + > +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst, > + uint64_t uid) > +{ > + if (!uid_info) > + return; > + > + if (type >= AMDGPU_UID_TYPE_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > + type); > + return; > + } > + > + if (inst >= AMDGPU_UID_INST_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > + inst); > + return; > + } > + > + if (uid_info->uid[type][inst] != 0) { > + dev_warn_once( > + uid_info->adev->dev, > + "Overwriting existing UID %llu for type %d instance %d\n", > + uid_info->uid[type][inst], type, inst); > + } > + > + uid_info->uid[type][inst] = uid; > +} > + > +u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst) > +{ > + if (!uid_info) > + return 0; > + > + if (type >= AMDGPU_UID_TYPE_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", > + type); > + return 0; > + } > + > + if (inst >= AMDGPU_UID_INST_MAX) { > + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", > + inst); > + return 0; > + } > + > + return uid_info->uid[type][inst]; > +} > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h > new file mode 100644 > index 000000000000..d92ddcce9f58 > --- /dev/null > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h > @@ -0,0 +1,50 @@ > +/* SPDX-License-Identifier: GPL-2.0 OR MIT > + * > + * Copyright 2026 Advanced Micro Devices, Inc. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > + * copy of this software and associated documentation files (the "Software"), > + * to deal in the Software without restriction, including without limitation > + * the rights to use, copy, modify, merge, publish, distribute, sublicense, > + * and/or sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR > + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, > + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > +#ifndef __AMDGPU_UID_H__ > +#define __AMDGPU_UID_H__ > + > +#include <linux/types.h> > + > +#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ > + > +struct amdgpu_device; > + > +enum amdgpu_uid_type { > + AMDGPU_UID_TYPE_XCD, > + AMDGPU_UID_TYPE_AID, > + AMDGPU_UID_TYPE_SOC, > + AMDGPU_UID_TYPE_MID, > + AMDGPU_UID_TYPE_MAX > +}; > + > +struct amdgpu_uid { > + uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; > + struct amdgpu_device *adev; > +}; > + > +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst, > + uint64_t uid); > +uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, > + enum amdgpu_uid_type type, uint8_t inst); > +#endif [-- Attachment #2: Type: text/html, Size: 23526 bytes --] ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid and helpers into separate files 2026-06-24 15:04 ` Soltani, Shahyan @ 2026-06-24 15:24 ` Christian König 0 siblings, 0 replies; 17+ messages in thread From: Christian König @ 2026-06-24 15:24 UTC (permalink / raw) To: Soltani, Shahyan, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander Hi Shahyan, in this case we need to sync up with Alex on the team meeting tomorrow. It would be greate if you can rebase the patches and just leave out this one my moving it to a separate branch. Please give "git rebase -i" a try, it should make this pretty easy, just make sure that everything still compiles. Thanks, Christian. On 6/24/26 17:04, Soltani, Shahyan wrote: > AMD General > > On 6/23/2026 04:55, Christian Koenig wrote: >> I think we should really just move the defines in a new file called amdgpu_device.h. >> >> The uid is something device specific and it is a bit overkill to have a separate C file for it. > > Hi Christian, > > I made a amdgpu_device.h file in v1 of the patch however I was asked by Alex to drop it > to keep core structures within amdgpu.h. > > I'm not entirely sure if it would be better to create amdgpu_device.h file with only the uid > struct and helpers or keep it within amdgpu.h (dropping this patch). Any clarification on the > this matter will be greatly appreciated. > > Thanks, > Shahyan. > ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ > *From:* Koenig, Christian <Christian.Koenig@amd.com> > *Sent:* Tuesday, June 23, 2026 4:55 AM > *To:* Soltani, Shahyan <Shahyan.Soltani@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org> > *Cc:* Deucher, Alexander <Alexander.Deucher@amd.com> > *Subject:* Re: [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid and helpers into separate files > > On 6/22/26 21:57, Shahyan Soltani wrote: >> Move struct amdgpu_uid and helpers from the monolithic amdgpu.h file into a new amdgpu_uid.h file. >> >> Move functions amdgpu_device_set_uid() and amdgpu_device_get_uid() out of >> amdgpu_device.c into new dedicated amdgpu_uid.c file. >> >> Update amdgpu/Makefile to build amdgpu_uid.o >> >> This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective >> separate headers. >> >> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> >> >> --- >> This patch and patch 7 can be dropped if moving amdgpu_uid out of >> amdgpu.h is not desirable. > > I think we should really just move the defines in a new file called amdgpu_device.h. > > The uid is something device specific and it is a bit overkill to have a separate C file for it. > > Regards, > Christian. > >> --- >> drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 22 +------ >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 --------------- >> drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c | 75 ++++++++++++++++++++++ >> drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h | 50 +++++++++++++++ >> 5 files changed, 127 insertions(+), 72 deletions(-) >> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c >> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile >> index 10dc7cfd607e..ab5fdbb5e4b4 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/Makefile >> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile >> @@ -72,7 +72,7 @@ amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms >> amdgpu_eeprom.o amdgpu_mca.o amdgpu_psp_ta.o amdgpu_lsdma.o amdgpu_lockdep.o \ >> amdgpu_ring_mux.o amdgpu_xcp.o amdgpu_seq64.o amdgpu_aca.o amdgpu_dev_coredump.o \ >> amdgpu_cper.o amdgpu_userq_fence.o amdgpu_eviction_fence.o amdgpu_ip.o \ >> - amdgpu_wb.o >> + amdgpu_wb.o amdgpu_uid.o >> >> amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> index 4ffcc0cc6404..fe951a901d20 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> @@ -116,6 +116,7 @@ >> #include "amdgpu_wb.h" >> #include "amdgpu_ip.h" >> #include "amdgpu_sa.h" >> +#include "amdgpu_uid.h" >> #if defined(CONFIG_DRM_AMD_ISP) >> #include "amdgpu_isp.h" >> #endif >> @@ -551,21 +552,6 @@ struct amdgpu_mmio_remap { >> struct amdgpu_bo *bo; >> }; >> >> -enum amdgpu_uid_type { >> - AMDGPU_UID_TYPE_XCD, >> - AMDGPU_UID_TYPE_AID, >> - AMDGPU_UID_TYPE_SOC, >> - AMDGPU_UID_TYPE_MID, >> - AMDGPU_UID_TYPE_MAX >> -}; >> - >> -#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ >> - >> -struct amdgpu_uid { >> - uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; >> - struct amdgpu_device *adev; >> -}; >> - >> #define MAX_UMA_OPTION_NAME 28 >> #define MAX_UMA_OPTION_ENTRIES 19 >> >> @@ -1530,10 +1516,4 @@ static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) >> >> return 0; >> } >> - >> -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, >> - enum amdgpu_uid_type type, uint8_t inst, >> - uint64_t uid); >> -uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, >> - enum amdgpu_uid_type type, uint8_t inst); >> #endif >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> index d6931e1184d0..8d55658ecb31 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> @@ -6717,53 +6717,3 @@ ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset) >> size += sysfs_emit_at(buf, size, "\n"); >> return size; >> } >> - >> -void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, >> - enum amdgpu_uid_type type, uint8_t inst, >> - uint64_t uid) >> -{ >> - if (!uid_info) >> - return; >> - >> - if (type >= AMDGPU_UID_TYPE_MAX) { >> - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", >> - type); >> - return; >> - } >> - >> - if (inst >= AMDGPU_UID_INST_MAX) { >> - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", >> - inst); >> - return; >> - } >> - >> - if (uid_info->uid[type][inst] != 0) { >> - dev_warn_once( >> - uid_info->adev->dev, >> - "Overwriting existing UID %llu for type %d instance %d\n", >> - uid_info->uid[type][inst], type, inst); >> - } >> - >> - uid_info->uid[type][inst] = uid; >> -} >> - >> -u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, >> - enum amdgpu_uid_type type, uint8_t inst) >> -{ >> - if (!uid_info) >> - return 0; >> - >> - if (type >= AMDGPU_UID_TYPE_MAX) { >> - dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", >> - type); >> - return 0; >> - } >> - >> - if (inst >= AMDGPU_UID_INST_MAX) { >> - dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", >> - inst); >> - return 0; >> - } >> - >> - return uid_info->uid[type][inst]; >> -} >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c >> new file mode 100644 >> index 000000000000..6cf6b3f12271 >> --- /dev/null >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.c >> @@ -0,0 +1,75 @@ >> +// SPDX-License-Identifier: GPL-2.0 OR MIT >> +/* >> + * Copyright 2026 Advanced Micro Devices, Inc. >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining a >> + * copy of this software and associated documentation files (the "Software"), >> + * to deal in the Software without restriction, including without limitation >> + * the rights to use, copy, modify, merge, publish, distribute, sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> +#include "amdgpu_uid.h" >> +#include <linux/dev_printk.h> >> +#include "amdgpu.h" >> + >> +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, >> + enum amdgpu_uid_type type, uint8_t inst, >> + uint64_t uid) >> +{ >> + if (!uid_info) >> + return; >> + >> + if (type >= AMDGPU_UID_TYPE_MAX) { >> + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", >> + type); >> + return; >> + } >> + >> + if (inst >= AMDGPU_UID_INST_MAX) { >> + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", >> + inst); >> + return; >> + } >> + >> + if (uid_info->uid[type][inst] != 0) { >> + dev_warn_once( >> + uid_info->adev->dev, >> + "Overwriting existing UID %llu for type %d instance %d\n", >> + uid_info->uid[type][inst], type, inst); >> + } >> + >> + uid_info->uid[type][inst] = uid; >> +} >> + >> +u64 amdgpu_device_get_uid(struct amdgpu_uid *uid_info, >> + enum amdgpu_uid_type type, uint8_t inst) >> +{ >> + if (!uid_info) >> + return 0; >> + >> + if (type >= AMDGPU_UID_TYPE_MAX) { >> + dev_err_once(uid_info->adev->dev, "Invalid UID type %d\n", >> + type); >> + return 0; >> + } >> + >> + if (inst >= AMDGPU_UID_INST_MAX) { >> + dev_err_once(uid_info->adev->dev, "Invalid UID instance %d\n", >> + inst); >> + return 0; >> + } >> + >> + return uid_info->uid[type][inst]; >> +} >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h >> new file mode 100644 >> index 000000000000..d92ddcce9f58 >> --- /dev/null >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uid.h >> @@ -0,0 +1,50 @@ >> +/* SPDX-License-Identifier: GPL-2.0 OR MIT >> + * >> + * Copyright 2026 Advanced Micro Devices, Inc. >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining a >> + * copy of this software and associated documentation files (the "Software"), >> + * to deal in the Software without restriction, including without limitation >> + * the rights to use, copy, modify, merge, publish, distribute, sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR >> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, >> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> +#ifndef __AMDGPU_UID_H__ >> +#define __AMDGPU_UID_H__ >> + >> +#include <linux/types.h> >> + >> +#define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ >> + >> +struct amdgpu_device; >> + >> +enum amdgpu_uid_type { >> + AMDGPU_UID_TYPE_XCD, >> + AMDGPU_UID_TYPE_AID, >> + AMDGPU_UID_TYPE_SOC, >> + AMDGPU_UID_TYPE_MID, >> + AMDGPU_UID_TYPE_MAX >> +}; >> + >> +struct amdgpu_uid { >> + uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; >> + struct amdgpu_device *adev; >> +}; >> + >> +void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, >> + enum amdgpu_uid_type type, uint8_t inst, >> + uint64_t uid); >> +uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, >> + enum amdgpu_uid_type type, uint8_t inst); >> +#endif > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 3/8] drm/amdgpu: move struct amdgpu_video_codecs and helpers into header file 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 1/8] drm/amdgpu: move struct amdgpu_wb and helpers into separate files Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid " Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd " Shahyan Soltani ` (4 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Move struct amdgpu_video_codec_info, struct amdgpu_video_codecs, and helpers into a new amdgpu_video_codecs.h file. This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 21 +-------- .../gpu/drm/amd/amdgpu/amdgpu_video_codecs.h | 47 +++++++++++++++++++ 2 files changed, 48 insertions(+), 20 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_video_codecs.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index fe951a901d20..61608acc0393 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -117,6 +117,7 @@ #include "amdgpu_ip.h" #include "amdgpu_sa.h" #include "amdgpu_uid.h" +#include "amdgpu_video_codecs.h" #if defined(CONFIG_DRM_AMD_ISP) #include "amdgpu_isp.h" #endif @@ -444,26 +445,6 @@ struct amdgpu_allowed_register_entry { bool grbm_indexed; }; -struct amdgpu_video_codec_info { - u32 codec_type; - u32 max_width; - u32 max_height; - u32 max_pixels_per_frame; - u32 max_level; -}; - -#define codec_info_build(type, width, height, level) \ - .codec_type = type,\ - .max_width = width,\ - .max_height = height,\ - .max_pixels_per_frame = height * width,\ - .max_level = level, - -struct amdgpu_video_codecs { - const u32 codec_count; - const struct amdgpu_video_codec_info *codec_array; -}; - /* * ASIC specific functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_video_codecs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_video_codecs.h new file mode 100644 index 000000000000..3b2a6cb8632d --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_video_codecs.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT + * + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_VIDEO_CODECS_H__ +#define __AMDGPU_VIDEO_CODECS_H__ + +#include <linux/types.h> + +#define codec_info_build(type, width, height, level) \ + .codec_type = type,\ + .max_width = width,\ + .max_height = height,\ + .max_pixels_per_frame = height * width,\ + .max_level = level, + +struct amdgpu_video_codec_info { + u32 codec_type; + u32 max_width; + u32 max_height; + u32 max_pixels_per_frame; + u32 max_level; +}; + +struct amdgpu_video_codecs { + const u32 codec_count; + const struct amdgpu_video_codec_info *codec_array; +}; +#endif -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd and helpers into header file 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani ` (2 preceding siblings ...) 2026-06-22 19:57 ` [PATCH v3 3/8] drm/amdgpu: move struct amdgpu_video_codecs and helpers into header file Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 2026-06-23 9:04 ` Christian König 2026-06-22 19:57 ` [PATCH v3 5/8] drm/amdgpu: move amdgpu_acpi helpers into new header Shahyan Soltani ` (3 subsequent siblings) 7 siblings, 1 reply; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Move struct amdgpu_mqd_prop, struct amdgpu_mqd, and helpers from the monolithic amdgpu.h into existing amdgpu_mes.h file. This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> --- Following v2's feedback struct amdgpu_mqd and helpers were moved into the existing amdgpu_mes.h instead of creating a new amdgpu_mqh.h file --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 48 +------------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 ++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 61608acc0393..ca86cef62f44 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -96,7 +96,6 @@ #include "amdgpu_doorbell.h" #include "amdgpu_amdkfd.h" #include "amdgpu_discovery.h" -#include "amdgpu_mes.h" #include "amdgpu_umc.h" #include "amdgpu_mmhub.h" #include "amdgpu_gfxhub.h" @@ -115,6 +114,7 @@ #include "amdgpu_eviction_fence.h" #include "amdgpu_wb.h" #include "amdgpu_ip.h" +#include "amdgpu_mes.h" #include "amdgpu_sa.h" #include "amdgpu_uid.h" #include "amdgpu_video_codecs.h" @@ -609,44 +609,6 @@ struct amd_powerplay { (rid == 0x01) || \ (rid == 0x10)))) -enum amdgpu_mqd_update_flag { - AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, - AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, - AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ -}; - -struct amdgpu_mqd_prop { - uint64_t mqd_gpu_addr; - uint64_t hqd_base_gpu_addr; - uint64_t rptr_gpu_addr; - uint64_t wptr_gpu_addr; - uint32_t queue_size; - bool use_doorbell; - uint32_t doorbell_index; - uint64_t eop_gpu_addr; - uint32_t hqd_pipe_priority; - uint32_t hqd_queue_priority; - uint32_t mqd_stride_size; - bool allow_tunneling; - bool hqd_active; - uint64_t shadow_addr; - uint64_t gds_bkup_addr; - uint64_t csa_addr; - uint64_t fence_address; - bool tmz_queue; - bool kernel_queue; - uint32_t *cu_mask; - uint32_t cu_mask_count; - uint32_t cu_flags; - bool is_user_cu_masked; -}; - -struct amdgpu_mqd { - unsigned mqd_size; - int (*init_mqd)(struct amdgpu_device *adev, void *mqd, - struct amdgpu_mqd_prop *p); -}; - struct amdgpu_pcie_reset_ctx { bool in_link_reset; bool occurs_dpc; @@ -1034,14 +996,6 @@ struct amdgpu_device { struct amdgpu_kfd_dev kfd; }; -/* - * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) - * as fence address and writes a 32 bit fence value to this address. - * Driver needs to allocate at least 4 DWs extra memory in addition to - * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. - */ -#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) - static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, uint8_t ip, uint8_t inst) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 5255360353f4..7b4cfb5c8f83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -438,6 +438,52 @@ struct amdgpu_mes_funcs { struct mes_inv_tlbs_pasid_input *input); }; +enum amdgpu_mqd_update_flag { + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ +}; + +struct amdgpu_mqd_prop { + uint64_t mqd_gpu_addr; + uint64_t hqd_base_gpu_addr; + uint64_t rptr_gpu_addr; + uint64_t wptr_gpu_addr; + uint32_t queue_size; + bool use_doorbell; + uint32_t doorbell_index; + uint64_t eop_gpu_addr; + uint32_t hqd_pipe_priority; + uint32_t hqd_queue_priority; + uint32_t mqd_stride_size; + bool allow_tunneling; + bool hqd_active; + uint64_t shadow_addr; + uint64_t gds_bkup_addr; + uint64_t csa_addr; + uint64_t fence_address; + bool tmz_queue; + bool kernel_queue; + uint32_t *cu_mask; + uint32_t cu_mask_count; + uint32_t cu_flags; + bool is_user_cu_masked; +}; + +struct amdgpu_mqd { + unsigned mqd_size; + int (*init_mqd)(struct amdgpu_device *adev, void *mqd, + struct amdgpu_mqd_prop *p); +}; + +/* + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) + * as fence address and writes a 32 bit fence value to this address. + * Driver needs to allocate at least 4 DWs extra memory in addition to + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. + */ +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) + #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ (adev)->mes.kiq_hw_init((adev), (xcc_id)) #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd and helpers into header file 2026-06-22 19:57 ` [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd " Shahyan Soltani @ 2026-06-23 9:04 ` Christian König 2026-06-24 12:59 ` Khatri, Sunil 0 siblings, 1 reply; 17+ messages in thread From: Christian König @ 2026-06-23 9:04 UTC (permalink / raw) To: Shahyan Soltani, amd-gfx, Khatri, Sunil; +Cc: alexander.deucher On 6/22/26 21:57, Shahyan Soltani wrote: > Move struct amdgpu_mqd_prop, struct amdgpu_mqd, and helpers from the monolithic amdgpu.h > into existing amdgpu_mes.h file. > > This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective > separate headers. > > Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> @Sunil can you take a look at that as well? Just to keep you updated on all userqueue stuff. Thanks, Christian. > > --- > Following v2's feedback struct amdgpu_mqd and helpers were moved into > the existing amdgpu_mes.h instead of creating a new amdgpu_mqh.h file > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 48 +------------------------ > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 ++++++++++++++++++++++++ > 2 files changed, 47 insertions(+), 47 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 61608acc0393..ca86cef62f44 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -96,7 +96,6 @@ > #include "amdgpu_doorbell.h" > #include "amdgpu_amdkfd.h" > #include "amdgpu_discovery.h" > -#include "amdgpu_mes.h" > #include "amdgpu_umc.h" > #include "amdgpu_mmhub.h" > #include "amdgpu_gfxhub.h" > @@ -115,6 +114,7 @@ > #include "amdgpu_eviction_fence.h" > #include "amdgpu_wb.h" > #include "amdgpu_ip.h" > +#include "amdgpu_mes.h" > #include "amdgpu_sa.h" > #include "amdgpu_uid.h" > #include "amdgpu_video_codecs.h" > @@ -609,44 +609,6 @@ struct amd_powerplay { > (rid == 0x01) || \ > (rid == 0x10)))) > > -enum amdgpu_mqd_update_flag { > - AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, > - AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, > - AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ > -}; > - > -struct amdgpu_mqd_prop { > - uint64_t mqd_gpu_addr; > - uint64_t hqd_base_gpu_addr; > - uint64_t rptr_gpu_addr; > - uint64_t wptr_gpu_addr; > - uint32_t queue_size; > - bool use_doorbell; > - uint32_t doorbell_index; > - uint64_t eop_gpu_addr; > - uint32_t hqd_pipe_priority; > - uint32_t hqd_queue_priority; > - uint32_t mqd_stride_size; > - bool allow_tunneling; > - bool hqd_active; > - uint64_t shadow_addr; > - uint64_t gds_bkup_addr; > - uint64_t csa_addr; > - uint64_t fence_address; > - bool tmz_queue; > - bool kernel_queue; > - uint32_t *cu_mask; > - uint32_t cu_mask_count; > - uint32_t cu_flags; > - bool is_user_cu_masked; > -}; > - > -struct amdgpu_mqd { > - unsigned mqd_size; > - int (*init_mqd)(struct amdgpu_device *adev, void *mqd, > - struct amdgpu_mqd_prop *p); > -}; > - > struct amdgpu_pcie_reset_ctx { > bool in_link_reset; > bool occurs_dpc; > @@ -1034,14 +996,6 @@ struct amdgpu_device { > struct amdgpu_kfd_dev kfd; > }; > > -/* > - * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) > - * as fence address and writes a 32 bit fence value to this address. > - * Driver needs to allocate at least 4 DWs extra memory in addition to > - * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. > - */ > -#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) > - > static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, > uint8_t ip, uint8_t inst) > { > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > index 5255360353f4..7b4cfb5c8f83 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > @@ -438,6 +438,52 @@ struct amdgpu_mes_funcs { > struct mes_inv_tlbs_pasid_input *input); > }; > > +enum amdgpu_mqd_update_flag { > + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, > + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, > + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ > +}; > + > +struct amdgpu_mqd_prop { > + uint64_t mqd_gpu_addr; > + uint64_t hqd_base_gpu_addr; > + uint64_t rptr_gpu_addr; > + uint64_t wptr_gpu_addr; > + uint32_t queue_size; > + bool use_doorbell; > + uint32_t doorbell_index; > + uint64_t eop_gpu_addr; > + uint32_t hqd_pipe_priority; > + uint32_t hqd_queue_priority; > + uint32_t mqd_stride_size; > + bool allow_tunneling; > + bool hqd_active; > + uint64_t shadow_addr; > + uint64_t gds_bkup_addr; > + uint64_t csa_addr; > + uint64_t fence_address; > + bool tmz_queue; > + bool kernel_queue; > + uint32_t *cu_mask; > + uint32_t cu_mask_count; > + uint32_t cu_flags; > + bool is_user_cu_masked; > +}; > + > +struct amdgpu_mqd { > + unsigned mqd_size; > + int (*init_mqd)(struct amdgpu_device *adev, void *mqd, > + struct amdgpu_mqd_prop *p); > +}; > + > +/* > + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) > + * as fence address and writes a 32 bit fence value to this address. > + * Driver needs to allocate at least 4 DWs extra memory in addition to > + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. > + */ > +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) > + > #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ > (adev)->mes.kiq_hw_init((adev), (xcc_id)) > #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd and helpers into header file 2026-06-23 9:04 ` Christian König @ 2026-06-24 12:59 ` Khatri, Sunil 2026-06-24 13:10 ` Khatri, Sunil 0 siblings, 1 reply; 17+ messages in thread From: Khatri, Sunil @ 2026-06-24 12:59 UTC (permalink / raw) To: Christian König, Shahyan Soltani, amd-gfx, Khatri, Sunil Cc: alexander.deucher On 23-06-2026 02:34 pm, Christian König wrote: > On 6/22/26 21:57, Shahyan Soltani wrote: >> Move struct amdgpu_mqd_prop, struct amdgpu_mqd, and helpers from the monolithic amdgpu.h >> into existing amdgpu_mes.h file. >> >> This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective >> separate headers. >> >> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> > Reviewed-by: Christian König <christian.koenig@amd.com> > > @Sunil can you take a look at that as well? Just to keep you updated on all userqueue stuff. LGTM, Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Regards Sunil Khatri > > Thanks, > Christian. > >> --- >> Following v2's feedback struct amdgpu_mqd and helpers were moved into >> the existing amdgpu_mes.h instead of creating a new amdgpu_mqh.h file >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 48 +------------------------ >> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 ++++++++++++++++++++++++ >> 2 files changed, 47 insertions(+), 47 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> index 61608acc0393..ca86cef62f44 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> @@ -96,7 +96,6 @@ >> #include "amdgpu_doorbell.h" >> #include "amdgpu_amdkfd.h" >> #include "amdgpu_discovery.h" >> -#include "amdgpu_mes.h" >> #include "amdgpu_umc.h" >> #include "amdgpu_mmhub.h" >> #include "amdgpu_gfxhub.h" >> @@ -115,6 +114,7 @@ >> #include "amdgpu_eviction_fence.h" >> #include "amdgpu_wb.h" >> #include "amdgpu_ip.h" >> +#include "amdgpu_mes.h" >> #include "amdgpu_sa.h" >> #include "amdgpu_uid.h" >> #include "amdgpu_video_codecs.h" >> @@ -609,44 +609,6 @@ struct amd_powerplay { >> (rid == 0x01) || \ >> (rid == 0x10)))) >> >> -enum amdgpu_mqd_update_flag { >> - AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, >> - AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, >> - AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ >> -}; >> - >> -struct amdgpu_mqd_prop { >> - uint64_t mqd_gpu_addr; >> - uint64_t hqd_base_gpu_addr; >> - uint64_t rptr_gpu_addr; >> - uint64_t wptr_gpu_addr; >> - uint32_t queue_size; >> - bool use_doorbell; >> - uint32_t doorbell_index; >> - uint64_t eop_gpu_addr; >> - uint32_t hqd_pipe_priority; >> - uint32_t hqd_queue_priority; >> - uint32_t mqd_stride_size; >> - bool allow_tunneling; >> - bool hqd_active; >> - uint64_t shadow_addr; >> - uint64_t gds_bkup_addr; >> - uint64_t csa_addr; >> - uint64_t fence_address; >> - bool tmz_queue; >> - bool kernel_queue; >> - uint32_t *cu_mask; >> - uint32_t cu_mask_count; >> - uint32_t cu_flags; >> - bool is_user_cu_masked; >> -}; >> - >> -struct amdgpu_mqd { >> - unsigned mqd_size; >> - int (*init_mqd)(struct amdgpu_device *adev, void *mqd, >> - struct amdgpu_mqd_prop *p); >> -}; >> - >> struct amdgpu_pcie_reset_ctx { >> bool in_link_reset; >> bool occurs_dpc; >> @@ -1034,14 +996,6 @@ struct amdgpu_device { >> struct amdgpu_kfd_dev kfd; >> }; >> >> -/* >> - * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) >> - * as fence address and writes a 32 bit fence value to this address. >> - * Driver needs to allocate at least 4 DWs extra memory in addition to >> - * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. >> - */ >> -#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) >> - >> static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, >> uint8_t ip, uint8_t inst) >> { >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >> index 5255360353f4..7b4cfb5c8f83 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >> @@ -438,6 +438,52 @@ struct amdgpu_mes_funcs { >> struct mes_inv_tlbs_pasid_input *input); >> }; >> >> +enum amdgpu_mqd_update_flag { >> + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, >> + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, >> + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ >> +}; >> + >> +struct amdgpu_mqd_prop { >> + uint64_t mqd_gpu_addr; >> + uint64_t hqd_base_gpu_addr; >> + uint64_t rptr_gpu_addr; >> + uint64_t wptr_gpu_addr; >> + uint32_t queue_size; >> + bool use_doorbell; >> + uint32_t doorbell_index; >> + uint64_t eop_gpu_addr; >> + uint32_t hqd_pipe_priority; >> + uint32_t hqd_queue_priority; >> + uint32_t mqd_stride_size; >> + bool allow_tunneling; >> + bool hqd_active; >> + uint64_t shadow_addr; >> + uint64_t gds_bkup_addr; >> + uint64_t csa_addr; >> + uint64_t fence_address; >> + bool tmz_queue; >> + bool kernel_queue; >> + uint32_t *cu_mask; >> + uint32_t cu_mask_count; >> + uint32_t cu_flags; >> + bool is_user_cu_masked; >> +}; >> + >> +struct amdgpu_mqd { >> + unsigned mqd_size; >> + int (*init_mqd)(struct amdgpu_device *adev, void *mqd, >> + struct amdgpu_mqd_prop *p); >> +}; >> + >> +/* >> + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) >> + * as fence address and writes a 32 bit fence value to this address. >> + * Driver needs to allocate at least 4 DWs extra memory in addition to >> + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. >> + */ >> +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) >> + >> #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ >> (adev)->mes.kiq_hw_init((adev), (xcc_id)) >> #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd and helpers into header file 2026-06-24 12:59 ` Khatri, Sunil @ 2026-06-24 13:10 ` Khatri, Sunil 2026-06-24 17:33 ` Soltani, Shahyan 0 siblings, 1 reply; 17+ messages in thread From: Khatri, Sunil @ 2026-06-24 13:10 UTC (permalink / raw) To: Christian König, Shahyan Soltani, amd-gfx, Khatri, Sunil Cc: alexander.deucher On 24-06-2026 06:29 pm, Khatri, Sunil wrote: > > On 23-06-2026 02:34 pm, Christian König wrote: >> On 6/22/26 21:57, Shahyan Soltani wrote: >>> Move struct amdgpu_mqd_prop, struct amdgpu_mqd, and helpers from the >>> monolithic amdgpu.h >>> into existing amdgpu_mes.h file. >>> >>> This is part of the ongoing effort to reduce the size of amdgpu.h >>> into their own respective >>> separate headers. >>> >>> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> >> Reviewed-by: Christian König <christian.koenig@amd.com> >> >> @Sunil can you take a look at that as well? Just to keep you updated >> on all userqueue stuff. > LGTM, > Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> > > Regards > Sunil Khatri >> >> Thanks, >> Christian. >> >>> --- >>> Following v2's feedback struct amdgpu_mqd and helpers were moved into >>> the existing amdgpu_mes.h instead of creating a new amdgpu_mqh.h file >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 48 >>> +------------------------ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 ++++++++++++++++++++++++ >>> 2 files changed, 47 insertions(+), 47 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> index 61608acc0393..ca86cef62f44 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> @@ -96,7 +96,6 @@ >>> #include "amdgpu_doorbell.h" >>> #include "amdgpu_amdkfd.h" >>> #include "amdgpu_discovery.h" >>> -#include "amdgpu_mes.h" >>> #include "amdgpu_umc.h" >>> #include "amdgpu_mmhub.h" >>> #include "amdgpu_gfxhub.h" >>> @@ -115,6 +114,7 @@ >>> #include "amdgpu_eviction_fence.h" >>> #include "amdgpu_wb.h" >>> #include "amdgpu_ip.h" >>> +#include "amdgpu_mes.h" I remember one thing, if you moved them from amdgpu.h and again added it via include "amdgpu_mes.h", there seems to be less benefit of it as its always there in amdgpu.h. Just check if there is a possibility if that include could be removed totally and include amdgpu_mes.h explicitly only where its needed. Regards Sunil khatri >>> #include "amdgpu_sa.h" >>> #include "amdgpu_uid.h" >>> #include "amdgpu_video_codecs.h" >>> @@ -609,44 +609,6 @@ struct amd_powerplay { >>> (rid == 0x01) || \ >>> (rid == 0x10)))) >>> -enum amdgpu_mqd_update_flag { >>> - AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, >>> - AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, >>> - AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ >>> -}; >>> - >>> -struct amdgpu_mqd_prop { >>> - uint64_t mqd_gpu_addr; >>> - uint64_t hqd_base_gpu_addr; >>> - uint64_t rptr_gpu_addr; >>> - uint64_t wptr_gpu_addr; >>> - uint32_t queue_size; >>> - bool use_doorbell; >>> - uint32_t doorbell_index; >>> - uint64_t eop_gpu_addr; >>> - uint32_t hqd_pipe_priority; >>> - uint32_t hqd_queue_priority; >>> - uint32_t mqd_stride_size; >>> - bool allow_tunneling; >>> - bool hqd_active; >>> - uint64_t shadow_addr; >>> - uint64_t gds_bkup_addr; >>> - uint64_t csa_addr; >>> - uint64_t fence_address; >>> - bool tmz_queue; >>> - bool kernel_queue; >>> - uint32_t *cu_mask; >>> - uint32_t cu_mask_count; >>> - uint32_t cu_flags; >>> - bool is_user_cu_masked; >>> -}; >>> - >>> -struct amdgpu_mqd { >>> - unsigned mqd_size; >>> - int (*init_mqd)(struct amdgpu_device *adev, void *mqd, >>> - struct amdgpu_mqd_prop *p); >>> -}; >>> - >>> struct amdgpu_pcie_reset_ctx { >>> bool in_link_reset; >>> bool occurs_dpc; >>> @@ -1034,14 +996,6 @@ struct amdgpu_device { >>> struct amdgpu_kfd_dev kfd; >>> }; >>> -/* >>> - * MES FW uses address(mqd_addr + sizeof(struct mqd) + >>> 3*sizeof(uint32_t)) >>> - * as fence address and writes a 32 bit fence value to this address. >>> - * Driver needs to allocate at least 4 DWs extra memory in addition to >>> - * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE >>> for safety. >>> - */ >>> -#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) >>> AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) >>> - >>> static inline uint32_t amdgpu_ip_version(const struct >>> amdgpu_device *adev, >>> uint8_t ip, uint8_t inst) >>> { >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> index 5255360353f4..7b4cfb5c8f83 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> @@ -438,6 +438,52 @@ struct amdgpu_mes_funcs { >>> struct mes_inv_tlbs_pasid_input *input); >>> }; >>> +enum amdgpu_mqd_update_flag { >>> + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, >>> + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, >>> + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ >>> +}; >>> + >>> +struct amdgpu_mqd_prop { >>> + uint64_t mqd_gpu_addr; >>> + uint64_t hqd_base_gpu_addr; >>> + uint64_t rptr_gpu_addr; >>> + uint64_t wptr_gpu_addr; >>> + uint32_t queue_size; >>> + bool use_doorbell; >>> + uint32_t doorbell_index; >>> + uint64_t eop_gpu_addr; >>> + uint32_t hqd_pipe_priority; >>> + uint32_t hqd_queue_priority; >>> + uint32_t mqd_stride_size; >>> + bool allow_tunneling; >>> + bool hqd_active; >>> + uint64_t shadow_addr; >>> + uint64_t gds_bkup_addr; >>> + uint64_t csa_addr; >>> + uint64_t fence_address; >>> + bool tmz_queue; >>> + bool kernel_queue; >>> + uint32_t *cu_mask; >>> + uint32_t cu_mask_count; >>> + uint32_t cu_flags; >>> + bool is_user_cu_masked; >>> +}; >>> + >>> +struct amdgpu_mqd { >>> + unsigned mqd_size; >>> + int (*init_mqd)(struct amdgpu_device *adev, void *mqd, >>> + struct amdgpu_mqd_prop *p); >>> +}; >>> + >>> +/* >>> + * MES FW uses address(mqd_addr + sizeof(struct mqd) + >>> 3*sizeof(uint32_t)) >>> + * as fence address and writes a 32 bit fence value to this address. >>> + * Driver needs to allocate at least 4 DWs extra memory in addition to >>> + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE >>> for safety. >>> + */ >>> +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) >>> AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) >>> + >>> #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ >>> (adev)->mes.kiq_hw_init((adev), (xcc_id)) >>> #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd and helpers into header file 2026-06-24 13:10 ` Khatri, Sunil @ 2026-06-24 17:33 ` Soltani, Shahyan 0 siblings, 0 replies; 17+ messages in thread From: Soltani, Shahyan @ 2026-06-24 17:33 UTC (permalink / raw) To: Khatri, Sunil, Koenig, Christian, amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander [-- Attachment #1: Type: text/plain, Size: 7775 bytes --] AMD General > I remember one thing, if you moved them from amdgpu.h and again added it > via include "amdgpu_mes.h", there seems to be less benefit of it as its > always there in amdgpu.h. Just check if there is a possibility if that > include could be removed totally and include amdgpu_mes.h explicitly > only where its needed. > > Regards > Sunil khatri Hi Sunil, I looked into removing amdgpu_mes.h as you asked, however struct amdgpu_device needs these by value: struct amdgpu_mes mes; struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; Because of this amdgpu.h needs the complete definition so as far as I know I'm unable to drop the include here and use something like a forward declaration. Thanks, Shahyan ________________________________ From: Khatri, Sunil <Sunil.Khatri@amd.com> Sent: Wednesday, June 24, 2026 9:10 AM To: Koenig, Christian <Christian.Koenig@amd.com>; Soltani, Shahyan <Shahyan.Soltani@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Khatri, Sunil <Sunil.Khatri@amd.com> Cc: Deucher, Alexander <Alexander.Deucher@amd.com> Subject: Re: [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd and helpers into header file On 24-06-2026 06:29 pm, Khatri, Sunil wrote: > > On 23-06-2026 02:34 pm, Christian König wrote: >> On 6/22/26 21:57, Shahyan Soltani wrote: >>> Move struct amdgpu_mqd_prop, struct amdgpu_mqd, and helpers from the >>> monolithic amdgpu.h >>> into existing amdgpu_mes.h file. >>> >>> This is part of the ongoing effort to reduce the size of amdgpu.h >>> into their own respective >>> separate headers. >>> >>> Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> >> Reviewed-by: Christian König <christian.koenig@amd.com> >> >> @Sunil can you take a look at that as well? Just to keep you updated >> on all userqueue stuff. > LGTM, > Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> > > Regards > Sunil Khatri >> >> Thanks, >> Christian. >> >>> --- >>> Following v2's feedback struct amdgpu_mqd and helpers were moved into >>> the existing amdgpu_mes.h instead of creating a new amdgpu_mqh.h file >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 48 >>> +------------------------ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 46 ++++++++++++++++++++++++ >>> 2 files changed, 47 insertions(+), 47 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> index 61608acc0393..ca86cef62f44 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> @@ -96,7 +96,6 @@ >>> #include "amdgpu_doorbell.h" >>> #include "amdgpu_amdkfd.h" >>> #include "amdgpu_discovery.h" >>> -#include "amdgpu_mes.h" >>> #include "amdgpu_umc.h" >>> #include "amdgpu_mmhub.h" >>> #include "amdgpu_gfxhub.h" >>> @@ -115,6 +114,7 @@ >>> #include "amdgpu_eviction_fence.h" >>> #include "amdgpu_wb.h" >>> #include "amdgpu_ip.h" >>> +#include "amdgpu_mes.h" I remember one thing, if you moved them from amdgpu.h and again added it via include "amdgpu_mes.h", there seems to be less benefit of it as its always there in amdgpu.h. Just check if there is a possibility if that include could be removed totally and include amdgpu_mes.h explicitly only where its needed. Regards Sunil khatri >>> #include "amdgpu_sa.h" >>> #include "amdgpu_uid.h" >>> #include "amdgpu_video_codecs.h" >>> @@ -609,44 +609,6 @@ struct amd_powerplay { >>> (rid == 0x01) || \ >>> (rid == 0x10)))) >>> -enum amdgpu_mqd_update_flag { >>> - AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, >>> - AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, >>> - AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ >>> -}; >>> - >>> -struct amdgpu_mqd_prop { >>> - uint64_t mqd_gpu_addr; >>> - uint64_t hqd_base_gpu_addr; >>> - uint64_t rptr_gpu_addr; >>> - uint64_t wptr_gpu_addr; >>> - uint32_t queue_size; >>> - bool use_doorbell; >>> - uint32_t doorbell_index; >>> - uint64_t eop_gpu_addr; >>> - uint32_t hqd_pipe_priority; >>> - uint32_t hqd_queue_priority; >>> - uint32_t mqd_stride_size; >>> - bool allow_tunneling; >>> - bool hqd_active; >>> - uint64_t shadow_addr; >>> - uint64_t gds_bkup_addr; >>> - uint64_t csa_addr; >>> - uint64_t fence_address; >>> - bool tmz_queue; >>> - bool kernel_queue; >>> - uint32_t *cu_mask; >>> - uint32_t cu_mask_count; >>> - uint32_t cu_flags; >>> - bool is_user_cu_masked; >>> -}; >>> - >>> -struct amdgpu_mqd { >>> - unsigned mqd_size; >>> - int (*init_mqd)(struct amdgpu_device *adev, void *mqd, >>> - struct amdgpu_mqd_prop *p); >>> -}; >>> - >>> struct amdgpu_pcie_reset_ctx { >>> bool in_link_reset; >>> bool occurs_dpc; >>> @@ -1034,14 +996,6 @@ struct amdgpu_device { >>> struct amdgpu_kfd_dev kfd; >>> }; >>> -/* >>> - * MES FW uses address(mqd_addr + sizeof(struct mqd) + >>> 3*sizeof(uint32_t)) >>> - * as fence address and writes a 32 bit fence value to this address. >>> - * Driver needs to allocate at least 4 DWs extra memory in addition to >>> - * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE >>> for safety. >>> - */ >>> -#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) >>> AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) >>> - >>> static inline uint32_t amdgpu_ip_version(const struct >>> amdgpu_device *adev, >>> uint8_t ip, uint8_t inst) >>> { >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> index 5255360353f4..7b4cfb5c8f83 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h >>> @@ -438,6 +438,52 @@ struct amdgpu_mes_funcs { >>> struct mes_inv_tlbs_pasid_input *input); >>> }; >>> +enum amdgpu_mqd_update_flag { >>> + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, >>> + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, >>> + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ >>> +}; >>> + >>> +struct amdgpu_mqd_prop { >>> + uint64_t mqd_gpu_addr; >>> + uint64_t hqd_base_gpu_addr; >>> + uint64_t rptr_gpu_addr; >>> + uint64_t wptr_gpu_addr; >>> + uint32_t queue_size; >>> + bool use_doorbell; >>> + uint32_t doorbell_index; >>> + uint64_t eop_gpu_addr; >>> + uint32_t hqd_pipe_priority; >>> + uint32_t hqd_queue_priority; >>> + uint32_t mqd_stride_size; >>> + bool allow_tunneling; >>> + bool hqd_active; >>> + uint64_t shadow_addr; >>> + uint64_t gds_bkup_addr; >>> + uint64_t csa_addr; >>> + uint64_t fence_address; >>> + bool tmz_queue; >>> + bool kernel_queue; >>> + uint32_t *cu_mask; >>> + uint32_t cu_mask_count; >>> + uint32_t cu_flags; >>> + bool is_user_cu_masked; >>> +}; >>> + >>> +struct amdgpu_mqd { >>> + unsigned mqd_size; >>> + int (*init_mqd)(struct amdgpu_device *adev, void *mqd, >>> + struct amdgpu_mqd_prop *p); >>> +}; >>> + >>> +/* >>> + * MES FW uses address(mqd_addr + sizeof(struct mqd) + >>> 3*sizeof(uint32_t)) >>> + * as fence address and writes a 32 bit fence value to this address. >>> + * Driver needs to allocate at least 4 DWs extra memory in addition to >>> + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE >>> for safety. >>> + */ >>> +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) >>> AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) >>> + >>> #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ >>> (adev)->mes.kiq_hw_init((adev), (xcc_id)) >>> #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ [-- Attachment #2: Type: text/html, Size: 15103 bytes --] ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 5/8] drm/amdgpu: move amdgpu_acpi helpers into new header 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani ` (3 preceding siblings ...) 2026-06-22 19:57 ` [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd " Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 6/8] drm/amdgpu: move amdgpu_allowed_register_entry into amdgpu_reg_access.h Shahyan Soltani ` (2 subsequent siblings) 7 siblings, 0 replies; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Move struct amdgpu_uma_carveout_option, struct amdgpu_uma_carveout_info, struct amdgpu_numa_info, and relevant acpi helpers from the monolithic amdgpu.h header file into a new amdgpu_acpi.h file. This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 122 +----------------- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h | 151 +++++++++++++++++++++++ 2 files changed, 152 insertions(+), 121 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ca86cef62f44..24c6a21efd67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -116,6 +116,7 @@ #include "amdgpu_ip.h" #include "amdgpu_mes.h" #include "amdgpu_sa.h" +#include "amdgpu_acpi.h" #include "amdgpu_uid.h" #include "amdgpu_video_codecs.h" #if defined(CONFIG_DRM_AMD_ISP) @@ -139,13 +140,6 @@ struct amdgpu_mgpu_info { uint32_t num_apu; }; -enum amdgpu_ss { - AMDGPU_SS_DRV_LOAD, - AMDGPU_SS_DEV_D0, - AMDGPU_SS_DEV_D3, - AMDGPU_SS_DRV_UNLOAD -}; - struct amdgpu_hwip_reg_entry { u32 hwip; u32 inst; @@ -533,38 +527,6 @@ struct amdgpu_mmio_remap { struct amdgpu_bo *bo; }; -#define MAX_UMA_OPTION_NAME 28 -#define MAX_UMA_OPTION_ENTRIES 19 - -#define AMDGPU_UMA_FLAG_AUTO BIT(1) -#define AMDGPU_UMA_FLAG_CUSTOM BIT(0) - -/** - * struct amdgpu_uma_carveout_option - single UMA carveout option - * @name: Name of the carveout option - * @memory_carved_mb: Amount of memory carved in MB - * @flags: ATCS flags supported by this option - */ -struct amdgpu_uma_carveout_option { - char name[MAX_UMA_OPTION_NAME]; - uint32_t memory_carved_mb; - uint8_t flags; -}; - -/** - * struct amdgpu_uma_carveout_info - table of available UMA carveout options - * @num_entries: Number of available options - * @uma_option_index: The index of the option currently applied - * @update_lock: Lock to serialize changes to the option - * @entries: The array of carveout options - */ -struct amdgpu_uma_carveout_info { - uint8_t num_entries; - uint8_t uma_option_index; - struct mutex update_lock; - struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; -}; - struct amd_powerplay { void *pp_handle; const struct amd_pm_funcs *pp_funcs; @@ -1312,88 +1274,6 @@ struct amdgpu_afmt_acr { struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); -/* amdgpu_acpi.c */ - -struct amdgpu_numa_info { - uint64_t size; - int pxm; - int nid; -}; - -/* ATCS Device/Driver State */ -#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 -#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 -#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 -#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 - -#if defined(CONFIG_ACPI) -int amdgpu_acpi_init(struct amdgpu_device *adev); -void amdgpu_acpi_fini(struct amdgpu_device *adev); -bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); -bool amdgpu_acpi_is_power_shift_control_supported(void); -bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); -int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, - u8 perf_req, bool advertise); -int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, - u8 dev_state, bool drv_state); -int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, - enum amdgpu_ss ss_state); -int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); -int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); -int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, - u64 *tmr_size); -int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, - struct amdgpu_numa_info *numa_info); - -void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); -bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); -void amdgpu_acpi_detect(void); -void amdgpu_acpi_release(void); -#else -static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } -static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, - u64 *tmr_offset, u64 *tmr_size) -{ - return -EINVAL; -} -static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, - int xcc_id, - struct amdgpu_numa_info *numa_info) -{ - return -EINVAL; -} -static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } -static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } -static inline void amdgpu_acpi_detect(void) { } -static inline void amdgpu_acpi_release(void) { } -static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } -static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } -static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, - u8 dev_state, bool drv_state) { return 0; } -static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, - enum amdgpu_ss ss_state) -{ - return 0; -} -static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) -{ - return -EINVAL; -} -static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } -#endif - -#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) -bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); -bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); -#else -static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } -static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } -#endif - -#if defined(CONFIG_DRM_AMD_ISP) -int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); -#endif - void amdgpu_register_gpu_instance(struct amdgpu_device *adev); void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h new file mode 100644 index 000000000000..6569a4db5dae --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT + * + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_ACPI_H__ +#define __AMDGPU_ACPI_H__ + +#include <linux/types.h> +#include <linux/mutex_types.h> + +struct amdgpu_device; +struct acpi_device; +struct amdgpu_dm_backlight_caps; + +#define MAX_UMA_OPTION_NAME 28 +#define MAX_UMA_OPTION_ENTRIES 19 + +#define AMDGPU_UMA_FLAG_AUTO BIT(1) +#define AMDGPU_UMA_FLAG_CUSTOM BIT(0) + +/* ATCS Device/Driver State */ +#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 +#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 +#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 +#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 + +enum amdgpu_ss { + AMDGPU_SS_DRV_LOAD, + AMDGPU_SS_DEV_D0, + AMDGPU_SS_DEV_D3, + AMDGPU_SS_DRV_UNLOAD +}; + +/** + * struct amdgpu_uma_carveout_option - single UMA carveout option + * @name: Name of the carveout option + * @memory_carved_mb: Amount of memory carved in MB + * @flags: ATCS flags supported by this option + */ +struct amdgpu_uma_carveout_option { + char name[MAX_UMA_OPTION_NAME]; + uint32_t memory_carved_mb; + uint8_t flags; +}; + +/** + * struct amdgpu_uma_carveout_info - table of available UMA carveout options + * @num_entries: Number of available options + * @uma_option_index: The index of the option currently applied + * @update_lock: Lock to serialize changes to the option + * @entries: The array of carveout options + */ +struct amdgpu_uma_carveout_info { + uint8_t num_entries; + uint8_t uma_option_index; + struct mutex update_lock; + struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; +}; + +struct amdgpu_numa_info { + uint64_t size; + int pxm; + int nid; +}; + +#if defined(CONFIG_ACPI) +int amdgpu_acpi_init(struct amdgpu_device *adev); +void amdgpu_acpi_fini(struct amdgpu_device *adev); +bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); +bool amdgpu_acpi_is_power_shift_control_supported(void); +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); +int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, + u8 perf_req, bool advertise); +int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, + u8 dev_state, bool drv_state); +int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, + enum amdgpu_ss ss_state); +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); +int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); +int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, + u64 *tmr_size); +int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_numa_info *numa_info); + +void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); +bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); +void amdgpu_acpi_detect(void); +void amdgpu_acpi_release(void); +#else +static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } +static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, + u64 *tmr_offset, u64 *tmr_size) +{ + return -EINVAL; +} +static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, + int xcc_id, + struct amdgpu_numa_info *numa_info) +{ + return -EINVAL; +} +static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } +static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } +static inline void amdgpu_acpi_detect(void) { } +static inline void amdgpu_acpi_release(void) { } +static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } +static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } +static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, + u8 dev_state, bool drv_state) { return 0; } +static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, + enum amdgpu_ss ss_state) +{ + return 0; +} +static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) +{ + return -EINVAL; +} +static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } +#endif + +#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) +bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); +bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); +#else +static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } +static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } +#endif + +#if defined(CONFIG_DRM_AMD_ISP) +int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); +#endif +#endif /* __AMDGPU_ACPI_H__ */ -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 6/8] drm/amdgpu: move amdgpu_allowed_register_entry into amdgpu_reg_access.h 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani ` (4 preceding siblings ...) 2026-06-22 19:57 ` [PATCH v3 5/8] drm/amdgpu: move amdgpu_acpi helpers into new header Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 7/8] drm/amdgpu: include amdgpu_uid.h only where needed Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 8/8] drm/amdgpu: include amdgpu_video_codecs.h " Shahyan Soltani 7 siblings, 0 replies; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Move struct amdgpu_allowed_register_entry from monolithics amdgpu.h file into existing amdgpu_reg_access.h file. This is part of the ongoing effort to reduce the size of amdgpu.h into their own respective separate headers. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 -------- drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 24c6a21efd67..fff532bdc6ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -431,14 +431,6 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); */ int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); -/* - * ASIC specific register table accessible by UMD - */ -struct amdgpu_allowed_register_entry { - uint32_t reg_offset; - bool grbm_indexed; -}; - /* * ASIC specific functions. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h index a1011af6b52b..320c30ce4a62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -89,6 +89,14 @@ struct amdgpu_reg_access { struct amdgpu_reg_smn_ext smn; }; +/* + * ASIC specific register table accessible by UMD + */ +struct amdgpu_allowed_register_entry { + uint32_t reg_offset; + bool grbm_indexed; +}; + void amdgpu_reg_access_init(struct amdgpu_device *adev); uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 7/8] drm/amdgpu: include amdgpu_uid.h only where needed 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani ` (5 preceding siblings ...) 2026-06-22 19:57 ` [PATCH v3 6/8] drm/amdgpu: move amdgpu_allowed_register_entry into amdgpu_reg_access.h Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 8/8] drm/amdgpu: include amdgpu_video_codecs.h " Shahyan Soltani 7 siblings, 0 replies; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Remove #include "amdgpu_uid.h" from amdgpu.h and add a foward declaration of struct amdgpu_uid. Add #include "amdgpu_uid.h" into files amdgpu_device.c, amdgpu_xcp.c, smu_v13_0_12_ppt.c, smu_v13_0_6_ppt.c, and smu_v15_0_8_ppt.c. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Acked-by: Christian König <christian.koenig@amd.com> --- This patch and patch 2 can be dropped if moving amdgpu_uid out of amdgpu.h is not desirable. --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 1 + drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c | 1 + 6 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index fff532bdc6ac..358508120dfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -117,7 +117,6 @@ #include "amdgpu_mes.h" #include "amdgpu_sa.h" #include "amdgpu_acpi.h" -#include "amdgpu_uid.h" #include "amdgpu_video_codecs.h" #if defined(CONFIG_DRM_AMD_ISP) #include "amdgpu_isp.h" @@ -328,6 +327,7 @@ struct amdgpu_hive_info; struct amdgpu_reset_context; struct amdgpu_reset_control; struct amdgpu_coredump_info; +struct amdgpu_uid; enum amdgpu_cp_irq { AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8d55658ecb31..f6905f9da587 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -78,6 +78,7 @@ #include "amdgpu_reset.h" #include "amdgpu_virt.h" #include "amdgpu_dev_coredump.h" +#include "amdgpu_uid.h" #include <linux/suspend.h> #include <drm/task_barrier.h> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 88e6eab91bc6..0f2e4d2995b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -23,6 +23,7 @@ #include "amdgpu.h" #include "amdgpu_xcp.h" #include "amdgpu_drv.h" +#include "amdgpu_uid.h" #include <drm/drm_drv.h> #include "../amdxcp/amdgpu_xcp_drv.h" diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 12b57a0f4fc4..f61bdc2aed5e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -35,6 +35,7 @@ #include <linux/pci.h> #include "smu_cmn.h" #include "amdgpu_ras.h" +#include "amdgpu_uid.h" #undef MP1_Public #undef smnMP1_FIRMWARE_FLAGS diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index ce520f43ab94..799ef8dbe66c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -50,6 +50,7 @@ #include "mp/mp_13_0_6_offset.h" #include "mp/mp_13_0_6_sh_mask.h" #include "umc_v12_0.h" +#include "amdgpu_uid.h" #undef MP1_Public #undef smnMP1_FIRMWARE_FLAGS diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c index 2105a1d7bb34..c241fe5f2e09 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -36,6 +36,7 @@ #include "mp/mp_15_0_8_sh_mask.h" #include "smu_v15_0.h" #include "amdgpu_fru_eeprom.h" +#include "amdgpu_uid.h" #undef MP1_Public -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 8/8] drm/amdgpu: include amdgpu_video_codecs.h only where needed 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani ` (6 preceding siblings ...) 2026-06-22 19:57 ` [PATCH v3 7/8] drm/amdgpu: include amdgpu_uid.h only where needed Shahyan Soltani @ 2026-06-22 19:57 ` Shahyan Soltani 7 siblings, 0 replies; 17+ messages in thread From: Shahyan Soltani @ 2026-06-22 19:57 UTC (permalink / raw) To: amd-gfx; +Cc: alexander.deucher, christian.koenig Remove #include "amdgpu_video_codecs.h" from amdgpu.h and add forward declaration of struct amdgpu_video_codecs. Add #include "amdgpu_video_codecs.h" into files amdgpu_kms.c, amdgpu_virt.c, cik.c, nv.c, si.c, soc15.c, soc21.c, soc24.c, soc_v1_0.c, and vi.c. Signed-off-by: Shahyan Soltani <shahyan.soltani@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 + drivers/gpu/drm/amd/amdgpu/cik.c | 1 + drivers/gpu/drm/amd/amdgpu/nv.c | 1 + drivers/gpu/drm/amd/amdgpu/si.c | 1 + drivers/gpu/drm/amd/amdgpu/soc15.c | 1 + drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + drivers/gpu/drm/amd/amdgpu/soc24.c | 1 + drivers/gpu/drm/amd/amdgpu/soc_v1_0.c | 1 + drivers/gpu/drm/amd/amdgpu/vi.c | 1 + 11 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 358508120dfd..7e06caeeaa48 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -117,7 +117,6 @@ #include "amdgpu_mes.h" #include "amdgpu_sa.h" #include "amdgpu_acpi.h" -#include "amdgpu_video_codecs.h" #if defined(CONFIG_DRM_AMD_ISP) #include "amdgpu_isp.h" #endif @@ -328,6 +327,7 @@ struct amdgpu_reset_context; struct amdgpu_reset_control; struct amdgpu_coredump_info; struct amdgpu_uid; +struct amdgpu_video_codecs; enum amdgpu_cp_irq { AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index cacdc99b3ad6..6b4de2a6c629 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -46,6 +46,7 @@ #include "amdgpu_reset.h" #include "amd_pcie.h" #include "amdgpu_userq.h" +#include "amdgpu_video_codecs.h" void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 7b0d42510161..c792e3088b76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -34,6 +34,7 @@ #include "amdgpu_ras.h" #include "amdgpu_reset.h" #include "amdgpu_dpm.h" +#include "amdgpu_video_codecs.h" #include "vi.h" #include "soc15.h" #include "nv.h" diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 77e120a72815..e037c08c8547 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -36,6 +36,7 @@ #include "cikd.h" #include "atom.h" #include "amd_pcie.h" +#include "amdgpu_video_codecs.h" #include "cik.h" #include "gmc_v7_0.h" diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 77557ee3ca16..96faaf8c5737 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -36,6 +36,7 @@ #include "amdgpu_psp.h" #include "atom.h" #include "amd_pcie.h" +#include "amdgpu_video_codecs.h" #include "gc/gc_10_1_0_offset.h" #include "gc/gc_10_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index b104469c38ec..6e455ad66d62 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -35,6 +35,7 @@ #include "amdgpu_vce.h" #include "atom.h" #include "amd_pcie.h" +#include "amdgpu_video_codecs.h" #include "si_dpm.h" #include "sid.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index ed3fd58b78d0..3d4573d93742 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -77,6 +77,7 @@ #include "mxgpu_ai.h" #include "amdgpu_ras.h" #include "amdgpu_xgmi.h" +#include "amdgpu_video_codecs.h" #include <uapi/linux/kfd_ioctl.h> #define mmMP0_MISC_CGTT_CTRL0 0x01b9 diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 223702e5c220..685258b29fe9 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -33,6 +33,7 @@ #include "amdgpu_ucode.h" #include "amdgpu_psp.h" #include "amdgpu_smu.h" +#include "amdgpu_video_codecs.h" #include "atom.h" #include "amd_pcie.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index e5e3a460e486..9a658e4837f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -34,6 +34,7 @@ #include "amdgpu_smu.h" #include "atom.h" #include "amd_pcie.h" +#include "amdgpu_video_codecs.h" #include "gc/gc_12_0_0_offset.h" #include "gc/gc_12_0_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c index a9039fb1a77b..43e92e2a85e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -29,6 +29,7 @@ #include "gfxhub_v12_1.h" #include "sdma_v7_1.h" #include "gfx_v12_1.h" +#include "amdgpu_video_codecs.h" #include "gc/gc_12_1_0_offset.h" #include "gc/gc_12_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 5715b6b596af..514715793f78 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -34,6 +34,7 @@ #include "amdgpu_ucode.h" #include "atom.h" #include "amd_pcie.h" +#include "amdgpu_video_codecs.h" #include "gmc/gmc_8_1_d.h" #include "gmc/gmc_8_1_sh_mask.h" -- 2.54.0 ^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2026-06-24 17:33 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-06-22 19:57 [PATCH v3 0/8] refactor monolithic amdgpu.h Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 1/8] drm/amdgpu: move struct amdgpu_wb and helpers into separate files Shahyan Soltani 2026-06-23 8:52 ` Christian König 2026-06-22 19:57 ` [PATCH v3 2/8] drm/amdgpu: move struct amdgpu_uid " Shahyan Soltani 2026-06-23 8:55 ` Christian König 2026-06-24 15:04 ` Soltani, Shahyan 2026-06-24 15:24 ` Christian König 2026-06-22 19:57 ` [PATCH v3 3/8] drm/amdgpu: move struct amdgpu_video_codecs and helpers into header file Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 4/8] drm/amdgpu: move struct amdgpu_mqd " Shahyan Soltani 2026-06-23 9:04 ` Christian König 2026-06-24 12:59 ` Khatri, Sunil 2026-06-24 13:10 ` Khatri, Sunil 2026-06-24 17:33 ` Soltani, Shahyan 2026-06-22 19:57 ` [PATCH v3 5/8] drm/amdgpu: move amdgpu_acpi helpers into new header Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 6/8] drm/amdgpu: move amdgpu_allowed_register_entry into amdgpu_reg_access.h Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 7/8] drm/amdgpu: include amdgpu_uid.h only where needed Shahyan Soltani 2026-06-22 19:57 ` [PATCH v3 8/8] drm/amdgpu: include amdgpu_video_codecs.h " Shahyan Soltani
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