Re: [PATCH 6.12.y] spi: spi-fsl-dspi: Avoid setup_accel logic for DMA transfers

[James Clark <james.clark@linaro.org>]

On 11/08/2026 09:40, Mehmet Fide wrote:
> Some measurements on the hardware, in case they help decide this one.
> 
> I ran the transfers that fail on 6.12 against 6.18.44, which carries
> cac7e5054115, on the same board (Colibri VF50, vf610, DSPI in DMA mode) with
> MOSI and MISO shorted at the connector, using spidev_test:
> 
>    3, 5, 7, 9, 11 and 13 byte transfers: every byte comes back, in order.
>    Even lengths and a single byte: fine as well.
>    SPI_LSB_FIRST at 2, 3, 5, 8 and 13 bytes: bytes come back unchanged.
> 
> Without the commit, the same odd length transfers lose the tail of the buffer,
> because the accel path packs into 16 bit frames and computes the word count as
> len / 2, and SPI_LSB_FIRST comes back byte swapped, because the accel helpers
> byte swap through cpu_to_be16() on top of the hardware LSBFE bit. That is what
> we have been carrying a local equivalent for.
> 
> So the commit is what makes those transfers correct on this hardware, not just
> a saving of pointless repacking.
> 
> Thanks,
> Mehmet

It's possible that this was originally done as a fix but I interpreted 
it as a refactor. As part of upstreaming this I broke down and added 
commit messages to changes from NXPs board support branch. It does make 
sense that this change was added after seeing the bug, rather than just 
a clean up. But it could also be a coincidence.

James