* [PATCH v2 1/4] drm: Add P010, P012, P016 format definitions and fourcc
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
@ 2018-06-12 11:16 ` Juha-Pekka Heikkila
2018-06-26 12:32 ` Maarten Lankhorst
2018-06-12 11:16 ` [PATCH v2 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Juha-Pekka Heikkila @ 2018-06-12 11:16 UTC (permalink / raw)
To: intel-gfx
Add P010 definition, semi-planar yuv format where each component
is 16 bits 10 msb containing color value. First come Y plane [10:6]
followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
Add P012 definition, semi-planar yuv format where each component
is 16 bits 12 msb containing color value. First come Y plane [12:4]
followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
Add P016 definition, semi-planar yuv format where each component
is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
plane [16:16]
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 10 ++++++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 5ca6395..5bb2641 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 64bf67a..16f7dbd 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -142,6 +142,16 @@ extern "C" {
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
+ * 2 plane YCbCr
+ * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
+ * component xxx msb Y [xxx:16-xxx]
+ * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian [xxx:16-xxx:xxx:16-xxx]
+ */
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane, 10 bit per channel */
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane, 12 bit per channel */
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane, 16 bit per channel */
+
+/*
* 3 plane YCbCr
* index 0: Y plane, [7:0] Y
* index 1: Cb plane, [7:0] Cb
--
2.7.4
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^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 1/4] drm: Add P010, P012, P016 format definitions and fourcc
2018-06-12 11:16 ` [PATCH v2 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
@ 2018-06-26 12:32 ` Maarten Lankhorst
0 siblings, 0 replies; 13+ messages in thread
From: Maarten Lankhorst @ 2018-06-26 12:32 UTC (permalink / raw)
To: Juha-Pekka Heikkila, intel-gfx; +Cc: dri-devel@lists.freedesktop.org
Op 12-06-18 om 13:16 schreef Juha-Pekka Heikkila:
> Add P010 definition, semi-planar yuv format where each component
> is 16 bits 10 msb containing color value. First come Y plane [10:6]
> followed by 2x2 subsampled Cr:Cb plane [10:6:10:6]
>
> Add P012 definition, semi-planar yuv format where each component
> is 16 bits 12 msb containing color value. First come Y plane [12:4]
> followed by 2x2 subsampled Cr:Cb plane [12:4:12:4]
>
> Add P016 definition, semi-planar yuv format where each component
> is 16 bits. First come Y plane followed by 2x2 subsampled Cr:Cb
> plane [16:16]
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
> drivers/gpu/drm/drm_fourcc.c | 3 +++
> include/uapi/drm/drm_fourcc.h | 10 ++++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 5ca6395..5bb2641 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -173,6 +173,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
> { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1 },
> { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> + { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
> };
>
> unsigned int i;
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 64bf67a..16f7dbd 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -142,6 +142,16 @@ extern "C" {
> #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
>
> /*
> + * 2 plane YCbCr
> + * index 0 = Y plane, [15:0] Y little endian where Pxxx indicate
> + * component xxx msb Y [xxx:16-xxx]
> + * index 1 = Cr:Cb plane, [31:0] Cr:Cb little endian [xxx:16-xxx:xxx:16-xxx]
> + */
> +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane, 10 bit per channel */
> +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane, 12 bit per channel */
> +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane, 16 bit per channel */
> +
> +/*
> * 3 plane YCbCr
> * index 0: Y plane, [7:0] Y
> * index 1: Cb plane, [7:0] Cb
Looking better. :) Please CC dri-devel next time.
~Maarten
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/4] drm/i915: Add P010, P012, P016 plane control definitions
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
2018-06-12 11:16 ` [PATCH v2 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
@ 2018-06-12 11:16 ` Juha-Pekka Heikkila
2018-06-26 12:33 ` Maarten Lankhorst
2018-06-12 11:16 ` [PATCH v2 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Juha-Pekka Heikkila @ 2018-06-12 11:16 UTC (permalink / raw)
To: intel-gfx
Add needed plane control flag definitions for P010, P012 and
P016 formats.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 987def2..9add270 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6378,8 +6378,11 @@ enum {
#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
#define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
+#define PLANE_CTL_FORMAT_P010 ( 3 << 24)
#define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
+#define PLANE_CTL_FORMAT_P012 ( 5 << 24)
#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
+#define PLANE_CTL_FORMAT_P016 ( 7 << 24)
#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/4] drm/i915: Add P010, P012, P016 plane control definitions
2018-06-12 11:16 ` [PATCH v2 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
@ 2018-06-26 12:33 ` Maarten Lankhorst
0 siblings, 0 replies; 13+ messages in thread
From: Maarten Lankhorst @ 2018-06-26 12:33 UTC (permalink / raw)
To: Juha-Pekka Heikkila, intel-gfx
Op 12-06-18 om 13:16 schreef Juha-Pekka Heikkila:
> Add needed plane control flag definitions for P010, P012 and
> P016 formats.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 987def2..9add270 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6378,8 +6378,11 @@ enum {
> #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
> #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
> #define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
> +#define PLANE_CTL_FORMAT_P010 ( 3 << 24)
> #define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
> +#define PLANE_CTL_FORMAT_P012 ( 5 << 24)
> #define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
> +#define PLANE_CTL_FORMAT_P016 ( 7 << 24)
> #define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
> #define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
> #define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
I think this will break with
commit af7187b784432d62cb2059d65ef91b7e0aa77a4f
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Tue Jun 12 16:56:53 2018 -0700
drm/i915/i915_reg.h: fix the checkpatch SPACE_BEFORE_TAB issues
_______________________________________________
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
2018-06-12 11:16 ` [PATCH v2 1/4] drm: Add P010, P012, P016 format definitions and fourcc Juha-Pekka Heikkila
2018-06-12 11:16 ` [PATCH v2 2/4] drm/i915: Add P010, P012, P016 plane control definitions Juha-Pekka Heikkila
@ 2018-06-12 11:16 ` Juha-Pekka Heikkila
2018-08-21 13:47 ` Sharma, Swati2
2018-06-12 11:16 ` [PATCH v2 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes Juha-Pekka Heikkila
` (4 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Juha-Pekka Heikkila @ 2018-06-12 11:16 UTC (permalink / raw)
To: intel-gfx
Preparations for enabling P010, P012 and P016 formats. These
formats will extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
drivers/gpu/drm/i915/intel_atomic.c | 3 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 19 ++++++-------
drivers/gpu/drm/i915/intel_sprite.c | 21 +++++++++++++-
6 files changed, 72 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 61ddb58..d42624b 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -332,8 +332,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
/* set scaler mode */
if ((INTEL_GEN(dev_priv) >= 9) &&
plane_state && plane_state->base.fb &&
- plane_state->base.fb->format->format ==
- DRM_FORMAT_NV12) {
+ is_planar_yuv_format(plane_state->base.fb->format->format)) {
if (INTEL_GEN(dev_priv) == 9 &&
!IS_GEMINILAKE(dev_priv) &&
!IS_SKYLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index e8bf4cc..5b08d53 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
else
crtc_state->active_planes &= ~BIT(intel_plane->id);
- if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
+ if (state->visible && is_planar_yuv_format(state->fb->format->format))
crtc_state->nv12_planes |= BIT(intel_plane->id);
else
crtc_state->nv12_planes &= ~BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2c16c3a..728684c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
return DRM_FORMAT_RGB565;
case PLANE_CTL_FORMAT_NV12:
return DRM_FORMAT_NV12;
+ case PLANE_CTL_FORMAT_P010:
+ return DRM_FORMAT_P010;
+ case PLANE_CTL_FORMAT_P012:
+ return DRM_FORMAT_P012;
+ case PLANE_CTL_FORMAT_P016:
+ return DRM_FORMAT_P016;
default:
case PLANE_CTL_FORMAT_XRGB_8888:
if (rgb_order) {
@@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (fb->format->format == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fb->format->format)) {
ret = skl_check_nv12_surface(crtc_state, plane_state);
if (ret)
return ret;
@@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
+ case DRM_FORMAT_P010:
+ return PLANE_CTL_FORMAT_P010;
+ case DRM_FORMAT_P012:
+ return PLANE_CTL_FORMAT_P012;
+ case DRM_FORMAT_P016:
+ return PLANE_CTL_FORMAT_P016;
default:
MISSING_CASE(pixel_format);
}
@@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
need_scaling = src_w != dst_w || src_h != dst_h;
if (plane_scaler_check)
- if (pixel_format == DRM_FORMAT_NV12)
- need_scaling = true;
+ need_scaling = is_planar_yuv_format(pixel_format);
if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
need_scaling = true;
@@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
return 0;
}
- if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
+ if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
DRM_DEBUG_KMS("NV12: src dimensions not met\n");
return -EINVAL;
@@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
break;
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13093,7 +13107,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
* or
* cdclk/crtc_clock
*/
- mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+ mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
tmpclk1 = (1 << 16) * mult - 1;
tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
max_scale = min(tmpclk1, tmpclk2);
@@ -13325,6 +13339,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
@@ -14465,6 +14482,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
break;
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
+ mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
+ DRM_DEBUG_KMS("RC not to be enabled with %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
+ DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
+ goto err;
+ }
+ break;
default:
DRM_DEBUG_KMS("unsupported pixel format: %s\n",
drm_get_format_name(mode_cmd->pixel_format, &format_name));
@@ -14477,7 +14511,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
- if (fb->format->format == DRM_FORMAT_NV12 &&
+ if (is_planar_yuv_format(fb->format->format) &&
(fb->width < SKL_MIN_YUV_420_SRC_W ||
fb->height < SKL_MIN_YUV_420_SRC_H ||
(fb->width % 4) != 0 || (fb->height % 4) != 0)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 884010874..84f1431 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2075,6 +2075,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
/* intel_sprite.c */
bool intel_format_is_yuv(u32 format);
+bool is_planar_yuv_format(uint32_t pixelformat);
int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
int usecs);
struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 53aaaa3..97d0243 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3911,7 +3911,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
- if (fourcc == DRM_FORMAT_NV12) {
+ if (is_planar_yuv_format(fourcc)) {
skl_ddb_entry_init_from_hw(dev_priv,
&ddb->plane[pipe][plane_id], val2);
skl_ddb_entry_init_from_hw(dev_priv,
@@ -4119,7 +4119,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
if (intel_plane->id == PLANE_CURSOR)
return 0;
- if (plane == 1 && format != DRM_FORMAT_NV12)
+ if (plane == 1 && !is_planar_yuv_format(format))
return 0;
/*
@@ -4131,7 +4131,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
height = drm_rect_height(&intel_pstate->base.src) >> 16;
/* UV plane does 1/2 pixel sub-sampling */
- if (plane == 1 && format == DRM_FORMAT_NV12) {
+ if (plane == 1 && is_planar_yuv_format(format)) {
width /= 2;
height /= 2;
}
@@ -4198,7 +4198,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
return 0;
/* For packed formats, and uv-plane, return 0 */
- if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
+ if (plane == 1 && !is_planar_yuv_format(fb->format->format))
return 0;
/* For Non Y-tile return 8-blocks */
@@ -4216,7 +4216,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
- /* Halve UV plane width and height for NV12 */
+ /* Halve UV plane width and height for NV12 and other planar yuv */
if (plane == 1) {
src_w /= 2;
src_h /= 2;
@@ -4495,8 +4495,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
return 0;
/* only NV12 format has two planes */
- if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
- DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+ if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
+ DRM_DEBUG_KMS("Non planar format have single plane\n");
return -EINVAL;
}
@@ -4507,7 +4507,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
- wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
+ wp->is_planar = is_planar_yuv_format(fb->format->format);
if (plane->id == PLANE_CURSOR) {
wp->width = intel_pstate->base.crtc_w;
@@ -4782,8 +4782,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
return ret;
}
- if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
- wm->is_planar = true;
+ wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 344c0e7..61b6bd7 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -49,6 +49,22 @@ bool intel_format_is_yuv(u32 format)
case DRM_FORMAT_VYUY:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool is_planar_yuv_format(uint32_t pixelformat)
+{
+ switch (pixelformat) {
+ case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
return true;
default:
return false;
@@ -1041,7 +1057,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
src->y2 = (src_y + src_h) << 16;
if (intel_format_is_yuv(fb->format->format) &&
- fb->format->format != DRM_FORMAT_NV12 &&
+ !is_planar_yuv_format(fb->format->format) &&
(src_x % 2 || src_w % 2)) {
DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
src_x, src_w);
@@ -1421,6 +1437,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_P010:
+ case DRM_FORMAT_P012:
+ case DRM_FORMAT_P016:
if (modifier == I915_FORMAT_MOD_Yf_TILED)
return true;
/* fall through */
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 3/4] drm/i915: preparations for enabling P010, P012, P016 formats
2018-06-12 11:16 ` [PATCH v2 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
@ 2018-08-21 13:47 ` Sharma, Swati2
0 siblings, 0 replies; 13+ messages in thread
From: Sharma, Swati2 @ 2018-08-21 13:47 UTC (permalink / raw)
To: Juha-Pekka Heikkila, intel-gfx
Hi Juha,
Shouldn't the following DRM_DEBUG_KMS
DRM_DEBUG_KMS("NV12: src dimensions not met\n");
be made generalized and not specific to NV12?
On 12-Jun-18 4:46 PM, Juha-Pekka Heikkila wrote:
> Preparations for enabling P010, P012 and P016 formats. These
> formats will extend NV12 for larger bit depths.
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 3 +-
> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 19 ++++++-------
> drivers/gpu/drm/i915/intel_sprite.c | 21 +++++++++++++-
> 6 files changed, 72 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 61ddb58..d42624b 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -332,8 +332,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> /* set scaler mode */
> if ((INTEL_GEN(dev_priv) >= 9) &&
> plane_state && plane_state->base.fb &&
> - plane_state->base.fb->format->format ==
> - DRM_FORMAT_NV12) {
> + is_planar_yuv_format(plane_state->base.fb->format->format)) {
> if (INTEL_GEN(dev_priv) == 9 &&
> !IS_GEMINILAKE(dev_priv) &&
> !IS_SKYLAKE(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index e8bf4cc..5b08d53 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -182,7 +182,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
> else
> crtc_state->active_planes &= ~BIT(intel_plane->id);
>
> - if (state->visible && state->fb->format->format == DRM_FORMAT_NV12)
> + if (state->visible && is_planar_yuv_format(state->fb->format->format))
> crtc_state->nv12_planes |= BIT(intel_plane->id);
> else
> crtc_state->nv12_planes &= ~BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2c16c3a..728684c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2667,6 +2667,12 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> return DRM_FORMAT_RGB565;
> case PLANE_CTL_FORMAT_NV12:
> return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_P010:
> + return DRM_FORMAT_P010;
> + case PLANE_CTL_FORMAT_P012:
> + return DRM_FORMAT_P012;
> + case PLANE_CTL_FORMAT_P016:
> + return DRM_FORMAT_P016;
> default:
> case PLANE_CTL_FORMAT_XRGB_8888:
> if (rgb_order) {
> @@ -3182,7 +3188,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> * Handle the AUX surface first since
> * the main surface setup depends on it.
> */
> - if (fb->format->format == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fb->format->format)) {
> ret = skl_check_nv12_surface(crtc_state, plane_state);
> if (ret)
> return ret;
> @@ -3507,6 +3513,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> + case DRM_FORMAT_P010:
> + return PLANE_CTL_FORMAT_P010;
> + case DRM_FORMAT_P012:
> + return PLANE_CTL_FORMAT_P012;
> + case DRM_FORMAT_P016:
> + return PLANE_CTL_FORMAT_P016;
> default:
> MISSING_CASE(pixel_format);
> }
> @@ -4808,8 +4820,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> need_scaling = src_w != dst_w || src_h != dst_h;
>
> if (plane_scaler_check)
> - if (pixel_format == DRM_FORMAT_NV12)
> - need_scaling = true;
> + need_scaling = is_planar_yuv_format(pixel_format);
>
> if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
> need_scaling = true;
> @@ -4850,7 +4861,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
> return 0;
> }
>
> - if (plane_scaler_check && pixel_format == DRM_FORMAT_NV12 &&
> + if (plane_scaler_check && is_planar_yuv_format(pixel_format) &&
> (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
> DRM_DEBUG_KMS("NV12: src dimensions not met\n");
> return -EINVAL;
> @@ -4955,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> break;
> default:
> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> @@ -13093,7 +13107,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> * or
> * cdclk/crtc_clock
> */
> - mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
> + mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
> tmpclk1 = (1 << 16) * mult - 1;
> tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
> max_scale = min(tmpclk1, tmpclk2);
> @@ -13325,6 +13339,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
> @@ -14465,6 +14482,23 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
> break;
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED_CCS ||
> + mode_cmd->modifier[0] == I915_FORMAT_MOD_Yf_TILED_CCS) {
> + DRM_DEBUG_KMS("RC not to be enabled with %s\n",
> + drm_get_format_name(mode_cmd->pixel_format,
> + &format_name));
> + goto err;
> + }
> + if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) {
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> + drm_get_format_name(mode_cmd->pixel_format,
> + &format_name));
> + goto err;
> + }
> + break;
> default:
> DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> @@ -14477,7 +14511,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>
> drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
>
> - if (fb->format->format == DRM_FORMAT_NV12 &&
> + if (is_planar_yuv_format(fb->format->format) &&
> (fb->width < SKL_MIN_YUV_420_SRC_W ||
> fb->height < SKL_MIN_YUV_420_SRC_H ||
> (fb->width % 4) != 0 || (fb->height % 4) != 0)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 884010874..84f1431 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2075,6 +2075,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
>
> /* intel_sprite.c */
> bool intel_format_is_yuv(u32 format);
> +bool is_planar_yuv_format(uint32_t pixelformat);
> int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
> int usecs);
> struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 53aaaa3..97d0243 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3911,7 +3911,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
> val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
> val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
>
> - if (fourcc == DRM_FORMAT_NV12) {
> + if (is_planar_yuv_format(fourcc)) {
> skl_ddb_entry_init_from_hw(dev_priv,
> &ddb->plane[pipe][plane_id], val2);
> skl_ddb_entry_init_from_hw(dev_priv,
> @@ -4119,7 +4119,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
>
> if (intel_plane->id == PLANE_CURSOR)
> return 0;
> - if (plane == 1 && format != DRM_FORMAT_NV12)
> + if (plane == 1 && !is_planar_yuv_format(format))
> return 0;
>
> /*
> @@ -4131,7 +4131,7 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
> height = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> /* UV plane does 1/2 pixel sub-sampling */
> - if (plane == 1 && format == DRM_FORMAT_NV12) {
> + if (plane == 1 && is_planar_yuv_format(format)) {
> width /= 2;
> height /= 2;
> }
> @@ -4198,7 +4198,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
> return 0;
>
> /* For packed formats, and uv-plane, return 0 */
> - if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
> + if (plane == 1 && !is_planar_yuv_format(fb->format->format))
> return 0;
>
> /* For Non Y-tile return 8-blocks */
> @@ -4216,7 +4216,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
> src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
> src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
>
> - /* Halve UV plane width and height for NV12 */
> + /* Halve UV plane width and height for NV12 and other planar yuv */
> if (plane == 1) {
> src_w /= 2;
> src_h /= 2;
> @@ -4495,8 +4495,8 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> return 0;
>
> /* only NV12 format has two planes */
> - if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
> - DRM_DEBUG_KMS("Non NV12 format have single plane\n");
> + if (plane_id == 1 && !is_planar_yuv_format(fb->format->format)) {
> + DRM_DEBUG_KMS("Non planar format have single plane\n");
> return -EINVAL;
> }
>
> @@ -4507,7 +4507,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
> wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
> wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> - wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
> + wp->is_planar = is_planar_yuv_format(fb->format->format);
>
> if (plane->id == PLANE_CURSOR) {
> wp->width = intel_pstate->base.crtc_w;
> @@ -4782,8 +4782,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
> return ret;
> }
>
> - if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
> - wm->is_planar = true;
> + wm->is_planar = is_planar_yuv_format(intel_pstate->base.fb->format->format);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 344c0e7..61b6bd7 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -49,6 +49,22 @@ bool intel_format_is_yuv(u32 format)
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_YVYU:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +bool is_planar_yuv_format(uint32_t pixelformat)
> +{
> + switch (pixelformat) {
> + case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> return true;
> default:
> return false;
> @@ -1041,7 +1057,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
> src->y2 = (src_y + src_h) << 16;
>
> if (intel_format_is_yuv(fb->format->format) &&
> - fb->format->format != DRM_FORMAT_NV12 &&
> + !is_planar_yuv_format(fb->format->format) &&
> (src_x % 2 || src_w % 2)) {
> DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
> src_x, src_w);
> @@ -1421,6 +1437,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> case DRM_FORMAT_UYVY:
> case DRM_FORMAT_VYUY:
> case DRM_FORMAT_NV12:
> + case DRM_FORMAT_P010:
> + case DRM_FORMAT_P012:
> + case DRM_FORMAT_P016:
> if (modifier == I915_FORMAT_MOD_Yf_TILED)
> return true;
> /* fall through */
--
Thanks and Regards,
Swati
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
` (2 preceding siblings ...)
2018-06-12 11:16 ` [PATCH v2 3/4] drm/i915: preparations for enabling P010, P012, P016 formats Juha-Pekka Heikkila
@ 2018-06-12 11:16 ` Juha-Pekka Heikkila
2018-06-26 14:45 ` Maarten Lankhorst
2018-06-12 11:37 ` ✗ Fi.CI.CHECKPATCH: warning for Enable P010, P012 and P016 formats for GLK/CNL (rev2) Patchwork
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Juha-Pekka Heikkila @ 2018-06-12 11:16 UTC (permalink / raw)
To: intel-gfx
Enabling of P010, P012 and P016 formats. These formats will
extend NV12 for larger bit depths.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
---
drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++++++++++++-
drivers/gpu/drm/i915/intel_sprite.c | 39 +++++++++++++++++++++++++++++++++++-
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 728684c..84bdd39 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static const uint32_t glk_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -13635,7 +13654,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
- if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
+ if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ intel_primary_formats = glk_primary_formats;
+ num_formats = ARRAY_SIZE(glk_primary_formats);
+ } else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
intel_primary_formats = skl_pri_planar_formats;
num_formats = ARRAY_SIZE(skl_pri_planar_formats);
} else {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 61b6bd7..c238017 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1297,6 +1297,22 @@ static uint32_t skl_planar_formats[] = {
DRM_FORMAT_NV12,
};
+static uint32_t glk_planar_formats[] = {
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_P010,
+ DRM_FORMAT_P012,
+ DRM_FORMAT_P016,
+};
+
static const uint64_t skl_plane_format_modifiers_noccs[] = {
I915_FORMAT_MOD_Yf_TILED,
I915_FORMAT_MOD_Y_TILED,
@@ -1542,7 +1558,28 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
}
intel_plane->base.state = &state->base;
- if (INTEL_GEN(dev_priv) >= 9) {
+ if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+ intel_plane->can_scale = true;
+ state->scaler_id = -1;
+
+ intel_plane->update_plane = skl_update_plane;
+ intel_plane->disable_plane = skl_disable_plane;
+ intel_plane->get_hw_state = skl_plane_get_hw_state;
+
+ if (skl_plane_has_planar(dev_priv, pipe,
+ PLANE_SPRITE0 + plane)) {
+ plane_formats = glk_planar_formats;
+ num_plane_formats = ARRAY_SIZE(glk_planar_formats);
+ } else {
+ plane_formats = skl_plane_formats;
+ num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+ }
+
+ if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
+ modifiers = skl_plane_format_modifiers_ccs;
+ else
+ modifiers = skl_plane_format_modifiers_noccs;
+ } else if (INTEL_GEN(dev_priv) >= 9) {
intel_plane->can_scale = true;
state->scaler_id = -1;
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
` (3 preceding siblings ...)
2018-06-12 11:16 ` [PATCH v2 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes Juha-Pekka Heikkila
@ 2018-06-12 11:37 ` Patchwork
2018-06-12 11:39 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-12 11:37 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2)
URL : https://patchwork.freedesktop.org/series/43891/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c556cc92888f drm: Add P010, P012, P016 format definitions and fourcc
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/drm_fourcc.c:176:
+ { .format = DRM_FORMAT_P010, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/drm_fourcc.c:177:
+ { .format = DRM_FORMAT_P012, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/drm_fourcc.c:178:
+ { .format = DRM_FORMAT_P016, .depth = 0, .num_planes = 2, .cpp = { 2, 4, 0 }, .hsub = 2, .vsub = 2 },
-:48: WARNING:LONG_LINE_COMMENT: line over 100 characters
#48: FILE: include/uapi/drm/drm_fourcc.h:150:
+#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane, 10 bit per channel */
-:49: WARNING:LONG_LINE_COMMENT: line over 100 characters
#49: FILE: include/uapi/drm/drm_fourcc.h:151:
+#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane, 12 bit per channel */
-:50: WARNING:LONG_LINE_COMMENT: line over 100 characters
#50: FILE: include/uapi/drm/drm_fourcc.h:152:
+#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane, 16 bit per channel */
total: 0 errors, 6 warnings, 0 checks, 25 lines checked
ffaf900fc205 drm/i915: Add P010, P012, P016 plane control definitions
-:19: ERROR:SPACING: space prohibited after that open parenthesis '('
#19: FILE: drivers/gpu/drm/i915/i915_reg.h:6381:
+#define PLANE_CTL_FORMAT_P010 ( 3 << 24)
-:21: ERROR:SPACING: space prohibited after that open parenthesis '('
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6383:
+#define PLANE_CTL_FORMAT_P012 ( 5 << 24)
-:23: ERROR:SPACING: space prohibited after that open parenthesis '('
#23: FILE: drivers/gpu/drm/i915/i915_reg.h:6385:
+#define PLANE_CTL_FORMAT_P016 ( 7 << 24)
total: 3 errors, 0 warnings, 0 checks, 11 lines checked
13b5a18b2a3f drm/i915: preparations for enabling P010, P012, P016 formats
-:136: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#136: FILE: drivers/gpu/drm/i915/intel_display.c:14492:
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
-:142: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#142: FILE: drivers/gpu/drm/i915/intel_display.c:14498:
+ drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
total: 0 errors, 0 warnings, 2 checks, 236 lines checked
b9090703ea04 drm/i915: enable P010, P012, P016 formats for primary and sprite planes
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* ✗ Fi.CI.SPARSE: warning for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
` (4 preceding siblings ...)
2018-06-12 11:37 ` ✗ Fi.CI.CHECKPATCH: warning for Enable P010, P012 and P016 formats for GLK/CNL (rev2) Patchwork
@ 2018-06-12 11:39 ` Patchwork
2018-06-12 11:53 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-12 14:44 ` ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-12 11:39 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2)
URL : https://patchwork.freedesktop.org/series/43891/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm: Add P010, P012, P016 format definitions and fourcc
Okay!
Commit: drm/i915: Add P010, P012, P016 plane control definitions
Okay!
Commit: drm/i915: preparations for enabling P010, P012, P016 formats
-O:drivers/gpu/drm/i915/intel_display.c:13099:21: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_display.c:13099:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_display.c:13113:21: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_display.c:13113:21: warning: expression using sizeof(void)
Commit: drm/i915: enable P010, P012, P016 formats for primary and sprite planes
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* ✓ Fi.CI.BAT: success for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
` (5 preceding siblings ...)
2018-06-12 11:39 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-06-12 11:53 ` Patchwork
2018-06-12 14:44 ` ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-12 11:53 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2)
URL : https://patchwork.freedesktop.org/series/43891/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4305 -> Patchwork_9274 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/43891/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_9274 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_wait@basic-busy-all:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-j4005: PASS -> FAIL (fdo#100368)
==== Possible fixes ====
igt@debugfs_test@read_all_entries:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
igt@gem_exec_suspend@basic-s3:
fi-skl-gvtdvm: INCOMPLETE (fdo#105600, fdo#104108) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: DMESG-WARN (fdo#106607) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#106607 https://bugs.freedesktop.org/show_bug.cgi?id=106607
== Participating hosts (42 -> 37) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-bxt-dsi fi-bsw-cyan fi-skl-6700hq
== Build changes ==
* Linux: CI_DRM_4305 -> Patchwork_9274
CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9274: b9090703ea04fcf0b22830e7c083f329b194a1ea @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b9090703ea04 drm/i915: enable P010, P012, P016 formats for primary and sprite planes
13b5a18b2a3f drm/i915: preparations for enabling P010, P012, P016 formats
ffaf900fc205 drm/i915: Add P010, P012, P016 plane control definitions
c556cc92888f drm: Add P010, P012, P016 format definitions and fourcc
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9274/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread* ✓ Fi.CI.IGT: success for Enable P010, P012 and P016 formats for GLK/CNL (rev2)
2018-06-12 11:16 [PATCH v2 0/4] Enable P010, P012 and P016 formats for GLK/CNL Juha-Pekka Heikkila
` (6 preceding siblings ...)
2018-06-12 11:53 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-06-12 14:44 ` Patchwork
7 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-06-12 14:44 UTC (permalink / raw)
To: Juha-Pekka Heikkila; +Cc: intel-gfx
== Series Details ==
Series: Enable P010, P012 and P016 formats for GLK/CNL (rev2)
URL : https://patchwork.freedesktop.org/series/43891/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4305_full -> Patchwork_9274_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9274_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9274_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9274_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-blt:
shard-kbl: PASS -> SKIP
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS +2
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: PASS -> SKIP +1
igt@kms_cursor_legacy@cursora-vs-flipa-legacy:
shard-snb: SKIP -> PASS +3
== Known issues ==
Here are the changes found in Patchwork_9274_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_gtt:
shard-apl: PASS -> FAIL (fdo#105347)
igt@drv_selftest@live_hangcheck:
shard-kbl: PASS -> DMESG-FAIL (fdo#106560)
igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#105363)
igt@kms_flip_tiling@flip-to-y-tiled:
shard-glk: PASS -> FAIL (fdo#103822, fdo#104724)
igt@perf@polling:
shard-hsw: PASS -> FAIL (fdo#102252)
==== Possible fixes ====
igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
shard-hsw: FAIL (fdo#103060) -> PASS
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-hsw: FAIL (fdo#102887) -> PASS
igt@kms_flip@2x-flip-vs-fences:
shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS +1
igt@kms_flip@plain-flip-ts-check-interruptible:
shard-hsw: FAIL (fdo#100368) -> PASS
igt@kms_flip_tiling@flip-y-tiled:
shard-glk: FAIL (fdo#103822, fdo#104724) -> PASS
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4305 -> Patchwork_9274
CI_DRM_4305: d5ec1c93d19ce1fa4e23176828f4fb9a592f2609 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9274: b9090703ea04fcf0b22830e7c083f329b194a1ea @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9274/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread