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From: Alejandro Lucero Palau <alucerop@amd.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dan Williams <djbw@kernel.org>, Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Dan Williams <danwilliams@nvidia.com>,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v9 01/11] cxl: Split decoder programming into a reusable helper
Date: Wed, 15 Jul 2026 14:49:45 +0100	[thread overview]
Message-ID: <f2f1dcaa-5656-4fd8-ba92-8a0e94659f5d@amd.com> (raw)
In-Reply-To: <20260709010304.680422-2-smadhavan@nvidia.com>


On 7/9/26 02:02, Srirangan Madhavan wrote:
> Move common HDM decoder settings to include/cxl/cxl.h and route the
> register programming sequence through cxl_commit(). This lets reset code
> restore cached HDM state without depending on private cxl_core types while
> keeping hdm.c in charge of the existing commit policy checks.
>
> Build the low-level HDM helper under CONFIG_CXL_HDM so it is available even
> when cxl_core is modular.
>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
>   drivers/cxl/Kconfig          |   4 ++
>   drivers/cxl/core/Makefile    |   1 +
>   drivers/cxl/core/hdm.c       | 122 ++++-------------------------------
>   drivers/cxl/core/region.c    |   6 +-
>   drivers/cxl/core/reset.c     | 118 +++++++++++++++++++++++++++++++++
>   drivers/cxl/cxl.h            |  43 ------------
>   include/cxl/cxl.h            |  55 +++++++++++++++-
>   tools/testing/cxl/test/cxl.c |  10 +--
>   8 files changed, 197 insertions(+), 162 deletions(-)
>   create mode 100644 drivers/cxl/core/reset.c


<snip>


>   /*
>    * Track whether this decoder is free for userspace provisioning, reserved for
>    * region autodiscovery, whether it is started connecting (awaiting other
> @@ -322,7 +281,6 @@ enum cxl_decoder_state {
>    * struct cxl_endpoint_decoder - Endpoint  / SPA to DPA decoder
>    * @cxld: base cxl_decoder_object
>    * @dpa_res: actively claimed DPA span of this decoder
> - * @skip: offset into @dpa_res where @cxld.hpa_range maps
>    * @state: autodiscovery state
>    * @part: partition index this decoder maps
>    * @pos: interleave position in @cxld.region
> @@ -330,7 +288,6 @@ enum cxl_decoder_state {
>   struct cxl_endpoint_decoder {
>   	struct cxl_decoder cxld;
>   	struct resource *dpa_res;
> -	resource_size_t skip;


I understand this change moving skip to the cxl_decoder struct, but I do 
not undertand why dpa_res is not moved as well since skip refers to an 
offset inside dpa_res. Doesn't it?


If I am right this assumes only one decoder and mapping all the DPA. Is 
this the intention?



  parent reply	other threads:[~2026-07-15 13:50 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-09  1:02 [PATCH v9 00/11] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-07-09  1:02 ` [PATCH v9 01/11] cxl: Split decoder programming into a reusable helper Srirangan Madhavan
2026-07-09  1:14   ` sashiko-bot
2026-07-15 13:49   ` Alejandro Lucero Palau [this message]
2026-07-09  1:02 ` [PATCH v9 02/11] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-07-09  1:16   ` sashiko-bot
2026-07-09  1:02 ` [PATCH v9 03/11] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-07-09  1:18   ` sashiko-bot
2026-07-09  1:02 ` [PATCH v9 04/11] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-07-09  1:17   ` sashiko-bot
2026-07-09  3:30   ` Alison Schofield
2026-07-10  0:48   ` Dan Williams (nvidia)
2026-07-09  1:02 ` [PATCH v9 05/11] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-07-09  1:15   ` sashiko-bot
2026-07-09  1:02 ` [PATCH v9 06/11] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-07-09  1:28   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 07/11] PCI/CXL: Discover the CXL reset scope Srirangan Madhavan
2026-07-09  1:24   ` sashiko-bot
2026-07-10  1:00   ` Dan Williams (nvidia)
2026-07-09  1:03 ` [PATCH v9 08/11] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-07-09  1:17   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 09/11] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-07-09  1:27   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 10/11] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-07-09  1:05   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 11/11] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-07-09  1:20   ` sashiko-bot
2026-07-15 15:14 ` [PATCH v9 00/11] PCI/CXL: Add CXL reset support for Type 2 devices Alejandro Lucero Palau

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