All of lore.kernel.org
 help / color / mirror / Atom feed
From: mdalam@codeaurora.org
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: mani@kernel.org, linux-mtd@lists.infradead.org,
	linux-kernel@vger.kernel.org, sricharan@codeaurora.org
Subject: Re: [PATCH V3] mtd: rawnand: qcom: avoid writing to obsolete register
Date: Tue, 08 Jun 2021 12:20:40 +0530	[thread overview]
Message-ID: <f30e4b983e92dd474a208039bcfdf0ad@codeaurora.org> (raw)
In-Reply-To: <20210607115041.21e21e19@xps13>

On 2021-06-07 15:20, Miquel Raynal wrote:
> Hello,
> 
> Md Sadre Alam <mdalam@codeaurora.org> wrote on Mon,  7 Jun 2021
> 15:13:37 +0530:
> 
>> QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
>> Avoid writing this register if QPIC version is V2.0 or newer.
>> 
>> Also fixed nandc undeclared issue reported by,
>> 
>> Reported-by: kernel test robot <lkp@intel.com>
> 
> This tag should only be added when you fix something that is already in
> mainline. The Reported-by here points to v2, which makes no sense.
> Please drop it.

  updated this V4 patch.
> 
>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> ---
>> [V3]
>>  * Fixed nandc undeclared issue.
>>  drivers/mtd/nand/raw/qcom_nandc.c | 18 ++++++++++++------
>>  1 file changed, 12 insertions(+), 6 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c 
>> b/drivers/mtd/nand/raw/qcom_nandc.c
>> index a64fb6c..ee5985d 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -734,6 +734,7 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read, i
>>  {
>>  	struct nand_chip *chip = &host->chip;
>>  	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
>> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> 
>>  	if (read) {
>>  		if (host->use_ecc)
>> @@ -762,7 +763,8 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read, i
>>  	nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
>>  	nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
>>  	nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
>> -	nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> +	if (!nandc->props->qpic_v2)
>> +		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>>  	nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
>>  	nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
>>  	nandc_set_reg(chip, NAND_EXEC_CMD, 1);
>> @@ -1133,7 +1135,8 @@ static void config_nand_page_read(struct 
>> nand_chip *chip)
>> 
>>  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>>  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> +	if (!nandc->props->qpic_v2)
>> +		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>>  	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>>  	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>>  		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> @@ -1191,8 +1194,9 @@ static void config_nand_page_write(struct 
>> nand_chip *chip)
>> 
>>  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>>  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> -		      NAND_BAM_NEXT_SGL);
>> +	if (!nandc->props->qpic_v2)
>> +		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> +			      NAND_BAM_NEXT_SGL);
>>  }
>> 
>>  /*
>> @@ -1248,7 +1252,8 @@ static int nandc_param(struct qcom_nand_host 
>> *host)
>>  					| 2 << WR_RD_BSY_GAP
>>  					| 0 << WIDE_FLASH
>>  					| 1 << DEV0_CFG1_ECC_DISABLE);
>> -	nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << 
>> ECC_CFG_ECC_DISABLE);
>> +	if (!nandc->props->qpic_v2)
>> +		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << 
>> ECC_CFG_ECC_DISABLE);
>> 
>>  	/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
>>  	if (!nandc->props->qpic_v2) {
>> @@ -2689,7 +2694,8 @@ static int qcom_nand_attach_chip(struct 
>> nand_chip *chip)
>>  				| ecc_mode << ECC_MODE
>>  				| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>> 
>> -	host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> +	if (!nandc->props->qpic_v2)
>> +		host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> 
>>  	host->clrflashstatus = FS_READY_BSY_N;
>>  	host->clrreadstatus = 0xc0;
> 
> 
> Thanks,
> Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: mdalam@codeaurora.org
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: mani@kernel.org, linux-mtd@lists.infradead.org,
	linux-kernel@vger.kernel.org, sricharan@codeaurora.org
Subject: Re: [PATCH V3] mtd: rawnand: qcom: avoid writing to obsolete register
Date: Tue, 08 Jun 2021 12:20:40 +0530	[thread overview]
Message-ID: <f30e4b983e92dd474a208039bcfdf0ad@codeaurora.org> (raw)
In-Reply-To: <20210607115041.21e21e19@xps13>

On 2021-06-07 15:20, Miquel Raynal wrote:
> Hello,
> 
> Md Sadre Alam <mdalam@codeaurora.org> wrote on Mon,  7 Jun 2021
> 15:13:37 +0530:
> 
>> QPIC_EBI2_ECC_BUF_CFG register got obsolete from QPIC V2.0 onwards.
>> Avoid writing this register if QPIC version is V2.0 or newer.
>> 
>> Also fixed nandc undeclared issue reported by,
>> 
>> Reported-by: kernel test robot <lkp@intel.com>
> 
> This tag should only be added when you fix something that is already in
> mainline. The Reported-by here points to v2, which makes no sense.
> Please drop it.

  updated this V4 patch.
> 
>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> ---
>> [V3]
>>  * Fixed nandc undeclared issue.
>>  drivers/mtd/nand/raw/qcom_nandc.c | 18 ++++++++++++------
>>  1 file changed, 12 insertions(+), 6 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c 
>> b/drivers/mtd/nand/raw/qcom_nandc.c
>> index a64fb6c..ee5985d 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -734,6 +734,7 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read, i
>>  {
>>  	struct nand_chip *chip = &host->chip;
>>  	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
>> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> 
>>  	if (read) {
>>  		if (host->use_ecc)
>> @@ -762,7 +763,8 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read, i
>>  	nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0);
>>  	nandc_set_reg(chip, NAND_DEV0_CFG1, cfg1);
>>  	nandc_set_reg(chip, NAND_DEV0_ECC_CFG, ecc_bch_cfg);
>> -	nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>> +	if (!nandc->props->qpic_v2)
>> +		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, host->ecc_buf_cfg);
>>  	nandc_set_reg(chip, NAND_FLASH_STATUS, host->clrflashstatus);
>>  	nandc_set_reg(chip, NAND_READ_STATUS, host->clrreadstatus);
>>  	nandc_set_reg(chip, NAND_EXEC_CMD, 1);
>> @@ -1133,7 +1135,8 @@ static void config_nand_page_read(struct 
>> nand_chip *chip)
>> 
>>  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>>  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> +	if (!nandc->props->qpic_v2)
>> +		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>>  	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0);
>>  	write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1,
>>  		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>> @@ -1191,8 +1194,9 @@ static void config_nand_page_write(struct 
>> nand_chip *chip)
>> 
>>  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>>  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>> -	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> -		      NAND_BAM_NEXT_SGL);
>> +	if (!nandc->props->qpic_v2)
>> +		write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1,
>> +			      NAND_BAM_NEXT_SGL);
>>  }
>> 
>>  /*
>> @@ -1248,7 +1252,8 @@ static int nandc_param(struct qcom_nand_host 
>> *host)
>>  					| 2 << WR_RD_BSY_GAP
>>  					| 0 << WIDE_FLASH
>>  					| 1 << DEV0_CFG1_ECC_DISABLE);
>> -	nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << 
>> ECC_CFG_ECC_DISABLE);
>> +	if (!nandc->props->qpic_v2)
>> +		nandc_set_reg(chip, NAND_EBI2_ECC_BUF_CFG, 1 << 
>> ECC_CFG_ECC_DISABLE);
>> 
>>  	/* configure CMD1 and VLD for ONFI param probing in QPIC v1 */
>>  	if (!nandc->props->qpic_v2) {
>> @@ -2689,7 +2694,8 @@ static int qcom_nand_attach_chip(struct 
>> nand_chip *chip)
>>  				| ecc_mode << ECC_MODE
>>  				| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_BCH;
>> 
>> -	host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> +	if (!nandc->props->qpic_v2)
>> +		host->ecc_buf_cfg = 0x203 << NUM_STEPS;
>> 
>>  	host->clrflashstatus = FS_READY_BSY_N;
>>  	host->clrreadstatus = 0xc0;
> 
> 
> Thanks,
> Miquèl

  reply	other threads:[~2021-06-08  6:52 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-07  9:43 [PATCH V3] mtd: rawnand: qcom: avoid writing to obsolete register Md Sadre Alam
2021-06-07  9:43 ` Md Sadre Alam
2021-06-07  9:50 ` Miquel Raynal
2021-06-07  9:50   ` Miquel Raynal
2021-06-08  6:50   ` mdalam [this message]
2021-06-08  6:50     ` mdalam

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f30e4b983e92dd474a208039bcfdf0ad@codeaurora.org \
    --to=mdalam@codeaurora.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=mani@kernel.org \
    --cc=miquel.raynal@bootlin.com \
    --cc=sricharan@codeaurora.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.