From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: Re: [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2]
Date: Fri, 14 Feb 2020 19:29:47 +0100 [thread overview]
Message-ID: <f511ebeb-228f-0e77-38be-32c19862569c@redhat.com> (raw)
In-Reply-To: <20200214181547.21408-2-richard.henderson@linaro.org>
On 2/14/20 7:15 PM, Richard Henderson wrote:
> These registers are 32-bits wide. Cut and paste used FIELD_EX64
> instead of the more proper FIELD_EX32. In practice all this did
> was use an unnecessary 64-bit operation, producing correct results.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/cpu.h | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index e943ffe8a9..28cb2be6fc 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -3415,18 +3415,18 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
> static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
> {
> /* Return true if D16-D31 are implemented */
> - return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2;
> + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
> }
>
> static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
> + return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
> }
>
> static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
> {
> /* Return true if CPU supports double precision floating point */
> - return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
> + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
> }
>
> /*
> @@ -3436,32 +3436,32 @@ static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
> */
> static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
> + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
> }
>
> static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
> + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
> }
>
> static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
> + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
> }
>
> static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
> + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
> }
>
> static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
> + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
> }
>
> static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
> {
> - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
> + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
> }
>
> static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
next prev parent reply other threads:[~2020-02-14 18:30 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 18:15 [PATCH 00/19] target/arm: vfp feature and decodetree cleanup Richard Henderson
2020-02-14 18:15 ` [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2] Richard Henderson
2020-02-14 18:29 ` Philippe Mathieu-Daudé [this message]
2020-02-14 18:35 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32 Richard Henderson
2020-02-14 18:50 ` Philippe Mathieu-Daudé
2020-02-21 15:58 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places Richard Henderson
2020-02-21 16:02 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus Richard Henderson
2020-02-21 16:02 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 05/19] target/arm: Add isar_feature_aa32_simd_r16 Richard Henderson
2020-02-21 16:01 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2 Richard Henderson
2020-02-14 18:51 ` Philippe Mathieu-Daudé
2020-02-14 18:15 ` [PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Richard Henderson
2020-02-21 16:03 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 08/19] target/arm: Perform fpdp_v2 check first Richard Henderson
2020-02-21 16:04 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 09/19] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Richard Henderson
2020-02-21 16:05 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 10/19] target/arm: Add missing checks for fpsp_v2 Richard Henderson
2020-02-21 16:05 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 11/19] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Richard Henderson
2020-02-20 16:37 ` Peter Maydell
2020-02-20 16:41 ` Peter Maydell
2020-02-20 17:55 ` Richard Henderson
2020-02-14 18:15 ` [PATCH 12/19] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Richard Henderson
2020-02-20 17:19 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 13/19] target/arm: Move VLLDM and VLSTM to vfp.decode Richard Henderson
2020-02-20 17:02 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 14/19] target/arm: Move the vfp decodetree calls next to the base isa Richard Henderson
2020-02-20 17:16 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 15/19] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Richard Henderson
2020-02-20 17:32 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 16/19] target/arm: Remove ARM_FEATURE_VFP* Richard Henderson
2020-02-20 17:33 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 17/19] target/arm: Add formats for some vfp 2 and 3-register insns Richard Henderson
2020-02-20 17:40 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 18/19] target/arm: Split VFM decode Richard Henderson
2020-02-20 17:45 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 19/19] target/arm: Split VMINMAXNM decode Richard Henderson
2020-02-20 17:49 ` Peter Maydell
2020-02-14 20:11 ` [PATCH 00/19] target/arm: vfp feature and decodetree cleanup no-reply
2020-02-20 17:52 ` Peter Maydell
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