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From: Shameerali Kolothum Thodi via <qemu-arm@nongnu.org>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"eric.auger@redhat.com" <eric.auger@redhat.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"jgg@nvidia.com" <jgg@nvidia.com>,
	"ddutile@redhat.com" <ddutile@redhat.com>,
	"berrange@redhat.com" <berrange@redhat.com>,
	"imammedo@redhat.com" <imammedo@redhat.com>,
	"nathanc@nvidia.com" <nathanc@nvidia.com>,
	"mochs@nvidia.com" <mochs@nvidia.com>,
	"smostafa@google.com" <smostafa@google.com>,
	"gustavo.romero@linaro.org" <gustavo.romero@linaro.org>,
	"mst@redhat.com" <mst@redhat.com>,
	"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
	Linuxarm <linuxarm@huawei.com>,
	"Wangzhou (B)" <wangzhou1@hisilicon.com>,
	jiangkunkun <jiangkunkun@huawei.com>,
	Jonathan Cameron <jonathan.cameron@huawei.com>,
	"zhangfei.gao@linaro.org" <zhangfei.gao@linaro.org>
Subject: RE: [PATCH v8 08/12] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
Date: Fri, 18 Jul 2025 08:01:22 +0000	[thread overview]
Message-ID: <f793c36c2cf145b7842eb72795553824@huawei.com> (raw)
In-Reply-To: <aHnJ+qUsVyu+eFaT@Asurada-Nvidia>



> -----Original Message-----
> From: Nicolin Chen <nicolinc@nvidia.com>
> Sent: Friday, July 18, 2025 5:14 AM
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org;
> eric.auger@redhat.com; peter.maydell@linaro.org; jgg@nvidia.com;
> ddutile@redhat.com; berrange@redhat.com; imammedo@redhat.com;
> nathanc@nvidia.com; mochs@nvidia.com; smostafa@google.com;
> gustavo.romero@linaro.org; mst@redhat.com;
> marcel.apfelbaum@gmail.com; Linuxarm <linuxarm@huawei.com>;
> Wangzhou (B) <wangzhou1@hisilicon.com>; jiangkunkun
> <jiangkunkun@huawei.com>; Jonathan Cameron
> <jonathan.cameron@huawei.com>; zhangfei.gao@linaro.org
> Subject: Re: [PATCH v8 08/12] hw/arm/virt: Allow user-creatable SMMUv3
> dev instantiation
> 
> Hi Shameer,
> 
> On Fri, Jul 11, 2025 at 09:47:45AM +0100, Shameer Kolothum wrote:
> > +static void create_smmuv3_dev_dtb(VirtMachineState *vms,
> > +                                  DeviceState *dev, PCIBus *bus)
> > +{
> > +    PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms-
> >platform_bus_dev);
> > +    SysBusDevice *sbdev = SYS_BUS_DEVICE(dev);
> > +    int irq = platform_bus_get_irqn(pbus, sbdev, 0);
> > +    hwaddr base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
> > +    MachineState *ms = MACHINE(vms);
> > +
> > +    if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms))
> &&
> > +        strcmp("pcie.0", bus->qbus.name)) {
> > +        warn_report("SMMUv3 device only supported with pcie.0 for DT");
> > +        return;
> > +    }
> > +    base += vms->memmap[VIRT_PLATFORM_BUS].base;
> > +    irq += vms->irqmap[VIRT_PLATFORM_BUS];
> 
> The code is fine.
> 
> Just a related question here:
> 
> Do you know where we define the number of IRQs and the range of
> MMIO for the SysBusDevice?
> 
> SMMU has four IRQs. And I see multiple vSMMU instances do have
> correct intervals to their IRQ numbers, but I cannot find where
> the magic is done.

Look for,
#define PLATFORM_BUS_NUM_IRQS 64

So in theory we could have around 16 vSMMU per VM. It depends on
other platform devices specified as well. Do you see a need for more
on a per VM basis? I know there are host systems with large number of
SMMUv3s, but how many a VM will get assigned realistically?

Thanks,
Shameer






WARNING: multiple messages have this Message-ID (diff)
From: Shameerali Kolothum Thodi via <qemu-devel@nongnu.org>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	"eric.auger@redhat.com" <eric.auger@redhat.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"jgg@nvidia.com" <jgg@nvidia.com>,
	"ddutile@redhat.com" <ddutile@redhat.com>,
	"berrange@redhat.com" <berrange@redhat.com>,
	"imammedo@redhat.com" <imammedo@redhat.com>,
	"nathanc@nvidia.com" <nathanc@nvidia.com>,
	"mochs@nvidia.com" <mochs@nvidia.com>,
	"smostafa@google.com" <smostafa@google.com>,
	"gustavo.romero@linaro.org" <gustavo.romero@linaro.org>,
	"mst@redhat.com" <mst@redhat.com>,
	"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
	Linuxarm <linuxarm@huawei.com>,
	"Wangzhou (B)" <wangzhou1@hisilicon.com>,
	jiangkunkun <jiangkunkun@huawei.com>,
	Jonathan Cameron <jonathan.cameron@huawei.com>,
	"zhangfei.gao@linaro.org" <zhangfei.gao@linaro.org>
Subject: RE: [PATCH v8 08/12] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation
Date: Fri, 18 Jul 2025 08:01:22 +0000	[thread overview]
Message-ID: <f793c36c2cf145b7842eb72795553824@huawei.com> (raw)
In-Reply-To: <aHnJ+qUsVyu+eFaT@Asurada-Nvidia>



> -----Original Message-----
> From: Nicolin Chen <nicolinc@nvidia.com>
> Sent: Friday, July 18, 2025 5:14 AM
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> Cc: qemu-arm@nongnu.org; qemu-devel@nongnu.org;
> eric.auger@redhat.com; peter.maydell@linaro.org; jgg@nvidia.com;
> ddutile@redhat.com; berrange@redhat.com; imammedo@redhat.com;
> nathanc@nvidia.com; mochs@nvidia.com; smostafa@google.com;
> gustavo.romero@linaro.org; mst@redhat.com;
> marcel.apfelbaum@gmail.com; Linuxarm <linuxarm@huawei.com>;
> Wangzhou (B) <wangzhou1@hisilicon.com>; jiangkunkun
> <jiangkunkun@huawei.com>; Jonathan Cameron
> <jonathan.cameron@huawei.com>; zhangfei.gao@linaro.org
> Subject: Re: [PATCH v8 08/12] hw/arm/virt: Allow user-creatable SMMUv3
> dev instantiation
> 
> Hi Shameer,
> 
> On Fri, Jul 11, 2025 at 09:47:45AM +0100, Shameer Kolothum wrote:
> > +static void create_smmuv3_dev_dtb(VirtMachineState *vms,
> > +                                  DeviceState *dev, PCIBus *bus)
> > +{
> > +    PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms-
> >platform_bus_dev);
> > +    SysBusDevice *sbdev = SYS_BUS_DEVICE(dev);
> > +    int irq = platform_bus_get_irqn(pbus, sbdev, 0);
> > +    hwaddr base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
> > +    MachineState *ms = MACHINE(vms);
> > +
> > +    if (!(vms->bootinfo.firmware_loaded && virt_is_acpi_enabled(vms))
> &&
> > +        strcmp("pcie.0", bus->qbus.name)) {
> > +        warn_report("SMMUv3 device only supported with pcie.0 for DT");
> > +        return;
> > +    }
> > +    base += vms->memmap[VIRT_PLATFORM_BUS].base;
> > +    irq += vms->irqmap[VIRT_PLATFORM_BUS];
> 
> The code is fine.
> 
> Just a related question here:
> 
> Do you know where we define the number of IRQs and the range of
> MMIO for the SysBusDevice?
> 
> SMMU has four IRQs. And I see multiple vSMMU instances do have
> correct intervals to their IRQ numbers, but I cannot find where
> the magic is done.

Look for,
#define PLATFORM_BUS_NUM_IRQS 64

So in theory we could have around 16 vSMMU per VM. It depends on
other platform devices specified as well. Do you see a need for more
on a per VM basis? I know there are host systems with large number of
SMMUv3s, but how many a VM will get assigned realistically?

Thanks,
Shameer






  reply	other threads:[~2025-07-18  8:02 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-11  8:47 [PATCH v8 00/12] hw/arm/virt: Add support for user creatable SMMUv3 device Shameer Kolothum via
2025-07-11  8:47 ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 01/12] hw/arm/virt-acpi-build: Don't create ITS id mappings by default Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 02/12] hw/arm/smmu-common: Check SMMU has PCIe Root Complex association Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 03/12] hw/arm/virt-acpi-build: Re-arrange SMMUv3 IORT build Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 04/12] hw/arm/virt-acpi-build: Update IORT for multiple smmuv3 devices Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 05/12] hw/arm/virt: Factor out common SMMUV3 dt bindings code Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 06/12] hw/arm/virt: Add an SMMU_IO_LEN macro Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 07/12] hw/pci: Introduce pci_setup_iommu_per_bus() for per-bus IOMMU ops retrieval Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 08/12] hw/arm/virt: Allow user-creatable SMMUv3 dev instantiation Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-18  4:13   ` Nicolin Chen
2025-07-18  8:01     ` Shameerali Kolothum Thodi via [this message]
2025-07-18  8:01       ` Shameerali Kolothum Thodi via
2025-07-18  8:12       ` Nicolin Chen
2025-07-18  8:22         ` Shameerali Kolothum Thodi via
2025-07-18  8:22           ` Shameerali Kolothum Thodi via
2025-07-18  8:28           ` Nicolin Chen
2025-07-11  8:47 ` [PATCH v8 09/12] qemu-options.hx: Document the arm-smmuv3 device Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 10/12] bios-tables-test: Allow for smmuv3 test data Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 11/12] qtest/bios-tables-test: Add tests for legacy smmuv3 and smmuv3 device Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-11  8:47 ` [PATCH v8 12/12] qtest/bios-tables-test: Update tables for smmuv3 tests Shameer Kolothum via
2025-07-11  8:47   ` Shameer Kolothum via
2025-07-18  4:00 ` [PATCH v8 00/12] hw/arm/virt: Add support for user creatable SMMUv3 device Nicolin Chen

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