Re: [PATCH 2/2] target/riscv: Update MISA.X for non-standard extensions

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

On 11/14/25 6:01 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
> 
> MISA.X is set if there are any non-standard extensions.
> We should set MISA.X when any of the vendor extensions is enabled.
> 
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.h         |  1 +
>   target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
>   2 files changed, 16 insertions(+)
> 
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 8899bf7667a..2e0c92fe593 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -69,6 +69,7 @@ typedef struct CPUArchState CPURISCVState;
>   #define RVH RV('H')
>   #define RVG RV('G')
>   #define RVB RV('B')
> +#define RVX RV('X')
>   
>   extern const uint32_t misa_bits[];
>   const char *riscv_get_misa_ext_name(uint32_t bit);
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index da09a2417cc..0d730f4d774 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1180,6 +1180,20 @@ static void riscv_cpu_update_misa_c(RISCVCPU *cpu)
>       }
>   }
>   
> +/* MISA.X is set when any of the non-standard extensions is enabled. */
> +static void riscv_cpu_update_misa_x(RISCVCPU *cpu)
> +{
> +    CPURISCVState *env = &cpu->env;
> +    const RISCVCPUMultiExtConfig *arr = riscv_cpu_vendor_exts;
> +
> +    for (int i = 0; arr[i].name != NULL; i++) {
> +        if (isa_ext_is_enabled(cpu, arr[i].offset)) {
> +            riscv_cpu_set_misa_ext(env, env->misa_ext | RVX);
> +            break;
> +        }
> +    }
> +}
> +
>   void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
>   {
>       CPURISCVState *env = &cpu->env;
> @@ -1188,6 +1202,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
>       riscv_cpu_init_implied_exts_rules();
>       riscv_cpu_enable_implied_rules(cpu);
>       riscv_cpu_update_misa_c(cpu);
> +    riscv_cpu_update_misa_x(cpu);
>   
>       riscv_cpu_validate_misa_priv(env, &local_err);
>       if (local_err != NULL) {