From: Chris Wilson <chris@chris-wilson.co.uk>
To: Jesse Barnes <jbarnes@virtuousgeek.org>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: set cache sharing policy to max sharing on SNB+
Date: Sat, 02 Jul 2011 08:20:39 +0100 [thread overview]
Message-ID: <f80fcd$o97mr@fmsmga001.fm.intel.com> (raw)
In-Reply-To: <1309563307-5480-1-git-send-email-jbarnes@virtuousgeek.org>
On Fri, 1 Jul 2011 16:35:07 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> By default, the GPU will only share a very small portion of the CPU
> cache. With this change, both the GPU and CPU will have full access to
> the cache, which should help (sometimes a lot) in most cases.
What's the trade off? Is the GPU data in the cache treated differently
than CPU data when it comes to cache eviction and so this asymmetrically
hurts CPU bound applications? At the least it will force more CPU data out
of the cache, which will be enough to make some people scream and howl.
Do we want to expose this as a parameter whilst we test various
configurations? Is this just yet a another step on the path to a
coordinated cpu-gpu governor?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2011-07-02 7:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-01 23:35 [PATCH] drm/i915: set cache sharing policy to max sharing on SNB+ Jesse Barnes
2011-07-02 7:20 ` Chris Wilson [this message]
2011-07-02 10:47 ` Chris Wilson
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