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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Rob Clark <robdclark@gmail.com>, dri-devel@lists.freedesktop.org
Cc: "Rob Clark" <robdclark@chromium.org>,
	"Pekka Paalanen" <pekka.paalanen@collabora.com>,
	"Christian König" <ckoenig.leichtzumerken@gmail.com>,
	intel-gfx@lists.freedesktop.org,
	"open list" <linux-kernel@vger.kernel.org>,
	"Christian König" <christian.koenig@amd.com>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	"Luben Tuikov" <luben.tuikov@amd.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Gustavo Padovan" <gustavo@padovan.org>,
	"Matt Turner" <mattst88@gmail.com>,
	freedreno@lists.freedesktop.org,
	"Sumit Semwal" <sumit.semwal@linaro.org>,
	"open list:SYNC FILE FRAMEWORK" <linux-media@vger.kernel.org>
Subject: Re: [Intel-gfx] [PATCH v10 07/15] dma-buf/sw_sync: Add fence deadline support
Date: Tue, 28 Mar 2023 14:57:33 +0100	[thread overview]
Message-ID: <f973f656-acdf-320f-95d5-3f79cc3ce95a@linux.intel.com> (raw)
In-Reply-To: <20230308155322.344664-8-robdclark@gmail.com>


On 08/03/2023 15:52, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> This consists of simply storing the most recent deadline, and adding an
> ioctl to retrieve the deadline.  This can be used in conjunction with
> the SET_DEADLINE ioctl on a fence fd for testing.  Ie. create various
> sw_sync fences, merge them into a fence-array, set deadline on the
> fence-array and confirm that it is propagated properly to each fence.
> 
> v2: Switch UABI to express deadline as u64
> v3: More verbose UAPI docs, show how to convert from timespec
> v4: Better comments, track the soonest deadline, as a normal fence
>      implementation would, return an error if no deadline set.
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> Reviewed-by: Christian König <christian.koenig@amd.com>
> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
> ---
>   drivers/dma-buf/sw_sync.c    | 81 ++++++++++++++++++++++++++++++++++++
>   drivers/dma-buf/sync_debug.h |  2 +
>   2 files changed, 83 insertions(+)
> 
> diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
> index 348b3a9170fa..f53071bca3af 100644
> --- a/drivers/dma-buf/sw_sync.c
> +++ b/drivers/dma-buf/sw_sync.c
> @@ -52,12 +52,33 @@ struct sw_sync_create_fence_data {
>   	__s32	fence; /* fd of new fence */
>   };
>   
> +/**
> + * struct sw_sync_get_deadline - get the deadline hint of a sw_sync fence
> + * @deadline_ns: absolute time of the deadline
> + * @pad:	must be zero
> + * @fence_fd:	the sw_sync fence fd (in)
> + *
> + * Return the earliest deadline set on the fence.  The timebase for the
> + * deadline is CLOCK_MONOTONIC (same as vblank).  If there is no deadline

Mentioning vblank reads odd since this is drivers/dma-buf/. Dunno.

> + * set on the fence, this ioctl will return -ENOENT.
> + */
> +struct sw_sync_get_deadline {
> +	__u64	deadline_ns;
> +	__u32	pad;
> +	__s32	fence_fd;
> +};
> +
>   #define SW_SYNC_IOC_MAGIC	'W'
>   
>   #define SW_SYNC_IOC_CREATE_FENCE	_IOWR(SW_SYNC_IOC_MAGIC, 0,\
>   		struct sw_sync_create_fence_data)
>   
>   #define SW_SYNC_IOC_INC			_IOW(SW_SYNC_IOC_MAGIC, 1, __u32)
> +#define SW_SYNC_GET_DEADLINE		_IOWR(SW_SYNC_IOC_MAGIC, 2, \
> +		struct sw_sync_get_deadline)
> +
> +
> +#define SW_SYNC_HAS_DEADLINE_BIT	DMA_FENCE_FLAG_USER_BITS
>   
>   static const struct dma_fence_ops timeline_fence_ops;
>   
> @@ -171,6 +192,22 @@ static void timeline_fence_timeline_value_str(struct dma_fence *fence,
>   	snprintf(str, size, "%d", parent->value);
>   }
>   
> +static void timeline_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
> +{
> +	struct sync_pt *pt = dma_fence_to_sync_pt(fence);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(fence->lock, flags);
> +	if (test_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags)) {
> +		if (ktime_before(deadline, pt->deadline))
> +			pt->deadline = deadline;
> +	} else {
> +		pt->deadline = deadline;
> +		set_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags);

FWIW could use __set_bit to avoid needless atomic under spinlock.

> +	}
> +	spin_unlock_irqrestore(fence->lock, flags);
> +}
> +
>   static const struct dma_fence_ops timeline_fence_ops = {
>   	.get_driver_name = timeline_fence_get_driver_name,
>   	.get_timeline_name = timeline_fence_get_timeline_name,
> @@ -179,6 +216,7 @@ static const struct dma_fence_ops timeline_fence_ops = {
>   	.release = timeline_fence_release,
>   	.fence_value_str = timeline_fence_value_str,
>   	.timeline_value_str = timeline_fence_timeline_value_str,
> +	.set_deadline = timeline_fence_set_deadline,
>   };
>   
>   /**
> @@ -387,6 +425,46 @@ static long sw_sync_ioctl_inc(struct sync_timeline *obj, unsigned long arg)
>   	return 0;
>   }
>   
> +static int sw_sync_ioctl_get_deadline(struct sync_timeline *obj, unsigned long arg)
> +{
> +	struct sw_sync_get_deadline data;
> +	struct dma_fence *fence;
> +	struct sync_pt *pt;
> +	int ret = 0;
> +
> +	if (copy_from_user(&data, (void __user *)arg, sizeof(data)))
> +		return -EFAULT;
> +
> +	if (data.deadline_ns || data.pad)
> +		return -EINVAL;
> +
> +	fence = sync_file_get_fence(data.fence_fd);
> +	if (!fence)
> +		return -EINVAL;
> +
> +	pt = dma_fence_to_sync_pt(fence);
> +	if (!pt)
> +		return -EINVAL;
> +
> +	spin_lock(fence->lock);

This may need to be _irq.

> +	if (test_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags)) {
> +		data.deadline_ns = ktime_to_ns(pt->deadline);
> +	} else {
> +		ret = -ENOENT;
> +	}
> +	spin_unlock(fence->lock);
> +
> +	dma_fence_put(fence);
> +
> +	if (ret)
> +		return ret;
> +
> +	if (copy_to_user((void __user *)arg, &data, sizeof(data)))
> +		return -EFAULT;
> +
> +	return 0;
> +}
> +
>   static long sw_sync_ioctl(struct file *file, unsigned int cmd,
>   			  unsigned long arg)
>   {
> @@ -399,6 +477,9 @@ static long sw_sync_ioctl(struct file *file, unsigned int cmd,
>   	case SW_SYNC_IOC_INC:
>   		return sw_sync_ioctl_inc(obj, arg);
>   
> +	case SW_SYNC_GET_DEADLINE:
> +		return sw_sync_ioctl_get_deadline(obj, arg);
> +
>   	default:
>   		return -ENOTTY;
>   	}
> diff --git a/drivers/dma-buf/sync_debug.h b/drivers/dma-buf/sync_debug.h
> index 6176e52ba2d7..a1bdd62efccd 100644
> --- a/drivers/dma-buf/sync_debug.h
> +++ b/drivers/dma-buf/sync_debug.h
> @@ -55,11 +55,13 @@ static inline struct sync_timeline *dma_fence_parent(struct dma_fence *fence)
>    * @base: base fence object
>    * @link: link on the sync timeline's list
>    * @node: node in the sync timeline's tree
> + * @deadline: the earliest fence deadline hint
>    */
>   struct sync_pt {
>   	struct dma_fence base;
>   	struct list_head link;
>   	struct rb_node node;
> +	ktime_t deadline;
>   };
>   
>   extern const struct file_operations sw_sync_debugfs_fops;

Regards,

Tvrtko

WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Rob Clark <robdclark@gmail.com>, dri-devel@lists.freedesktop.org
Cc: "Rob Clark" <robdclark@chromium.org>,
	"Pekka Paalanen" <pekka.paalanen@collabora.com>,
	"Christian König" <ckoenig.leichtzumerken@gmail.com>,
	intel-gfx@lists.freedesktop.org,
	"open list" <linux-kernel@vger.kernel.org>,
	"Christian König" <christian.koenig@amd.com>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	"Luben Tuikov" <luben.tuikov@amd.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Gustavo Padovan" <gustavo@padovan.org>,
	"Matt Turner" <mattst88@gmail.com>,
	freedreno@lists.freedesktop.org,
	"Sumit Semwal" <sumit.semwal@linaro.org>,
	"open list:SYNC FILE FRAMEWORK" <linux-media@vger.kernel.org>
Subject: Re: [PATCH v10 07/15] dma-buf/sw_sync: Add fence deadline support
Date: Tue, 28 Mar 2023 14:57:33 +0100	[thread overview]
Message-ID: <f973f656-acdf-320f-95d5-3f79cc3ce95a@linux.intel.com> (raw)
In-Reply-To: <20230308155322.344664-8-robdclark@gmail.com>


On 08/03/2023 15:52, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> This consists of simply storing the most recent deadline, and adding an
> ioctl to retrieve the deadline.  This can be used in conjunction with
> the SET_DEADLINE ioctl on a fence fd for testing.  Ie. create various
> sw_sync fences, merge them into a fence-array, set deadline on the
> fence-array and confirm that it is propagated properly to each fence.
> 
> v2: Switch UABI to express deadline as u64
> v3: More verbose UAPI docs, show how to convert from timespec
> v4: Better comments, track the soonest deadline, as a normal fence
>      implementation would, return an error if no deadline set.
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> Reviewed-by: Christian König <christian.koenig@amd.com>
> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
> ---
>   drivers/dma-buf/sw_sync.c    | 81 ++++++++++++++++++++++++++++++++++++
>   drivers/dma-buf/sync_debug.h |  2 +
>   2 files changed, 83 insertions(+)
> 
> diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
> index 348b3a9170fa..f53071bca3af 100644
> --- a/drivers/dma-buf/sw_sync.c
> +++ b/drivers/dma-buf/sw_sync.c
> @@ -52,12 +52,33 @@ struct sw_sync_create_fence_data {
>   	__s32	fence; /* fd of new fence */
>   };
>   
> +/**
> + * struct sw_sync_get_deadline - get the deadline hint of a sw_sync fence
> + * @deadline_ns: absolute time of the deadline
> + * @pad:	must be zero
> + * @fence_fd:	the sw_sync fence fd (in)
> + *
> + * Return the earliest deadline set on the fence.  The timebase for the
> + * deadline is CLOCK_MONOTONIC (same as vblank).  If there is no deadline

Mentioning vblank reads odd since this is drivers/dma-buf/. Dunno.

> + * set on the fence, this ioctl will return -ENOENT.
> + */
> +struct sw_sync_get_deadline {
> +	__u64	deadline_ns;
> +	__u32	pad;
> +	__s32	fence_fd;
> +};
> +
>   #define SW_SYNC_IOC_MAGIC	'W'
>   
>   #define SW_SYNC_IOC_CREATE_FENCE	_IOWR(SW_SYNC_IOC_MAGIC, 0,\
>   		struct sw_sync_create_fence_data)
>   
>   #define SW_SYNC_IOC_INC			_IOW(SW_SYNC_IOC_MAGIC, 1, __u32)
> +#define SW_SYNC_GET_DEADLINE		_IOWR(SW_SYNC_IOC_MAGIC, 2, \
> +		struct sw_sync_get_deadline)
> +
> +
> +#define SW_SYNC_HAS_DEADLINE_BIT	DMA_FENCE_FLAG_USER_BITS
>   
>   static const struct dma_fence_ops timeline_fence_ops;
>   
> @@ -171,6 +192,22 @@ static void timeline_fence_timeline_value_str(struct dma_fence *fence,
>   	snprintf(str, size, "%d", parent->value);
>   }
>   
> +static void timeline_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
> +{
> +	struct sync_pt *pt = dma_fence_to_sync_pt(fence);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(fence->lock, flags);
> +	if (test_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags)) {
> +		if (ktime_before(deadline, pt->deadline))
> +			pt->deadline = deadline;
> +	} else {
> +		pt->deadline = deadline;
> +		set_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags);

FWIW could use __set_bit to avoid needless atomic under spinlock.

> +	}
> +	spin_unlock_irqrestore(fence->lock, flags);
> +}
> +
>   static const struct dma_fence_ops timeline_fence_ops = {
>   	.get_driver_name = timeline_fence_get_driver_name,
>   	.get_timeline_name = timeline_fence_get_timeline_name,
> @@ -179,6 +216,7 @@ static const struct dma_fence_ops timeline_fence_ops = {
>   	.release = timeline_fence_release,
>   	.fence_value_str = timeline_fence_value_str,
>   	.timeline_value_str = timeline_fence_timeline_value_str,
> +	.set_deadline = timeline_fence_set_deadline,
>   };
>   
>   /**
> @@ -387,6 +425,46 @@ static long sw_sync_ioctl_inc(struct sync_timeline *obj, unsigned long arg)
>   	return 0;
>   }
>   
> +static int sw_sync_ioctl_get_deadline(struct sync_timeline *obj, unsigned long arg)
> +{
> +	struct sw_sync_get_deadline data;
> +	struct dma_fence *fence;
> +	struct sync_pt *pt;
> +	int ret = 0;
> +
> +	if (copy_from_user(&data, (void __user *)arg, sizeof(data)))
> +		return -EFAULT;
> +
> +	if (data.deadline_ns || data.pad)
> +		return -EINVAL;
> +
> +	fence = sync_file_get_fence(data.fence_fd);
> +	if (!fence)
> +		return -EINVAL;
> +
> +	pt = dma_fence_to_sync_pt(fence);
> +	if (!pt)
> +		return -EINVAL;
> +
> +	spin_lock(fence->lock);

This may need to be _irq.

> +	if (test_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags)) {
> +		data.deadline_ns = ktime_to_ns(pt->deadline);
> +	} else {
> +		ret = -ENOENT;
> +	}
> +	spin_unlock(fence->lock);
> +
> +	dma_fence_put(fence);
> +
> +	if (ret)
> +		return ret;
> +
> +	if (copy_to_user((void __user *)arg, &data, sizeof(data)))
> +		return -EFAULT;
> +
> +	return 0;
> +}
> +
>   static long sw_sync_ioctl(struct file *file, unsigned int cmd,
>   			  unsigned long arg)
>   {
> @@ -399,6 +477,9 @@ static long sw_sync_ioctl(struct file *file, unsigned int cmd,
>   	case SW_SYNC_IOC_INC:
>   		return sw_sync_ioctl_inc(obj, arg);
>   
> +	case SW_SYNC_GET_DEADLINE:
> +		return sw_sync_ioctl_get_deadline(obj, arg);
> +
>   	default:
>   		return -ENOTTY;
>   	}
> diff --git a/drivers/dma-buf/sync_debug.h b/drivers/dma-buf/sync_debug.h
> index 6176e52ba2d7..a1bdd62efccd 100644
> --- a/drivers/dma-buf/sync_debug.h
> +++ b/drivers/dma-buf/sync_debug.h
> @@ -55,11 +55,13 @@ static inline struct sync_timeline *dma_fence_parent(struct dma_fence *fence)
>    * @base: base fence object
>    * @link: link on the sync timeline's list
>    * @node: node in the sync timeline's tree
> + * @deadline: the earliest fence deadline hint
>    */
>   struct sync_pt {
>   	struct dma_fence base;
>   	struct list_head link;
>   	struct rb_node node;
> +	ktime_t deadline;
>   };
>   
>   extern const struct file_operations sw_sync_debugfs_fops;

Regards,

Tvrtko

WARNING: multiple messages have this Message-ID (diff)
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Rob Clark <robdclark@gmail.com>, dri-devel@lists.freedesktop.org
Cc: "Rob Clark" <robdclark@chromium.org>,
	"Pekka Paalanen" <pekka.paalanen@collabora.com>,
	"Christian König" <ckoenig.leichtzumerken@gmail.com>,
	intel-gfx@lists.freedesktop.org,
	"open list" <linux-kernel@vger.kernel.org>,
	"Sumit Semwal" <sumit.semwal@linaro.org>,
	"moderated list:DMA BUFFER SHARING FRAMEWORK"
	<linaro-mm-sig@lists.linaro.org>,
	"Luben Tuikov" <luben.tuikov@amd.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Gustavo Padovan" <gustavo@padovan.org>,
	"Matt Turner" <mattst88@gmail.com>,
	freedreno@lists.freedesktop.org,
	"Christian König" <christian.koenig@amd.com>,
	"open list:SYNC FILE FRAMEWORK" <linux-media@vger.kernel.org>
Subject: Re: [PATCH v10 07/15] dma-buf/sw_sync: Add fence deadline support
Date: Tue, 28 Mar 2023 14:57:33 +0100	[thread overview]
Message-ID: <f973f656-acdf-320f-95d5-3f79cc3ce95a@linux.intel.com> (raw)
In-Reply-To: <20230308155322.344664-8-robdclark@gmail.com>


On 08/03/2023 15:52, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> This consists of simply storing the most recent deadline, and adding an
> ioctl to retrieve the deadline.  This can be used in conjunction with
> the SET_DEADLINE ioctl on a fence fd for testing.  Ie. create various
> sw_sync fences, merge them into a fence-array, set deadline on the
> fence-array and confirm that it is propagated properly to each fence.
> 
> v2: Switch UABI to express deadline as u64
> v3: More verbose UAPI docs, show how to convert from timespec
> v4: Better comments, track the soonest deadline, as a normal fence
>      implementation would, return an error if no deadline set.
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> Reviewed-by: Christian König <christian.koenig@amd.com>
> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
> ---
>   drivers/dma-buf/sw_sync.c    | 81 ++++++++++++++++++++++++++++++++++++
>   drivers/dma-buf/sync_debug.h |  2 +
>   2 files changed, 83 insertions(+)
> 
> diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c
> index 348b3a9170fa..f53071bca3af 100644
> --- a/drivers/dma-buf/sw_sync.c
> +++ b/drivers/dma-buf/sw_sync.c
> @@ -52,12 +52,33 @@ struct sw_sync_create_fence_data {
>   	__s32	fence; /* fd of new fence */
>   };
>   
> +/**
> + * struct sw_sync_get_deadline - get the deadline hint of a sw_sync fence
> + * @deadline_ns: absolute time of the deadline
> + * @pad:	must be zero
> + * @fence_fd:	the sw_sync fence fd (in)
> + *
> + * Return the earliest deadline set on the fence.  The timebase for the
> + * deadline is CLOCK_MONOTONIC (same as vblank).  If there is no deadline

Mentioning vblank reads odd since this is drivers/dma-buf/. Dunno.

> + * set on the fence, this ioctl will return -ENOENT.
> + */
> +struct sw_sync_get_deadline {
> +	__u64	deadline_ns;
> +	__u32	pad;
> +	__s32	fence_fd;
> +};
> +
>   #define SW_SYNC_IOC_MAGIC	'W'
>   
>   #define SW_SYNC_IOC_CREATE_FENCE	_IOWR(SW_SYNC_IOC_MAGIC, 0,\
>   		struct sw_sync_create_fence_data)
>   
>   #define SW_SYNC_IOC_INC			_IOW(SW_SYNC_IOC_MAGIC, 1, __u32)
> +#define SW_SYNC_GET_DEADLINE		_IOWR(SW_SYNC_IOC_MAGIC, 2, \
> +		struct sw_sync_get_deadline)
> +
> +
> +#define SW_SYNC_HAS_DEADLINE_BIT	DMA_FENCE_FLAG_USER_BITS
>   
>   static const struct dma_fence_ops timeline_fence_ops;
>   
> @@ -171,6 +192,22 @@ static void timeline_fence_timeline_value_str(struct dma_fence *fence,
>   	snprintf(str, size, "%d", parent->value);
>   }
>   
> +static void timeline_fence_set_deadline(struct dma_fence *fence, ktime_t deadline)
> +{
> +	struct sync_pt *pt = dma_fence_to_sync_pt(fence);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(fence->lock, flags);
> +	if (test_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags)) {
> +		if (ktime_before(deadline, pt->deadline))
> +			pt->deadline = deadline;
> +	} else {
> +		pt->deadline = deadline;
> +		set_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags);

FWIW could use __set_bit to avoid needless atomic under spinlock.

> +	}
> +	spin_unlock_irqrestore(fence->lock, flags);
> +}
> +
>   static const struct dma_fence_ops timeline_fence_ops = {
>   	.get_driver_name = timeline_fence_get_driver_name,
>   	.get_timeline_name = timeline_fence_get_timeline_name,
> @@ -179,6 +216,7 @@ static const struct dma_fence_ops timeline_fence_ops = {
>   	.release = timeline_fence_release,
>   	.fence_value_str = timeline_fence_value_str,
>   	.timeline_value_str = timeline_fence_timeline_value_str,
> +	.set_deadline = timeline_fence_set_deadline,
>   };
>   
>   /**
> @@ -387,6 +425,46 @@ static long sw_sync_ioctl_inc(struct sync_timeline *obj, unsigned long arg)
>   	return 0;
>   }
>   
> +static int sw_sync_ioctl_get_deadline(struct sync_timeline *obj, unsigned long arg)
> +{
> +	struct sw_sync_get_deadline data;
> +	struct dma_fence *fence;
> +	struct sync_pt *pt;
> +	int ret = 0;
> +
> +	if (copy_from_user(&data, (void __user *)arg, sizeof(data)))
> +		return -EFAULT;
> +
> +	if (data.deadline_ns || data.pad)
> +		return -EINVAL;
> +
> +	fence = sync_file_get_fence(data.fence_fd);
> +	if (!fence)
> +		return -EINVAL;
> +
> +	pt = dma_fence_to_sync_pt(fence);
> +	if (!pt)
> +		return -EINVAL;
> +
> +	spin_lock(fence->lock);

This may need to be _irq.

> +	if (test_bit(SW_SYNC_HAS_DEADLINE_BIT, &fence->flags)) {
> +		data.deadline_ns = ktime_to_ns(pt->deadline);
> +	} else {
> +		ret = -ENOENT;
> +	}
> +	spin_unlock(fence->lock);
> +
> +	dma_fence_put(fence);
> +
> +	if (ret)
> +		return ret;
> +
> +	if (copy_to_user((void __user *)arg, &data, sizeof(data)))
> +		return -EFAULT;
> +
> +	return 0;
> +}
> +
>   static long sw_sync_ioctl(struct file *file, unsigned int cmd,
>   			  unsigned long arg)
>   {
> @@ -399,6 +477,9 @@ static long sw_sync_ioctl(struct file *file, unsigned int cmd,
>   	case SW_SYNC_IOC_INC:
>   		return sw_sync_ioctl_inc(obj, arg);
>   
> +	case SW_SYNC_GET_DEADLINE:
> +		return sw_sync_ioctl_get_deadline(obj, arg);
> +
>   	default:
>   		return -ENOTTY;
>   	}
> diff --git a/drivers/dma-buf/sync_debug.h b/drivers/dma-buf/sync_debug.h
> index 6176e52ba2d7..a1bdd62efccd 100644
> --- a/drivers/dma-buf/sync_debug.h
> +++ b/drivers/dma-buf/sync_debug.h
> @@ -55,11 +55,13 @@ static inline struct sync_timeline *dma_fence_parent(struct dma_fence *fence)
>    * @base: base fence object
>    * @link: link on the sync timeline's list
>    * @node: node in the sync timeline's tree
> + * @deadline: the earliest fence deadline hint
>    */
>   struct sync_pt {
>   	struct dma_fence base;
>   	struct list_head link;
>   	struct rb_node node;
> +	ktime_t deadline;
>   };
>   
>   extern const struct file_operations sw_sync_debugfs_fops;

Regards,

Tvrtko

  reply	other threads:[~2023-03-28 13:59 UTC|newest]

Thread overview: 148+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-08 15:52 [Intel-gfx] [PATCH v10 00/15] dma-fence: Deadline awareness Rob Clark
2023-03-08 15:52 ` Rob Clark
2023-03-08 15:52 ` Rob Clark
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 01/15] dma-buf/dma-fence: Add deadline awareness Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-10 15:45   ` [Intel-gfx] " Jonas Ådahl
2023-03-10 15:45     ` Jonas Ådahl
2023-03-10 15:45     ` Jonas Ådahl
2023-03-10 17:38     ` [Intel-gfx] " Rob Clark
2023-03-10 17:38       ` Rob Clark
2023-03-10 17:38       ` Rob Clark
2023-03-15 13:53       ` [Intel-gfx] " Jonas Ådahl
2023-03-15 13:53         ` Jonas Ådahl
2023-03-15 13:53         ` Jonas Ådahl
2023-03-15 16:19         ` [Intel-gfx] " Rob Clark
2023-03-15 16:19           ` Rob Clark
2023-03-15 16:19           ` Rob Clark
2023-03-16  9:26           ` [Intel-gfx] " Jonas Ådahl
2023-03-16  9:26             ` Jonas Ådahl
2023-03-16  9:26             ` Jonas Ådahl
2023-03-16 16:28             ` [Intel-gfx] " Rob Clark
2023-03-16 16:28               ` Rob Clark
2023-03-16 16:28               ` Rob Clark
2023-03-16 22:22               ` [Intel-gfx] " Sebastian Wick
2023-03-16 22:22                 ` Sebastian Wick
2023-03-16 22:22                 ` Sebastian Wick
2023-03-16 22:59                 ` [Intel-gfx] " Rob Clark
2023-03-16 22:59                   ` Rob Clark
2023-03-16 22:59                   ` Rob Clark
2023-03-17 15:07                   ` [Intel-gfx] " Sebastian Wick
2023-03-17 15:07                     ` Sebastian Wick
2023-03-17 15:07                     ` Sebastian Wick
2023-03-17  9:09                 ` [Intel-gfx] " Pekka Paalanen
2023-03-17  9:09                   ` Pekka Paalanen
2023-03-17  9:17                   ` [Intel-gfx] " Pekka Paalanen
2023-03-17  9:17                     ` Pekka Paalanen
2023-03-17  9:59                     ` [Intel-gfx] " Pekka Paalanen
2023-03-17  9:59                       ` Pekka Paalanen
2023-03-17  9:10                 ` [Intel-gfx] " Michel Dänzer
2023-03-17  9:10                   ` Michel Dänzer
2023-03-17  9:10                   ` Michel Dänzer
2023-03-17 10:23               ` [Intel-gfx] " Jonas Ådahl
2023-03-17 10:23                 ` Jonas Ådahl
2023-03-17 10:23                 ` Jonas Ådahl
2023-03-17 15:59                 ` [Intel-gfx] " Rob Clark
2023-03-17 15:59                   ` Rob Clark
2023-03-17 15:59                   ` Rob Clark
2023-03-21 13:24                   ` [Intel-gfx] " Jonas Ådahl
2023-03-21 13:24                     ` Jonas Ådahl
2023-03-21 13:24                     ` Jonas Ådahl
2023-03-21 14:34                     ` [Intel-gfx] " Rob Clark
2023-03-21 14:34                       ` Rob Clark
2023-03-21 14:34                       ` Rob Clark
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 02/15] dma-buf/fence-array: Add fence deadline support Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 03/15] dma-buf/fence-chain: " Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 04/15] dma-buf/dma-resv: Add a way to set fence deadline Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 05/15] dma-buf/sync_file: Surface sync-file uABI Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 06/15] dma-buf/sync_file: Add SET_DEADLINE ioctl Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 07/15] dma-buf/sw_sync: Add fence deadline support Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-28 13:57   ` Tvrtko Ursulin [this message]
2023-03-28 13:57     ` Tvrtko Ursulin
2023-03-28 13:57     ` Tvrtko Ursulin
2023-03-08 15:52 ` [Intel-gfx] [PATCH v10 08/15] drm/scheduler: " Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:52   ` Rob Clark
2023-03-08 15:53 ` [Intel-gfx] [PATCH v10 09/15] drm/syncobj: Add deadline support for syncobj waits Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-17 19:08   ` [Intel-gfx] " Faith Ekstrand
2023-03-17 19:08     ` Faith Ekstrand
2023-03-17 19:38     ` Rob Clark
2023-03-17 19:38       ` Rob Clark
2023-03-17 19:38       ` Rob Clark
2023-03-18 16:07     ` Rob Clark
2023-03-18 16:07       ` Rob Clark
2023-03-18 16:07       ` Rob Clark
2023-03-28 14:24   ` Tvrtko Ursulin
2023-03-28 14:24     ` Tvrtko Ursulin
2023-03-08 15:53 ` [Intel-gfx] [PATCH v10 10/15] drm/vblank: Add helper to get next vblank time Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53 ` [Intel-gfx] [PATCH v10 11/15] drm/atomic-helper: Set fence deadline for vblank Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-31 20:44   ` [Intel-gfx] " Nathan Chancellor
2023-03-31 20:44     ` Nathan Chancellor
2023-03-31 20:44     ` Nathan Chancellor
2023-03-31 22:14     ` [Intel-gfx] " Rob Clark
2023-03-31 22:14       ` Rob Clark
2023-03-31 22:14       ` Rob Clark
2023-03-31 23:30       ` [Intel-gfx] " Nathan Chancellor
2023-03-31 23:30         ` Nathan Chancellor
2023-03-31 23:30         ` Nathan Chancellor
2023-04-01 15:39         ` [Intel-gfx] " Rob Clark
2023-04-01 15:39           ` Rob Clark
2023-04-01 15:39           ` Rob Clark
2023-04-04 17:22   ` [Intel-gfx] " Dmitry Baryshkov
2023-04-04 17:22     ` Dmitry Baryshkov
2023-04-04 17:22     ` Dmitry Baryshkov
2023-04-04 19:16     ` [Intel-gfx] " Daniel Vetter
2023-04-04 19:16       ` Daniel Vetter
2023-04-04 19:16       ` Daniel Vetter
2023-04-04 21:53       ` [Intel-gfx] " Dmitry Baryshkov
2023-04-04 21:53         ` Dmitry Baryshkov
2023-04-05  7:58         ` [Intel-gfx] " Daniel Vetter
2023-04-05  7:58           ` Daniel Vetter
2023-04-05  7:58           ` Daniel Vetter
2023-03-08 15:53 ` [Intel-gfx] [PATCH v10 12/15] drm/msm: Add deadline based boost support Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53 ` [Intel-gfx] [PATCH v10 13/15] drm/msm: Add wait-boost support Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53 ` [Intel-gfx] [PATCH v10 14/15] drm/msm/atomic: Switch to vblank_start helper Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53 ` [Intel-gfx] [PATCH v10 15/15] drm/i915: Add deadline based boost support Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-08 15:53   ` Rob Clark
2023-03-09 10:21 ` [Intel-gfx] [PATCH v10 00/15] dma-fence: Deadline awareness Pekka Paalanen
2023-03-09 10:21   ` Pekka Paalanen
2023-03-09 10:21   ` Pekka Paalanen
2023-03-14 11:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2023-03-14 12:18 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-15 16:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-03-16 21:22 ` [Intel-gfx] [PATCH v10 00/15] " Rob Clark
2023-03-16 21:22   ` Rob Clark
2023-03-16 21:22   ` Rob Clark
2023-03-27 19:05 ` [Intel-gfx] " Matt Turner
2023-03-27 19:05   ` Matt Turner
2023-03-27 19:05   ` Matt Turner
2023-04-04 21:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for dma-fence: Deadline awareness (rev2) Patchwork
2023-04-04 21:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-04 21:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-05  5:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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