* [PATCH] pci: zynqmp: Fix the pcireg base
@ 2025-05-16 9:23 Venkatesh Yadav Abbarapu
2025-05-19 6:45 ` Stefan Roese
2025-05-21 13:10 ` Michal Simek
0 siblings, 2 replies; 3+ messages in thread
From: Venkatesh Yadav Abbarapu @ 2025-05-16 9:23 UTC (permalink / raw)
To: u-boot, sr; +Cc: michal.simek, trini, git
The pcireg base is not assigned to any address, reading the
pcireg base with PS_LINKUP_OFFSET which is incorrect and
giving random values. So update the pcireg base from
devicetree so that we can read the valid PCIE link status
and PHY ready status.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
---
drivers/pci/pcie-xilinx-nwl.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c
index 7ef2bdf57b5..e03ab3be912 100644
--- a/drivers/pci/pcie-xilinx-nwl.c
+++ b/drivers/pci/pcie-xilinx-nwl.c
@@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
return PTR_ERR(pcie->breg_base);
pcie->phys_breg_base = res.start;
+ ret = dev_read_resource_byname(dev, "pcireg", &res);
+ if (ret)
+ return ret;
+ pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(pcie->pcireg_base))
+ return PTR_ERR(pcie->pcireg_base);
+
ret = dev_read_resource_byname(dev, "cfg", &res);
if (ret)
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] pci: zynqmp: Fix the pcireg base
2025-05-16 9:23 [PATCH] pci: zynqmp: Fix the pcireg base Venkatesh Yadav Abbarapu
@ 2025-05-19 6:45 ` Stefan Roese
2025-05-21 13:10 ` Michal Simek
1 sibling, 0 replies; 3+ messages in thread
From: Stefan Roese @ 2025-05-19 6:45 UTC (permalink / raw)
To: Venkatesh Yadav Abbarapu, u-boot; +Cc: michal.simek, trini, git
On 16.05.25 11:23, Venkatesh Yadav Abbarapu wrote:
> The pcireg base is not assigned to any address, reading the
> pcireg base with PS_LINKUP_OFFSET which is incorrect and
> giving random values. So update the pcireg base from
> devicetree so that we can read the valid PCIE link status
> and PHY ready status.
>
> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
> ---
> drivers/pci/pcie-xilinx-nwl.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c
> index 7ef2bdf57b5..e03ab3be912 100644
> --- a/drivers/pci/pcie-xilinx-nwl.c
> +++ b/drivers/pci/pcie-xilinx-nwl.c
> @@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
> return PTR_ERR(pcie->breg_base);
> pcie->phys_breg_base = res.start;
>
> + ret = dev_read_resource_byname(dev, "pcireg", &res);
> + if (ret)
> + return ret;
> + pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res));
> + if (IS_ERR(pcie->pcireg_base))
> + return PTR_ERR(pcie->pcireg_base);
> +
> ret = dev_read_resource_byname(dev, "cfg", &res);
> if (ret)
> return ret;
Ah, many thanks for catching.
Reviewed-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] pci: zynqmp: Fix the pcireg base
2025-05-16 9:23 [PATCH] pci: zynqmp: Fix the pcireg base Venkatesh Yadav Abbarapu
2025-05-19 6:45 ` Stefan Roese
@ 2025-05-21 13:10 ` Michal Simek
1 sibling, 0 replies; 3+ messages in thread
From: Michal Simek @ 2025-05-21 13:10 UTC (permalink / raw)
To: Venkatesh Yadav Abbarapu, u-boot, sr; +Cc: trini, git
On 5/16/25 11:23, Venkatesh Yadav Abbarapu wrote:
> The pcireg base is not assigned to any address, reading the
> pcireg base with PS_LINKUP_OFFSET which is incorrect and
> giving random values. So update the pcireg base from
> devicetree so that we can read the valid PCIE link status
> and PHY ready status.
>
> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
> ---
> drivers/pci/pcie-xilinx-nwl.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c
> index 7ef2bdf57b5..e03ab3be912 100644
> --- a/drivers/pci/pcie-xilinx-nwl.c
> +++ b/drivers/pci/pcie-xilinx-nwl.c
> @@ -303,6 +303,13 @@ static int nwl_pcie_parse_dt(struct nwl_pcie *pcie)
> return PTR_ERR(pcie->breg_base);
> pcie->phys_breg_base = res.start;
>
> + ret = dev_read_resource_byname(dev, "pcireg", &res);
> + if (ret)
> + return ret;
> + pcie->pcireg_base = devm_ioremap(dev, res.start, resource_size(&res));
> + if (IS_ERR(pcie->pcireg_base))
> + return PTR_ERR(pcie->pcireg_base);
> +
> ret = dev_read_resource_byname(dev, "cfg", &res);
> if (ret)
> return ret;
Applied.
M
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-05-21 13:11 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2025-05-16 9:23 [PATCH] pci: zynqmp: Fix the pcireg base Venkatesh Yadav Abbarapu
2025-05-19 6:45 ` Stefan Roese
2025-05-21 13:10 ` Michal Simek
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