* [PATCH v5 01/10] rockchip: configs: compile rk3066 SPL with SPL_OF_REAL
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
@ 2026-06-15 21:06 ` Johan Jonker
2026-06-15 21:07 ` [PATCH v5 02/10] usb: Kconfig: add SPL_USB_DWC2 Johan Jonker
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:06 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
Unlike later Rockchip models the rk3066 SOC has no build-in support
for SD/MMC cards in the boot phase. The current workaround in SPL
probes the rockchip_dwmmc driver with OF_PLATDATA. For a simple board
as MK808 with MMC that just works fine, but for more complex boot options
not all required drivers come with OF_PLATDATA support, so compile
rk3066 SPL with SPL_OF_REAL. Update mk808_defconfig.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V5:
rebase
---
configs/mk808_defconfig | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index ea257495db73..31b18c529134 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -16,16 +16,17 @@ CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_ENV_SIZE=0x8000
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3066a-mk808"
CONFIG_DM_RESET=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000
CONFIG_ROCKCHIP_RK3066=y
# CONFIG_ROCKCHIP_STIMER is not set
CONFIG_TPL_TEXT_BASE=0x10080c00
CONFIG_TPL_STACK=0x1008FFFF
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x0800
CONFIG_TARGET_MK808=y
CONFIG_SPL_STACK_R_ADDR=0x70000000
-CONFIG_SPL_STACK=0x1008ffff
CONFIG_SPL_TEXT_BASE=0x60000000
CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000
CONFIG_SYS_LOAD_ADDR=0x70800800
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
@@ -43,9 +44,6 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x32000
CONFIG_SPL_NO_BSS_LIMIT=y
-# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_HAVE_INIT_STACK=y
-CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=2
CONFIG_TPL_HAVE_INIT_STACK=y
@@ -65,7 +63,6 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_OF_DTB_PROPS_REMOVE=y
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 02/10] usb: Kconfig: add SPL_USB_DWC2
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
2026-06-15 21:06 ` [PATCH v5 01/10] rockchip: configs: compile rk3066 SPL with SPL_OF_REAL Johan Jonker
@ 2026-06-15 21:07 ` Johan Jonker
2026-06-15 21:07 ` [PATCH v5 03/10] phy: rockchip: sort Makefile and Kconfig Johan Jonker
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:07 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
The config SPL_DM_USB gives the user the option to be more
selective in what phase the USB drivers should enabled.
Pass this concept to the dwc2_usb driver and make a SPL_USB_DWC2
config available in SPL to load U-Boot (full) from a USB disk.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Note:
There are no boards with SPL_DM_USB and USB_DWC2 enabled,
so no need for a default y.
grep -l SPL_DM_USB `grep -l USB_DWC2 ./configs/*`
Changed V5:
(Marek)
spelling U-Boot
Changed V4:
(Jonas)
reword
replaced deprecated help word
---
drivers/Makefile | 3 ++-
drivers/usb/common/Makefile | 2 +-
drivers/usb/host/Kconfig | 11 +++++++++++
drivers/usb/host/Makefile | 2 +-
4 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index 43d0ba332818..87f755d8a35b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -68,8 +68,9 @@ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
obj-$(CONFIG_SPL_USB_GADGET) += usb/common/
obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/
-obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
+obj-$(CONFIG_SPL_USB_HOST) += usb/common/
obj-$(CONFIG_SPL_USB_HOST) += usb/host/
+obj-$(CONFIG_SPL_WATCHDOG) += watchdog/
obj-$(CONFIG_SPL_SATA) += ata/ scsi/
obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/
obj-$(CONFIG_SPL_THERMAL) += thermal/
diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
index db8f35c10c4f..5350cd668d03 100644
--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
@@ -4,7 +4,7 @@
#
obj-$(CONFIG_$(PHASE_)DM_USB) += common.o
-obj-$(CONFIG_USB_DWC2) += dwc2_core.o
+obj-$(CONFIG_$(PHASE_)USB_DWC2) += dwc2_core.o
obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_core.o
obj-$(CONFIG_USB_ISP1760) += usb_urb.o
obj-$(CONFIG_USB_MUSB_HOST) += usb_urb.o
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d75883e28650..fcea2a22e955 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -417,6 +417,17 @@ config USB_DWC2
operation is compliant to the controller Supplement. If you want to
enable this controller in host mode, say Y.
+config SPL_USB_DWC2
+ bool "DesignWare USB2 Core support in SPL"
+ depends on SPL_DM && SPL_OF_CONTROL
+ select SPL_USB_HOST
+ help
+ The DesignWare USB 2.0 controller is compliant with the
+ USB-Implementers Forum (USB-IF) USB 2.0 specifications.
+ Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
+ operation is compliant to the controller Supplement. If you want to
+ enable this controller in host mode, say Y.
+
if USB_DWC2
config USB_DWC2_BUFFER_SIZE
int "Data buffer size in kB"
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 9cac53f07c7a..950cc8fa0698 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -57,4 +57,4 @@ obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
# designware
-obj-$(CONFIG_USB_DWC2) += dwc2.o
+obj-$(CONFIG_$(PHASE_)USB_DWC2) += dwc2.o
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 03/10] phy: rockchip: sort Makefile and Kconfig
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
2026-06-15 21:06 ` [PATCH v5 01/10] rockchip: configs: compile rk3066 SPL with SPL_OF_REAL Johan Jonker
2026-06-15 21:07 ` [PATCH v5 02/10] usb: Kconfig: add SPL_USB_DWC2 Johan Jonker
@ 2026-06-15 21:07 ` Johan Jonker
2026-06-15 21:07 ` [PATCH v5 04/10] rockchip: bind grf syscon usbphy subnode Johan Jonker
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:07 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
Sort Makefile and Kconfig, so that new phy drivers entries
insert in a clean proper orderly way.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
drivers/phy/rockchip/Kconfig | 27 ++++++++++++++-------------
drivers/phy/rockchip/Makefile | 6 +++---
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 80128335d52f..1662aef0b8fe 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -17,7 +17,7 @@ config PHY_ROCKCHIP_INNO_HDMI
depends on ARCH_ROCKCHIP
select PHY
help
- Enable this to support the Rockchip Innosilicon HDMI PHY.
+ Support for Rockchip Innosilicon HDMI PHY.
config PHY_ROCKCHIP_INNO_USB2
bool "Rockchip INNO USB2PHY Driver"
@@ -27,40 +27,41 @@ config PHY_ROCKCHIP_INNO_USB2
Support for Rockchip USB2.0 PHY with Innosilicon IP block.
config PHY_ROCKCHIP_NANENG_COMBOPHY
- bool "Support Rockchip NANENG combo PHY Driver"
+ bool "Rockchip NANENG combo PHY Driver"
depends on ARCH_ROCKCHIP
select PHY
help
- Enable this to support the Rockchip NANENG combo PHY.
+ Support for Rockchip NANENG combo PHY.
config PHY_ROCKCHIP_PCIE
bool "Rockchip PCIe PHY Driver"
depends on ARCH_ROCKCHIP
select PHY
help
- Enable this to support the Rockchip PCIe PHY.
+ Support for Rockchip PCIe PHY.
config PHY_ROCKCHIP_SNPS_PCIE3
- bool "Rockchip Snps PCIe3 PHY Driver"
- depends on PHY && ARCH_ROCKCHIP
+ bool "Rockchip SNPS PCIe3 PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
help
Support for Rockchip PCIe3 PHY with Synopsys IP block.
It could support PCIe Gen3 single root complex, and could
also be able splited into multiple combinations of lanes.
-config PHY_ROCKCHIP_USBDP
- tristate "Rockchip USBDP COMBO PHY Driver"
+config PHY_ROCKCHIP_TYPEC
+ bool "Rockchip TYPEC PHY Driver"
depends on ARCH_ROCKCHIP
select PHY
help
- Enable this to support the Rockchip USB3.0/DP
- combo PHY with Samsung IP block.
+ Support for Rockchip USB TYPEC PHY.
-config PHY_ROCKCHIP_TYPEC
- bool "Rockchip TYPEC PHY Driver"
+config PHY_ROCKCHIP_USBDP
+ bool "Rockchip USBDP COMBO PHY Driver"
depends on ARCH_ROCKCHIP
select PHY
help
- Enable this to support the Rockchip USB TYPEC PHY.
+ Support for Rockchip USB3.0/DP
+ combo PHY with Samsung IP block.
endmenu
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 04200174254e..b5e4763572bb 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -3,11 +3,11 @@
# Copyright (C) 2020 Amarula Solutions(India)
#
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
-obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
-obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
-obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 04/10] rockchip: bind grf syscon usbphy subnode
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
` (2 preceding siblings ...)
2026-06-15 21:07 ` [PATCH v5 03/10] phy: rockchip: sort Makefile and Kconfig Johan Jonker
@ 2026-06-15 21:07 ` Johan Jonker
2026-06-15 21:07 ` [PATCH v5 05/10] phy: rockchip: add phy-rockchip-usb2.c Johan Jonker
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:07 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
The RK3066/RK3188/RK3288 SoC's have a grf usbphy subnode that
doesn't show up in DM by it's self, so call dm_scan_fdt_dev to
bind grf child devices in the device tree.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 3 +++
arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 3 +++
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 3 +++
3 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
index ff269b53b542..41655d433d26 100644
--- a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
+++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c
@@ -20,6 +20,9 @@ U_BOOT_DRIVER(syscon_rk3066) = {
.name = "rk3066_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3066_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
index 6df054e5b27d..543f078bc659 100644
--- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
+++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
@@ -20,6 +20,9 @@ U_BOOT_DRIVER(syscon_rk3188) = {
.name = "rk3188_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
index 6413d0a88a16..fddb61f419b3 100644
--- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -24,6 +24,9 @@ U_BOOT_DRIVER(syscon_rk3288) = {
.name = "rk3288_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 05/10] phy: rockchip: add phy-rockchip-usb2.c
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
` (3 preceding siblings ...)
2026-06-15 21:07 ` [PATCH v5 04/10] rockchip: bind grf syscon usbphy subnode Johan Jonker
@ 2026-06-15 21:07 ` Johan Jonker
2026-06-15 21:08 ` [PATCH v5 06/10] rockchip: configs: use phy-rockchip-usb2 DM driver Johan Jonker
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:07 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
Add phy-rockchip-usb2.c driver with support
for RK3066, RK3188 and RK3288 pdata.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V5:
remove empty line
Changed V4:
restyle
remove clk
(Jonas)
split Makefile and Kconfig sort
fixup SPL_PHY_ROCKCHIP_USB2
remove DECLARE_GLOBAL_DATA_PTR
add bind rollback
use device_get_supply_regulator
use regulator_set_enable_if_allowed
use reset_assert_bulk functions
init the port in the port probe function
protect against a blank struct
remove of_xlate
remove RESET_ROCKCHIP
Changed V2:
add DM_FLAG_PROBE_AFTER_BIND
restyle
---
drivers/phy/rockchip/Kconfig | 14 ++
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-usb2.c | 234 +++++++++++++++++++++++
3 files changed, 249 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-usb2.c
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 1662aef0b8fe..8b59008a303d 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -56,6 +56,20 @@ config PHY_ROCKCHIP_TYPEC
help
Support for Rockchip USB TYPEC PHY.
+config PHY_ROCKCHIP_USB2
+ bool "Rockchip USB2 PHY"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Support for Rockchip USB 2.0 PHY.
+
+config SPL_PHY_ROCKCHIP_USB2
+ bool "Rockchip USB2 PHY in SPL"
+ depends on ARCH_ROCKCHIP && SPL
+ select SPL_PHY
+ help
+ Support for Rockchip USB 2.0 PHY.
+
config PHY_ROCKCHIP_USBDP
bool "Rockchip USBDP COMBO PHY Driver"
depends on ARCH_ROCKCHIP
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index b5e4763572bb..725c58cf708b 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
+obj-$(CONFIG_$(PHASE_)PHY_ROCKCHIP_USB2) += phy-rockchip-usb2.o
obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
diff --git a/drivers/phy/rockchip/phy-rockchip-usb2.c b/drivers/phy/rockchip/phy-rockchip-usb2.c
new file mode 100644
index 000000000000..fc40a4e232d8
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-usb2.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <generic-phy.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <reset.h>
+
+#define BIT_WRITEABLE_SHIFT 16
+
+struct usb_phy_port_reg {
+ unsigned int offset;
+ unsigned int bitend;
+ unsigned int bitstart;
+ unsigned int disable;
+ unsigned int enable;
+};
+
+struct rockchip_usb_phy_port_cfg {
+ struct usb_phy_port_reg port_reset;
+ struct usb_phy_port_reg soft_con;
+ struct usb_phy_port_reg suspend;
+};
+
+struct rockchip_usb_phy_port_priv {
+ void __iomem *reg_base;
+ u32 reg_offset;
+ struct reset_ctl_bulk resets;
+ struct udevice *vbus_supply;
+ const struct rockchip_usb_phy_port_cfg *port_cfg;
+};
+
+static void rockchip_usb_phy_port_property_enable(struct phy *phy,
+ const struct usb_phy_port_reg *reg,
+ bool en)
+{
+ struct rockchip_usb_phy_port_priv *priv = dev_get_priv(phy->dev);
+ unsigned int val, mask, tmp;
+
+ if (!reg->offset && !reg->enable && !reg->disable)
+ return;
+
+ tmp = en ? reg->enable : reg->disable;
+ mask = GENMASK(reg->bitend, reg->bitstart);
+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
+
+ regmap_write(priv->reg_base, priv->reg_offset + reg->offset, val);
+}
+
+static int rockchip_usb_phy_port_power_on(struct phy *phy)
+{
+ struct rockchip_usb_phy_port_priv *priv = dev_get_priv(phy->dev);
+ const struct rockchip_usb_phy_port_cfg *port_cfg = priv->port_cfg;
+ int ret;
+
+ if (priv->vbus_supply) {
+ ret = regulator_set_enable_if_allowed(priv->vbus_supply, true);
+ if (ret)
+ return ret;
+ }
+
+ /* Exit suspend. */
+ rockchip_usb_phy_port_property_enable(phy, &port_cfg->suspend, false);
+ udelay(2000);
+
+ return 0;
+}
+
+static int rockchip_usb_phy_port_power_off(struct phy *phy)
+{
+ struct rockchip_usb_phy_port_priv *priv = dev_get_priv(phy->dev);
+ const struct rockchip_usb_phy_port_cfg *port_cfg = priv->port_cfg;
+
+ /* Enter suspend. */
+ rockchip_usb_phy_port_property_enable(phy, &port_cfg->suspend, true);
+
+ if (!priv->vbus_supply)
+ return 0;
+
+ return regulator_set_enable_if_allowed(priv->vbus_supply, false);
+}
+
+static int rockchip_usb_phy_port_reset(struct phy *phy)
+{
+ struct rockchip_usb_phy_port_priv *priv = dev_get_priv(phy->dev);
+
+ reset_assert_bulk(&priv->resets);
+ udelay(10);
+ reset_deassert_bulk(&priv->resets);
+
+ return 0;
+}
+
+static int rockchip_usb_phy_port_init(struct phy *phy)
+{
+ struct rockchip_usb_phy_port_priv *priv = dev_get_priv(phy->dev);
+ const struct rockchip_usb_phy_port_cfg *port_cfg = priv->port_cfg;
+
+ /* Disable software control. */
+ rockchip_usb_phy_port_property_enable(phy, &port_cfg->soft_con, false);
+
+ /* Reset OTG port. */
+ rockchip_usb_phy_port_property_enable(phy, &port_cfg->port_reset, true);
+ mdelay(1);
+ rockchip_usb_phy_port_property_enable(phy, &port_cfg->port_reset, false);
+ udelay(1);
+ return 0;
+}
+
+static int rockchip_usb_phy_port_exit(struct phy *phy)
+{
+ struct rockchip_usb_phy_port_priv *priv = dev_get_priv(phy->dev);
+ const struct rockchip_usb_phy_port_cfg *port_cfg = priv->port_cfg;
+
+ /* Enable software control. */
+ rockchip_usb_phy_port_property_enable(phy, &port_cfg->soft_con, true);
+
+ return 0;
+}
+
+static int rockchip_usb_phy_port_probe(struct udevice *dev)
+{
+ struct rockchip_usb_phy_port_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->port_cfg = (const struct rockchip_usb_phy_port_cfg *)
+ dev_get_driver_data(dev_get_parent(dev));
+ if (!priv->port_cfg)
+ return -EINVAL;
+
+ priv->reg_base = dev_read_addr_ptr(dev_get_parent(dev_get_parent(dev)));
+ if (!priv->reg_base)
+ return -EINVAL;
+
+ ret = dev_read_u32(dev, "reg", &priv->reg_offset);
+ if (ret)
+ return ret;
+
+ ret = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply);
+ if (ret && ret != -ENOENT && ret != -ENOSYS) {
+ dev_err(dev, "device_get_supply_regulator failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_bulk(dev, &priv->resets);
+ if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
+ dev_err(dev, "reset_get_bulk failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_usb_phy_bind(struct udevice *dev)
+{
+ const char *name;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, dev) {
+ if (!ofnode_is_enabled(node))
+ continue;
+
+ name = ofnode_get_name(node);
+ dev_dbg(dev, "subnode %s\n", name);
+
+ ret = device_bind_driver_to_node(dev, "rockchip_usb_phy_port",
+ name, node, NULL);
+ if (ret) {
+ dev_err(dev, "'%s' cannot bind 'rockchip_usb_phy_port'\n", name);
+ goto bind_fail;
+ }
+ }
+
+ return 0;
+
+bind_fail:
+ device_chld_unbind(dev, NULL);
+
+ return ret;
+}
+
+static struct phy_ops rockchip_usb_phy_port_ops = {
+ .init = rockchip_usb_phy_port_init,
+ .exit = rockchip_usb_phy_port_exit,
+ .power_on = rockchip_usb_phy_port_power_on,
+ .power_off = rockchip_usb_phy_port_power_off,
+ .reset = rockchip_usb_phy_port_reset,
+};
+
+static const struct rockchip_usb_phy_port_cfg rk3066a_pdata = {
+ .port_reset = {0x00, 12, 12, 0, 1},
+ .soft_con = {0x08, 2, 2, 0, 1},
+ .suspend = {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
+};
+
+static const struct rockchip_usb_phy_port_cfg rk3188_pdata = {
+ .port_reset = {0x00, 12, 12, 0, 1},
+ .soft_con = {0x08, 2, 2, 0, 1},
+ .suspend = {0x0c, 5, 0, 0x01, 0x2A},
+};
+
+static const struct rockchip_usb_phy_port_cfg rk3288_pdata = {
+ .port_reset = {0x00, 12, 12, 0, 1},
+ .soft_con = {0x08, 2, 2, 0, 1},
+ .suspend = {0x0c, 5, 0, 0x01, 0x2A},
+};
+
+static const struct udevice_id rockchip_usb_phy_ids[] = {
+ { .compatible = "rockchip,rk3066a-usb-phy", .data = (ulong)&rk3066a_pdata },
+ { .compatible = "rockchip,rk3188-usb-phy", .data = (ulong)&rk3188_pdata },
+ { .compatible = "rockchip,rk3288-usb-phy", .data = (ulong)&rk3288_pdata },
+ {}
+};
+
+U_BOOT_DRIVER(rockchip_usb_phy_port) = {
+ .name = "rockchip_usb_phy_port",
+ .id = UCLASS_PHY,
+ .ops = &rockchip_usb_phy_port_ops,
+ .probe = rockchip_usb_phy_port_probe,
+ .priv_auto = sizeof(struct rockchip_usb_phy_port_priv),
+};
+
+U_BOOT_DRIVER(rockchip_usb_phy) = {
+ .name = "rockchip_usb_phy",
+ .id = UCLASS_NOP,
+ .of_match = rockchip_usb_phy_ids,
+ .bind = rockchip_usb_phy_bind,
+};
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 06/10] rockchip: configs: use phy-rockchip-usb2 DM driver
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
` (4 preceding siblings ...)
2026-06-15 21:07 ` [PATCH v5 05/10] phy: rockchip: add phy-rockchip-usb2.c Johan Jonker
@ 2026-06-15 21:08 ` Johan Jonker
2026-06-15 21:08 ` [PATCH v5 07/10] usb: phy: remove rockchip_usb2_phy.c Johan Jonker
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:08 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
The new phy-rockchip-usb2 DM driver is now available.
Update defconfigs for RK3066/RK3188/RK3288.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V5:
rebase
Changed V4:
(Jonas)
split patch
remove CONFIG_DM_RESET
---
configs/chromebit_mickey_defconfig | 2 +-
configs/chromebook_jerry_defconfig | 2 +-
configs/chromebook_minnie_defconfig | 2 +-
configs/chromebook_speedy_defconfig | 2 +-
configs/evb-rk3288-rk808_defconfig | 2 +-
configs/firefly-rk3288_defconfig | 2 +-
configs/miqi-rk3288_defconfig | 2 +-
configs/mk808_defconfig | 2 +-
configs/phycore-rk3288_defconfig | 2 +-
configs/popmetal-rk3288_defconfig | 2 +-
configs/rock-pi-n8-rk3288_defconfig | 2 +-
configs/rock2_defconfig | 2 +-
configs/rock_defconfig | 2 +-
configs/tinker-rk3288_defconfig | 2 +-
configs/tinker-s-rk3288_defconfig | 2 +-
configs/vyasa-rk3288_defconfig | 2 +-
16 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 94a744ca005b..0986e99f01c4 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -80,6 +80,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -100,7 +101,6 @@ CONFIG_SYSRESET=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index b02db0d41f9c..7fbd72d1b617 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -80,6 +80,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -104,7 +105,6 @@ CONFIG_SYSRESET=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 0bfa2dfd94df..e3f8500352be 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -81,6 +81,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -105,7 +106,6 @@ CONFIG_SYSRESET=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 6bd272444a1c..3a3024930ff3 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -81,6 +81,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_SPL_PINCTRL=y
@@ -105,7 +106,6 @@ CONFIG_SYSRESET=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
CONFIG_CONSOLE_TRUETYPE=y
diff --git a/configs/evb-rk3288-rk808_defconfig b/configs/evb-rk3288-rk808_defconfig
index 2848a5593d24..842df342e6d4 100644
--- a/configs/evb-rk3288-rk808_defconfig
+++ b/configs/evb-rk3288-rk808_defconfig
@@ -69,6 +69,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -83,7 +84,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_VIDEO=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 58f26f1b1f3c..02b8dcd75899 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -65,6 +65,7 @@ CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -80,7 +81,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 1c03bd14b629..18f6a1a09587 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -62,6 +62,7 @@ CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -77,7 +78,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index 31b18c529134..b8c6f516591a 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -86,6 +86,7 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
@@ -105,7 +106,6 @@ CONFIG_TPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 0c28e298789b..3f8cccc3a377 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -66,6 +66,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -80,7 +81,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index d9471b0288eb..7ade720d044c 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -62,6 +62,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -76,7 +77,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig
index c4fe675920bc..9114184392de 100644
--- a/configs/rock-pi-n8-rk3288_defconfig
+++ b/configs/rock-pi-n8-rk3288_defconfig
@@ -61,6 +61,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -79,7 +80,6 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
# CONFIG_USB_KEYBOARD_FN_KEYS is not set
CONFIG_USB_GADGET=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 9fca00d179d8..ae306b90a9d2 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -63,6 +63,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -78,7 +79,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 4ad4d34a71fe..703a763de4cc 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -52,6 +52,7 @@ CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
@@ -67,7 +68,6 @@ CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_USB=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_RANDOM_UUID=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index b22962786b24..3f5bd8c3cd20 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -65,6 +65,7 @@ CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -79,7 +80,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index 93057cd991b1..9654b346f5ea 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -65,6 +65,7 @@ CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY_REALTEK=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -79,7 +80,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index cfa41d7b35de..30439311c9fd 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -70,6 +70,7 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
@@ -85,7 +86,6 @@ CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
CONFIG_USB_KEYBOARD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 07/10] usb: phy: remove rockchip_usb2_phy.c
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
` (5 preceding siblings ...)
2026-06-15 21:08 ` [PATCH v5 06/10] rockchip: configs: use phy-rockchip-usb2 DM driver Johan Jonker
@ 2026-06-15 21:08 ` Johan Jonker
2026-06-15 21:08 ` [PATCH v5 08/10] rockchip: spl-boot-order: add usb boot option Johan Jonker
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:08 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
The new phy-rockchip-usb2 DM driver is now available,
so remove rockchip_usb2_phy related code. Also remove a
variable no longer needed from an include file.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
(Jonas)
split patch
---
arch/arm/mach-rockchip/board.c | 28 -------
drivers/usb/phy/Kconfig | 3 -
drivers/usb/phy/Makefile | 1 -
drivers/usb/phy/rockchip_usb2_phy.c | 113 ----------------------------
include/usb/dwc2_udc.h | 1 -
5 files changed, 146 deletions(-)
delete mode 100644 drivers/usb/phy/rockchip_usb2_phy.c
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index 2e6bb38b9235..1538f4fef081 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -269,34 +269,6 @@ int board_usb_init(int index, enum usb_init_type init)
}
otg_data.regs_otg = ofnode_get_addr(node);
-#ifdef CONFIG_ROCKCHIP_USB2_PHY
- int ret;
- u32 phandle, offset;
- ofnode phy_node;
-
- ret = ofnode_read_u32(node, "phys", &phandle);
- if (ret)
- return ret;
-
- node = ofnode_get_by_phandle(phandle);
- if (!ofnode_valid(node)) {
- debug("Not found usb phy device\n");
- return -ENODEV;
- }
-
- phy_node = ofnode_get_parent(node);
- if (!ofnode_valid(node)) {
- debug("Not found usb phy device\n");
- return -ENODEV;
- }
-
- otg_data.phy_of_node = phy_node;
- ret = ofnode_read_u32(node, "reg", &offset);
- if (ret)
- return ret;
- otg_data.regs_phy = offset +
- (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-#endif
return dwc2_udc_probe(&otg_data);
}
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index c505862f1e15..9c91f63786ac 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -7,6 +7,3 @@ comment "USB Phy"
config TWL4030_USB
bool "TWL4030 PHY"
-
-config ROCKCHIP_USB2_PHY
- bool "Rockchip USB2 PHY"
diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
index b67a70bbe8ed..cf6109dee610 100644
--- a/drivers/usb/phy/Makefile
+++ b/drivers/usb/phy/Makefile
@@ -4,4 +4,3 @@
# Tom Rix <Tom.Rix@windriver.com>
obj-$(CONFIG_TWL4030_USB) += twl4030.o
-obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o
diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c
deleted file mode 100644
index bdbd0d44813a..000000000000
--- a/drivers/usb/phy/rockchip_usb2_phy.c
+++ /dev/null
@@ -1,113 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#include <hang.h>
-#include <log.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-
-#include "../gadget/dwc2_udc_otg_priv.h"
-
-#define BIT_WRITEABLE_SHIFT 16
-
-struct usb2phy_reg {
- unsigned int offset;
- unsigned int bitend;
- unsigned int bitstart;
- unsigned int disable;
- unsigned int enable;
-};
-
-/**
- * struct rockchip_usb2_phy_cfg: usb-phy port configuration
- * @port_reset: usb otg per-port reset register
- * @soft_con: software control usb otg register
- * @suspend: phy suspend register
- */
-struct rockchip_usb2_phy_cfg {
- struct usb2phy_reg port_reset;
- struct usb2phy_reg soft_con;
- struct usb2phy_reg suspend;
-};
-
-struct rockchip_usb2_phy_dt_id {
- char compatible[128];
- const void *data;
-};
-
-static const struct rockchip_usb2_phy_cfg rk3066a_pdata = {
- .port_reset = {0x00, 12, 12, 0, 1},
- .soft_con = {0x08, 2, 2, 0, 1},
- .suspend = {0x08, 8, 3, (0x01 << 3), (0x2A << 3)},
-};
-
-static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
- .port_reset = {0x00, 12, 12, 0, 1},
- .soft_con = {0x08, 2, 2, 0, 1},
- .suspend = {0x0c, 5, 0, 0x01, 0x2A},
-};
-
-static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
- { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
- { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3288_pdata },
- { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
- {}
-};
-
-static void property_enable(struct dwc2_plat_otg_data *pdata,
- const struct usb2phy_reg *reg, bool en)
-{
- unsigned int val, mask, tmp;
-
- tmp = en ? reg->enable : reg->disable;
- mask = GENMASK(reg->bitend, reg->bitstart);
- val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
-
- writel(val, pdata->regs_phy + reg->offset);
-}
-
-void otg_phy_init(struct dwc2_udc *dev)
-{
- struct dwc2_plat_otg_data *pdata = dev->pdata;
- struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
- struct rockchip_usb2_phy_dt_id *of_id;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
- of_id = &rockchip_usb2_phy_dt_ids[i];
- if (ofnode_device_is_compatible(pdata->phy_of_node,
- of_id->compatible)){
- phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
- break;
- }
- }
- if (!phy_cfg) {
- debug("Can't find device platform data\n");
-
- hang();
- return;
- }
- pdata->priv = phy_cfg;
- /* disable software control */
- property_enable(pdata, &phy_cfg->soft_con, false);
-
- /* reset otg port */
- property_enable(pdata, &phy_cfg->port_reset, true);
- mdelay(1);
- property_enable(pdata, &phy_cfg->port_reset, false);
- udelay(1);
-}
-
-void otg_phy_off(struct dwc2_udc *dev)
-{
- struct dwc2_plat_otg_data *pdata = dev->pdata;
- struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
-
- /* enable software control */
- property_enable(pdata, &phy_cfg->soft_con, true);
- /* enter suspend */
- property_enable(pdata, &phy_cfg->suspend, true);
-}
diff --git a/include/usb/dwc2_udc.h b/include/usb/dwc2_udc.h
index aa37e957b47c..c8610ef8c98a 100644
--- a/include/usb/dwc2_udc.h
+++ b/include/usb/dwc2_udc.h
@@ -15,7 +15,6 @@
struct dwc2_plat_otg_data {
void *priv;
- ofnode phy_of_node;
int (*phy_control)(int on);
uintptr_t regs_phy;
uintptr_t regs_otg;
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 08/10] rockchip: spl-boot-order: add usb boot option
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
` (6 preceding siblings ...)
2026-06-15 21:08 ` [PATCH v5 07/10] usb: phy: remove rockchip_usb2_phy.c Johan Jonker
@ 2026-06-15 21:08 ` Johan Jonker
2026-06-15 21:08 ` [PATCH v5 09/10] arm: dts: rockchip: add USB required properties in SPL for mk808 Johan Jonker
2026-06-15 21:09 ` [PATCH v5 10/10] rockchip: configs: enable USB " Johan Jonker
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:08 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
Add usb boot option to spl-boot-order.c
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V5:
rebase
Changed V4:
(Jonas)
use uclass_find_device_by_of_offset
---
arch/arm/mach-rockchip/spl-boot-order.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index d2dd5e10935f..1ed8c5728f2e 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -79,6 +79,9 @@ static int spl_node_to_boot_device(int node)
if (!uclass_find_device_by_of_offset(UCLASS_UFS, node, &parent))
return BOOT_DEVICE_UFS;
+ if (!uclass_find_device_by_of_offset(UCLASS_USB, node, &parent))
+ return BOOT_DEVICE_USB;
+
return -1;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 09/10] arm: dts: rockchip: add USB required properties in SPL for mk808
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
` (7 preceding siblings ...)
2026-06-15 21:08 ` [PATCH v5 08/10] rockchip: spl-boot-order: add usb boot option Johan Jonker
@ 2026-06-15 21:08 ` Johan Jonker
2026-06-15 21:09 ` [PATCH v5 10/10] rockchip: configs: enable USB " Johan Jonker
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:08 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
Add USB required properties in SPL for mk808.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3066a-mk808-u-boot.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
index dd2eff529e99..ab920272407e 100644
--- a/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
+++ b/arch/arm/dts/rk3066a-mk808-u-boot.dtsi
@@ -2,6 +2,12 @@
#include "rk3066a-u-boot.dtsi"
+/ {
+ chosen {
+ u-boot,spl-boot-order = &mmc0, &usb_host;
+ };
+};
+
&cru {
bootph-all;
};
@@ -41,3 +47,15 @@
&uart2 {
bootph-all;
};
+
+&usb_host {
+ bootph-pre-ram;
+};
+
+&usbphy {
+ bootph-pre-ram;
+};
+
+&usbphy1 {
+ bootph-pre-ram;
+};
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 10/10] rockchip: configs: enable USB in SPL for mk808
2026-06-15 21:05 [PATCH v5 00/10] Add Rockchip USBPHY DM driver Johan Jonker
` (8 preceding siblings ...)
2026-06-15 21:08 ` [PATCH v5 09/10] arm: dts: rockchip: add USB required properties in SPL for mk808 Johan Jonker
@ 2026-06-15 21:09 ` Johan Jonker
9 siblings, 0 replies; 11+ messages in thread
From: Johan Jonker @ 2026-06-15 21:09 UTC (permalink / raw)
To: kever.yang
Cc: sjg, philipp.tomsich, trini, hl, jernej.skrabec, w.egorov, jagan,
heiko, jonas, michael, marex, u-boot, upstream
Enable USB in SPL support for mk808.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V4:
remove SPL_DM_RESET
---
configs/mk808_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index b8c6f516591a..97246dacff3e 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -87,6 +87,7 @@ CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_USB2=y
+CONFIG_SPL_PHY_ROCKCHIP_USB2=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
@@ -106,6 +107,8 @@ CONFIG_TPL_TIMER=y
CONFIG_DESIGNWARE_APB_TIMER=y
CONFIG_USB=y
CONFIG_USB_DWC2=y
+CONFIG_SPL_USB_DWC2=y
+CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_FUNCTION_ROCKUSB=y
--
2.39.5
^ permalink raw reply related [flat|nested] 11+ messages in thread