Re: [PATCH 1/2] target/riscv: Add the implied rule for G extension

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

On 5/14/25 1:11 AM, frank.chang@sifive.com wrote:
> From: Jim Shu <jim.shu@sifive.com>
> 
> Add the missing implied rule from G to imafd_zicsr_zifencei.
> 
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---


Patch LGTM. I believe this will deprecate everything we're doing in
riscv_cpu_validate_g() in tcg-cpu.c and we should remove it in this same
patch.


Thanks,

Daniel

>   target/riscv/cpu.c | 14 +++++++++++++-
>   1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d92874baa0..27edd5af62 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2520,6 +2520,18 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
>       },
>   };
>   
> +static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
> +    .is_misa = true,
> +    .ext = RVG,
> +    .implied_misa_exts = RVI | RVM | RVA | RVF | RVD,
> +    .implied_multi_exts = {
> +        CPU_CFG_OFFSET(ext_zicsr),
> +        CPU_CFG_OFFSET(ext_zifencei),
> +
> +        RISCV_IMPLIED_EXTS_RULE_END
> +    },
> +};
> +
>   static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
>       .ext = CPU_CFG_OFFSET(ext_zcb),
>       .implied_multi_exts = {
> @@ -2898,7 +2910,7 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
>   
>   RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
>       &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> -    &RVM_IMPLIED, &RVV_IMPLIED, NULL
> +    &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
>   };
>   
>   RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {