[PATCH v2 0/3] Enable serial NOR flash on RZ/G2UL SMARC EVK

[PATCH v2 0/3] Enable serial NOR flash on RZ/G2UL SMARC EVK

[Biju Das]

This patch series aims to enable serial NOR flash on RZ/G2UL SMARC EVK.

The RZ/{G2L,G2LC,V2L} SMARC EVK uses Micron MT25QU412A flash and RZ/G2UL
SMARC EVK uses Renesas AT25QL128A flash. With current pin setting for
IOVF pin, 4-bit flash write fails for AT25QL128A flash. Use Hi-Z state
as the default for IOVF pins, so that spi controller driver in linux will
be independent of flash type.

To support this, during board production, the bit 4 of the NV config
register must be cleared by the bootloader for Micron flash.

Output from u-boot after clearing bit4 of NVCR register.
=> renesas_micron_flash_nvcr
SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB

Update partition table for spi-nor flash, so that we can flash bootloaders
in Linux by executing the below commands:
flash_erase /dev/mtd0  0 0
flash_erase /dev/mtd1  0 0
mtd_debug write /dev/mtd0 0 ${BL2_FILE_SIZE} ${BL2_IMAGE}
mtd_debug write /dev/mtd1 512 ${FIP_FILE_SIZE} ${FIP_IMAGE}

RFC->v1:
 * Dropped patches related to set_iofv() callback
 * Used Hi-Z state as the default for IOVF pin state.
 * Enabled Serial NOR flash on RZ/G2UL SMARC EVK
 * Updated partition table on RZ/{G2L,G2LC,V2L} SMARC EVK in order to
   flash bootloader images from Linux.
 
RFC: https://lore.kernel.org/linux-renesas-soc/e8ed909b39b5a7de46a07d2b57c0393a@walle.cc/T/#t

Biju Das (3):
  memory: renesas-rpc-if: Use Hi-Z state as the default for IOVF pin
  arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash
  arm64: dts: renesas: rz{g2l,g2lc}-smarc-som: Update partition table
    for spi-nor flash

 .../boot/dts/renesas/rzg2l-smarc-som.dtsi     | 15 ++++--
 .../boot/dts/renesas/rzg2lc-smarc-som.dtsi    | 15 ++++--
 .../boot/dts/renesas/rzg2ul-smarc-som.dtsi    | 48 +++++++++++++++++++
 drivers/memory/renesas-rpc-if.c               |  2 +-
 4 files changed, 71 insertions(+), 9 deletions(-)

-- 
2.43.0

[PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins

[Biju Das]

The RZ/{G2L,G2LC,V2L} SMARC EVK uses Micron MT25QU412A flash and RZ/G2UL
SMARC EVK uses Renesas AT25QL128A flash. With current pin setting for
IOVF pin, 4-bit flash write fails for AT25QL128A flash. Use Hi-Z state
as the default for IOVF pin, so that spi controller driver in linux will
be independent of flash type.

To support this, during board production, the bit 4 of the NV config
register must be cleared by the bootloader for Micron flash.

Output from u-boot after clearing bit4 of NVCR register.
=> renesas_micron_flash_nvcr
SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
NVCR=0xef

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
RFC->v1:
 * New patch.
---
 drivers/memory/renesas-rpc-if.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c
index 3167826b236a..7fbd36fa1a1b 100644
--- a/drivers/memory/renesas-rpc-if.c
+++ b/drivers/memory/renesas-rpc-if.c
@@ -367,7 +367,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash)
 		regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
 				   RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
 				   RPCIF_CMNCR_BSZ(3),
-				   RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
+				   RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(3) |
 				   RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
 	else
 		regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
-- 
2.43.0

[PATCH v2 2/3] arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash

[Biju Das]

Enable Renesas at25ql128a flash connected to QSPI0.

Tested the flash by flashing bootloaders:
flash_erase /dev/mtd0  0 0
flash_erase /dev/mtd1  0 0
mtd_debug write /dev/mtd0 0 ${BL2_FILE_SIZE} ${BL2_IMAGE}
mtd_debug write /dev/mtd1 512 ${FIP_FILE_SIZE} ${FIP_IMAGE}

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2:
 * New patch.
---
 .../boot/dts/renesas/rzg2ul-smarc-som.dtsi    | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 97cdad2a12e2..db41970ac9a0 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -179,6 +179,18 @@ eth1_pins: eth1 {
 			 <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
 	};
 
+	qspi0_pins: qspi0 {
+		qspi0-data {
+			pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
+			power-source = <1800>;
+		};
+
+		qspi0-ctrl {
+			pins = "QSPI0_SPCLK", "QSPI0_SSL";
+			power-source = <1800>;
+		};
+	};
+
 	sdhi0_emmc_pins: sd0emmc {
 		sd0_emmc_data {
 			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
@@ -230,6 +242,42 @@ sd0_mux_uhs {
 	};
 };
 
+&sbc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		m25p,fast-read;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x00000000 0x0001c000>;
+			};
+
+			partition@1d000 { /* fip is at offset 0x200 */
+				label = "fip";
+				reg = <0x0001d000 0x7e3000>;
+			};
+
+			partition@800000 {
+				label = "user";
+				reg = <0x800000 0x800000>;
+			};
+		};
+	};
+};
+
 #if (SW_SW0_DEV_SEL)
 &sdhi0 {
 	pinctrl-0 = <&sdhi0_emmc_pins>;
-- 
2.43.0

[PATCH v2 3/3] arm64: dts: renesas: rz{g2l,g2lc}-smarc-som: Update partition table for spi-nor flash

[Biju Das]

Update partition table for spi-nor flash, so that we can flash bootloaders
in Linux by executing the below commands:
flash_erase /dev/mtd0  0 0
flash_erase /dev/mtd1  0 0
mtd_debug write /dev/mtd0 0 ${BL2_FILE_SIZE} ${BL2_IMAGE}
mtd_debug write /dev/mtd1 512 ${FIP_FILE_SIZE} ${FIP_IMAGE}

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2:
 New patch.
---
 arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi  | 15 +++++++++++----
 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 15 +++++++++++----
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 4409c47239b9..09ff0c092f0c 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -319,11 +319,18 @@ partitions {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			boot@0 {
-				reg = <0x00000000 0x2000000>;
-				read-only;
+			partition@0 {
+				label = "bl2";
+				reg = <0x00000000 0x0001c000>;
 			};
-			user@2000000 {
+
+			partition@1d000 { /* fip is at offset 0x200 */
+				label = "fip";
+				reg = <0x0001d000 0x1fe3000>;
+			};
+
+			partition@2000000 {
+				label = "user";
 				reg = <0x2000000 0x2000000>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
index 5e4209d6fb42..66b5db3cf1f7 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
@@ -248,11 +248,18 @@ partitions {
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			boot@0 {
-				reg = <0x00000000 0x2000000>;
-				read-only;
+			partition@0 {
+				label = "bl2";
+				reg = <0x00000000 0x0001c000>;
 			};
-			user@2000000 {
+
+			partition@1d000 { /* fip is at offset 0x200 */
+				label = "fip";
+				reg = <0x0001d000 0x1fe3000>;
+			};
+
+			partition@2000000 {
+				label = "user";
 				reg = <0x2000000 0x2000000>;
 			};
 		};
-- 
2.43.0

RE: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins

[Biju Das]

Hi Krzysztof Kozlowski, Michael,

Gentle ping. Are you happy with this patch? or do you have different opinion?

This patch is based on RFC discussion [1]

[1] RFC: https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc/

Cheers,
Biju

> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: Wednesday, July 3, 2024 3:59 PM
> To: Krzysztof Kozlowski <krzk@kernel.org>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; Geert Uytterhoeven <geert+renesas@glider.be>; Michael Walle
> <michael@walle.cc>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; biju.das.au
> <biju.das.au@gmail.com>; linux-renesas-soc@vger.kernel.org
> Subject: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins
> 
> The RZ/{G2L,G2LC,V2L} SMARC EVK uses Micron MT25QU412A flash and RZ/G2UL SMARC EVK uses Renesas
> AT25QL128A flash. With current pin setting for IOVF pin, 4-bit flash write fails for AT25QL128A flash.
> Use Hi-Z state as the default for IOVF pin, so that spi controller driver in linux will be independent
> of flash type.
> 
> To support this, during board production, the bit 4 of the NV config register must be cleared by the
> bootloader for Micron flash.
> 
> Output from u-boot after clearing bit4 of NVCR register.
> => renesas_micron_flash_nvcr
> SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB NVCR=0xef
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> RFC->v1:
>  * New patch.
> ---
>  drivers/memory/renesas-rpc-if.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index
> 3167826b236a..7fbd36fa1a1b 100644
> --- a/drivers/memory/renesas-rpc-if.c
> +++ b/drivers/memory/renesas-rpc-if.c
> @@ -367,7 +367,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash)
>  		regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
>  				   RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
>  				   RPCIF_CMNCR_BSZ(3),
> -				   RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
> +				   RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(3) |
>  				   RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
>  	else
>  		regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
> --
> 2.43.0

Re: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins

[Krzysztof Kozlowski]

On 28/08/2024 19:02, Biju Das wrote:
> Hi Krzysztof Kozlowski, Michael,
> 
> Gentle ping. Are you happy with this patch? or do you have different opinion?
> 
> This patch is based on RFC discussion [1]
> 
> [1] RFC: https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc/

sorry, I don't have this patch in the inbox (anything older than 1 month
disappears). Even if it reached me, it was an reply to unrelated
patchset, so it could have been applied. And probably - due to being
inside other thread - got immediately discarded.

Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets.

Please resend.

Best regards,
Krzysztof

Re: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins

[Krzysztof Kozlowski]

On 30/08/2024 12:46, Krzysztof Kozlowski wrote:
> On 28/08/2024 19:02, Biju Das wrote:
>> Hi Krzysztof Kozlowski, Michael,
>>
>> Gentle ping. Are you happy with this patch? or do you have different opinion?
>>
>> This patch is based on RFC discussion [1]
>>
>> [1] RFC: https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc/
> 
> sorry, I don't have this patch in the inbox (anything older than 1 month
> disappears). Even if it reached me, it was an reply to unrelated
> patchset, so it could have been applied. And probably - due to being

"so it could have not been applied."

> inside other thread - got immediately discarded.
> 
> Do not attach (thread) your patchsets to some other threads (unrelated
> or older versions). This buries them deep in the mailbox and might
> interfere with applying entire sets.
> 
> Please resend.

Maybe the threading was correct, but I missed it because of my DT
filters. I don't know. Sorry for that, please resend.

Best regards,
Krzysztof

RE: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins

[Biju Das]

Hi Krzysztof Kozlowski,

Thanks for the feedback.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Friday, August 30, 2024 11:50 AM
> Subject: Re: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins
> 
> On 30/08/2024 12:46, Krzysztof Kozlowski wrote:
> > On 28/08/2024 19:02, Biju Das wrote:
> >> Hi Krzysztof Kozlowski, Michael,
> >>
> >> Gentle ping. Are you happy with this patch? or do you have different opinion?
> >>
> >> This patch is based on RFC discussion [1]
> >>
> >> [1] RFC:
> >> https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc
> >> /
> >
> > sorry, I don't have this patch in the inbox (anything older than 1
> > month disappears). Even if it reached me, it was an reply to unrelated
> > patchset, so it could have been applied. And probably - due to being
> 
> "so it could have not been applied."
> 
> > inside other thread - got immediately discarded.
> >
> > Do not attach (thread) your patchsets to some other threads (unrelated
> > or older versions). This buries them deep in the mailbox and might
> > interfere with applying entire sets.
> >
> > Please resend.
> 
> Maybe the threading was correct, but I missed it because of my DT filters. I don't know. Sorry for
> that, please resend.


Sure. Will resend.

Cheers,
Biju